	*************************************************
	*                                               *
	*          ONE-View report generation           *
	*                                               *
	*************************************************

[MAQAO] Info: Experiment configuration summary is available adding -dbg=1 in command line

* [MAQAO] Warning: Experiment directory /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/run/oneview_runs/defaults/armclang/oneview_results_1782312114 already exists and is reused.
           It can be replaced using --replace in the command line.
[MAQAO] Info: 
[MAQAO] Info: START THE APPLICATION PROFILING
[MAQAO] Info: -> RUNNING THE PROFILER...
[MAQAO] Info:   LPROF has already been run
[MAQAO] Info: STOP THE APPLICATION PROFILING
[MAQAO] Info: 
[MAQAO] Info: START FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: STOP FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: 
[MAQAO] Info: START THE REPORT GENERATION
[MAQAO] Info: -> ONE-VIEW EXPERIMENT DIRECTORY: /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/run/oneview_runs/defaults/armclang/oneview_results_1782312114


+===================================================================================================================+
+                                                   1  -  GLOBAL                                                    +
+===================================================================================================================+


+-------------------------------------------------------------------------------------------------------------------+
+                                            1.1  -  Experiment Summary                                             +
+-------------------------------------------------------------------------------------------------------------------+

  Application:			/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/run/oneview_runs/defaults/orig/exec
  Timestamp:			2026-06-24 14:41:54
  Universal Timestamp:		1782312114
  Experiment Type:		MPI; OpenMP; Throughput; 
  Machine:			ip-172-31-38-240.ec2.internal
  Architecture:			aarch64
  Micro Architecture:		ARM_NEOVERSE_V1
  OS Version:			Linux 6.1.170-213.321.amzn2023.aarch64 #1 SMP Thu May 14 12:18:13 UTC 2026
  Compilation Options:		
		exec: Arm Toolchain for Linux 22.1.0 flang version 22.1.0 (https://github.com/arm/arm-toolchain.git c95792353373404441df364b5a762338e5642230) 
  Number of processes observed:	1
  Number of threads observed:	64
  MAQAO version:		2026.0.0
  MAQAO build:			Build information not available




+-------------------------------------------------------------------------------------------------------------------+
+                                              1.2  -  Global Metrics                                               +
+-------------------------------------------------------------------------------------------------------------------+

  Total Time:				140.17 s
  Max (Thread Active Time):		136.59 s
  Average Active Time:			136.57 s
  Activity Ratio:			99.9 %
  Average number of active threads:	62.357
  Affinity Stability:			100.0 %
  Time spent in analyzed loops:		97.1 %
  Time spent in analyzed innermost loops: 51.7 %
  Time spent in user code:		97.3 %
  Compilation Options Score:		16.67
  Array Access Efficiency:		16.3 %

   Potential Speedups
  ----------------------------------------------------
  Perfect Flow Complexity:		1.02
  Perfect OpenMP/MPI/Pthread/TBB:	1.00
  Perfect OpenMP/MPI/Pthread/TBB + Load Distribution:	1.01
  If No Scalar Integer:
      Potential Speedup:		1.14
      Nb Loops to get 80%:		4
  If FP Vectorized:
      Potential Speedup:		1.08
      Nb Loops to get 80%:		4
  If Fully Vectorized:
      Potential Speedup:		1.10
      Nb Loops to get 80%:		4
  If Only FP Arithmetic:
      Potential Speedup:		1.21
      Nb Loops to get 80%:		13




+-------------------------------------------------------------------------------------------------------------------+
+                                            1.3  -  Potential Speedups                                             +
+-------------------------------------------------------------------------------------------------------------------+

  If No Scalar Integer:
      Number of loops   | 1      | 8      | 17     | 25     | 34     | 
      Cumulated Speedup | 1.0293 | 1.1374 | 1.1374 | 1.1374 | 1.1374 | 
  Top 5 loops:
    exec - 148:	1.0293
    exec - 83:	1.0595
    exec - 156:	1.0914
    exec - 76:	1.1154
    exec - 243:	1.1374

  If FP Vectorized:
      Number of loops   | 1      | 8      | 17     | 25     | 34     | 
      Cumulated Speedup | 1.0186 | 1.0809 | 1.0809 | 1.0809 | 1.0809 | 
  Top 5 loops:
    exec - 156:	1.0186
    exec - 148:	1.0375
    exec - 83:	1.0555
    exec - 243:	1.0701
    exec - 76:	1.0809

  If Fully Vectorized:
      Number of loops   | 1      | 8      | 17     | 25     | 34     | 
      Cumulated Speedup | 1.0256 | 1.0972 | 1.0972 | 1.0972 | 1.0972 | 
  Top 5 loops:
    exec - 83:	1.0256
    exec - 148:	1.0447
    exec - 76:	1.0638
    exec - 156:	1.0813
    exec - 243:	1.0966

  If Only FP Arithmetic:
      Number of loops   | 1      | 8      | 17     | 25     | 34     | 
      Cumulated Speedup | 1.0174 | 1.1209 | 1.1984 | 1.2081 | 1.2081 | 
  Top 5 loops:
    exec - 163:	1.0174
    exec - 172:	1.0347
    exec - 169:	1.0517
    exec - 83:	1.0668
    exec - 157:	1.0814



+===================================================================================================================+
+                                                   2  -  SUMMARY                                                   +
+===================================================================================================================+


+-------------------------------------------------------------------------------------------------------------------+
+                                            2.1  -  EXPERIMENT QUALITY                                             +
+-------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Application profile is long enough (136.59 s)
To have good quality measurements, it is advised that the application profiling time is greater than 10 seconds.

  [3 / 3] Most of time spent in analyzed modules comes from functions with source/debug info
-g option gives access to debugging informations, such are source locations.

  [0 / 3] Architecture specific options are unknown for some functions (compilation options info are not available)
Architecture specific options are needed to produce efficient code for a specific processor ( -mcpu=native ).

  [0 / 3] Most of time spent in analyzed modules comes from functions without compilation options informations
Functions without compilation options information cumulate 97.25% of the time spent in analyzed modules. For exec,
check that both -g and -frecord-command-line are present. Remark: if such options are indeed used, this can also be
due to some compiler built-in functions (typically math) or statically linked libraries. This warning can be ignored
in that case.

  [0 / 3] Optimization level is unknown for some functions (compilation options info are not available)
To have better performances, it is advised to help the compiler by using a proper optimization level (-O2 of higher).
Warning, depending on compilers, faster optimization levels can decrease numeric accuracy.

  [3 / 3] Host configuration allows retrieval of all necessary metrics.


  [2 / 2] Application is correctly profiled ("Others" category represents 0.00 % of the execution time)
To have a representative profiling, it is advised that the category "Others" represents less than 20% of the
execution time in order to analyze as much as possible of the user code

  [1 / 1] Lstopo present. The Topology lstopo report will be generated.



+-------------------------------------------------------------------------------------------------------------------+
+                                               2.2  -  CODE QUALITY                                                +
+-------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Enough time of the experiment time spent in analyzed loops (97.10%)
If the time spent in analyzed loops is less than 30%, standard loop optimizations will have a limited impact on
application performances.

  [4 / 4] Threads activity is good
On average, more than 97.43% of observed threads are actually active 

  [4 / 4] CPU activity is good
CPU cores are active 99.85% of time

  [4 / 4] Loop profile is not flat
At least one loop coverage is greater than 4% (7.91%), representing an hotspot for the application

  [4 / 4] Enough time of the experiment time spent in analyzed innermost loops (51.74%)
If the time spent in analyzed innermost loops is less than 15%, standard innermost loop optimizations such as
vectorisation will have a limited impact on application performances.

  [4 / 4] Affinity is good (99.95%)
Threads are not migrating to CPU cores: probably successfully pinned

  [3 / 3] Less than 10% (0.00%) is spend in BLAS1 operations
It could be more efficient to inline by hand BLAS1 operations

  [3 / 3] Functions mostly use all threads
Functions running on a reduced number of threads (typically sequential code) cover less than 10% of application
walltime (1.08%)

  [3 / 3] Cumulative Outermost/In between loops coverage (45.36%) lower than cumulative innermost loop coverage (51.74%)
Having cumulative Outermost/In between loops coverage greater than cumulative innermost loop coverage will make loop
optimization more complex

  [2 / 2] Less than 10% (0.00%) is spend in BLAS2 operations
BLAS2 calls usually could make a poor cache usage and could benefit from inlining.

  [2 / 2] Less than 10% (0.00%) is spend in Libm/SVML (special functions)



+-------------------------------------------------------------------------------------------------------------------+
+                                              2.3  -  LOOPS OVERVIEW                                               +
+-------------------------------------------------------------------------------------------------------------------+

  Top 5 loops:
   + exec - 41  :
     analysis: Execution Time: 7 % - Vectorization Ratio: 96.77 % - Vector Length Use: 98.59 %
     Loop Computation Issues: 16
        [16] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 4
            issues (= instructions) costing 4 points each.
     Data Access Issues: 56
        [56] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 14 issues ( = indirect data accesses) costing 4 point each.
     Vectorization Roadblocks: 56
        [56] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 14 issues ( = indirect data accesses) costing 4 point each.

   + exec - 62  :
     analysis: Execution Time: 7 % - Vectorization Ratio: 98.25 % - Vector Length Use: 98.46 %
     Loop Computation Issues: 4
        [4] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 1
            issues (= instructions) costing 4 points each.
     Data Access Issues: 60
        [60] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 15 issues ( = indirect data accesses) costing 4 point each.
     Vectorization Roadblocks: 60
        [60] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 15 issues ( = indirect data accesses) costing 4 point each.

   + exec - 44  :
     analysis: Execution Time: 6 % - Vectorization Ratio: 96.55 % - Vector Length Use: 98.49 %
     Loop Computation Issues: 16
        [16] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 4
            issues (= instructions) costing 4 points each.
     Control Flow Issues: 2
        [2] [SA] Non innermost loop (Outermost) - Collapse loop with innermost ones. This issue costs 2 points.
     Vectorization Roadblocks: 1002
        [1000] [SA] Too many paths (at least 1000 paths) - Simplify control structure. There are at least 1000 issues (
            = paths) costing 1 point.
        [2] [SA] Non innermost loop (Outermost) - Collapse loop with innermost ones. This issue costs 2 points.

   + exec - 152 :
     analysis: Execution Time: 4 % - Vectorization Ratio: 90.00 % - Vector Length Use: 91.25 %
     Loop Computation Issues: 4
        [4] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 1
            issues (= instructions) costing 4 points each.
     Data Access Issues: 20
        [20] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 5 issues ( = indirect data accesses) costing 4 point each.
     Vectorization Roadblocks: 20
        [20] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 5 issues ( = indirect data accesses) costing 4 point each.

   + exec - 271 :
     analysis: Execution Time: 4 % - Vectorization Ratio: 91.67 % - Vector Length Use: 93.23 %
     Loop Computation Issues: 4
        [4] [SA] Less than 10% of the FP ADD/SUB/MUL arithmetic operations are performed using FMA - Reorganize
            arithmetic expressions to exhibit potential for FMA. This issue costs 4 points.
     Data Access Issues: 32
        [32] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 8 issues ( = indirect data accesses) costing 4 point each.
     Vectorization Roadblocks: 32
        [32] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 8 issues ( = indirect data accesses) costing 4 point each.



+===================================================================================================================+
+                                                 3  -  APPLICATION                                                 +
+===================================================================================================================+


+-------------------------------------------------------------------------------------------------------------------+
+                                              3.1  -  Categorization                                               +
+-------------------------------------------------------------------------------------------------------------------+

   Category | IO     | Exe    | Others  | TBB   | String | Pthread | MPI   | OMP   | System | Memory | Math  |
  ----------+--------+--------+---------+-------+--------+---------+-------+-------+--------+--------+-------+
   Time (%) | 0.00   | 97.26  | 0.00    | 0.00  | 0.00   | 0.00    | 0.00  | 1.26  | 1.49   | 0.00   | 0.00  |




+-------------------------------------------------------------------------------------------------------------------+
+                                         3.2  -  Function Based Profiling                                          +
+-------------------------------------------------------------------------------------------------------------------+

   Buckets                   | Nb Functions              | Coverage                  | Cumulated Coverage        |
  ---------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                      | 3                         | 68.04                     | 68.04                     |
   4% to 8%                  | 4                         | 20.25                     | 88.29                     |
   2% to 4%                  | 2                         | 6.48                      | 94.77                     |
   1% to 2%                  | 1                         | 1.98                      | 96.75                     |
   0.5% to 1%                | 2                         | 1.68                      | 98.43                     |
   0.25% to 0.5%             | 2                         | 0.66                      | 99.09                     |
   0.125% to 0.25%           | 2                         | 0.36                      | 99.45                     |
   < 0.125%                  | 33                        | 0.47                      | 99.92                     |




+-------------------------------------------------------------------------------------------------------------------+
+                                           3.3  -  Loop Based Profiling                                            +
+-------------------------------------------------------------------------------------------------------------------+

   Buckets                   | Nb Loops                  | Coverage                  | Cumulated Coverage        |
  ---------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                      | 0                         | 0.00                      | 0.00                      |
   4% to 8%                  | 6                         | 32.78                     | 32.78                     |
   2% to 4%                  | 5                         | 15.18                     | 47.96                     |
   1% to 2%                  | 3                         | 3.35                      | 51.31                     |
   0.5% to 1%                | 0                         | 0.00                      | 51.31                     |
   0.25% to 0.5%             | 1                         | 0.33                      | 51.65                     |
   0.125% to 0.25%           | 0                         | 0.00                      | 51.65                     |
   < 0.125%                  | 15                        | 0.09                      | 51.74                     |


+===================================================================================================================+
+                                                  4  -  FUNCTIONS                                                  +
+===================================================================================================================+


+-------------------------------------------------------------------------------------------------------------------+
+                                             4.1  -  Top 10 Functions                                              +
+-------------------------------------------------------------------------------------------------------------------+

   Function                                               | Module               | Coverage (%)  | Time (s)      |
  --------------------------------------------------------+----------------------+---------------+---------------+
   _QMadvec_mom_kernel_modPadvec_mom_kernel..omp_par      | exec                 | 35.05         | 47.86         |
   _QMadvec_cell_kernel_modulePadvec_cell_kernel..omp_par | exec                 | 18.70         | 25.54         |
   _QMpdv_kernel_modulePpdv_kernel..omp_par               | exec                 | 14.30         | 19.52         |
   _QMaccelerate_kernel_modulePaccelerate_kernel..omp_par | exec                 | 7.04          | 9.62          |
   _QMflux_calc_kernel_modulePflux_calc_kernel..omp_par   | exec                 | 4.60          | 6.28          |
   _QMcalc_dt_kernel_modulePcalc_dt_kernel..omp_par       | exec                 | 4.43          | 6.06          |
   _QMideal_gas_kernel_modulePideal_gas_kernel..omp_par   | exec                 | 4.18          | 5.71          |
   _QMreset_field_kernel_modulePreset_field_kernel..om... | exec                 | 3.99          | 5.45          |
   _QMviscosity_kernel_modulePviscosity_kernel..omp_par   | exec                 | 2.49          | 3.40          |
   _QMrevert_kernel_modulePrevert_kernel..omp_par         | exec                 | 1.98          | 2.70          |


+===================================================================================================================+
+                                                    5  -  LOOPS                                                    +
+===================================================================================================================+


+-------------------------------------------------------------------------------------------------------------------+
+                                               5.1  -  Top 10 Loops                                                +
+-------------------------------------------------------------------------------------------------------------------+

   Loop Id        | Module               | Source Location                                       | Coverage (%)  |
  ----------------+----------------------+-------------------------------------------------------+---------------+
   41             | exec                 | PdV_kernel.f90:110-123,PdV_kernel.f90:129-135         | 7.91          |
   62             | exec                 | accelerate_kernel.f90:61-63,accelerate_kernel.f90:... | 7.03          |
   44             | exec                 | PdV_kernel.f90:74-74,PdV_kernel.f90:77-87,PdV_kern... | 6.38          |
   152            | exec                 | advec_mom_kernel.f90:246-248                          | 4.64          |
   271            | exec                 | flux_calc_kernel.f90:55-59                            | 4.60          |
   145            | exec                 | advec_mom_kernel.f90:182-184                          | 4.43          |
   351            | exec                 | ideal_gas_kernel.f90:48-55                            | 4.18          |
   80             | exec                 | advec_cell_kernel.f90:254-261                         | 3.99          |
   156            | exec                 | advec_mom_kernel.f90:214-215,advec_mom_kernel.f90:... | 3.79          |
   83             | exec                 | advec_cell_kernel.f90:199-204,advec_cell_kernel.f9... | 3.65          |





+===================================================================================================================+
+                                                     6  -  CQA                                                     +
+===================================================================================================================+


+-------------------------------------------------------------------------------------------------------------------+
+                                                   6.1  -  Loops                                                   +
+-------------------------------------------------------------------------------------------------------------------+





      6.1.1  -  Loop 41 from exec
  =========================================================================================================

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:110-123,129-135.

The related source loop is unrolled by 4 (including vectorization).

      6.1.1.1  -  Path 1
  ---------------------------------------------------------------------------------------------------------

8% of peak computational performance is used (2.63 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.1.1.1  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is highly vectorized.
98% of vector register length is used (average across all VPU instructions).


Details
96% of VPU instructions are used in vector version (process two or more data elements in vector registers):
 - 93% of VPU addition or subtraction instructions are used in vector version.
 - 0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.





      6.1.1.1.2  -  Expensive FP math instructions/calls
  ---------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 56.34 to 15.00 cycles (3.76x speedup).


      6.1.1.1.3  -  FMA
  ---------------------------------------------------------------------------------------------------------

Detected 16 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.1.1.4  -  Slow data structures access
  ---------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 14 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.1.1.5  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 148 FP arithmetical operations:
 - 72: addition or subtraction (16 inside FMA instructions)
 - 60: multiply (16 inside FMA instructions)
 - 16: divide
The binary loop is loading 800 bytes.
The binary loop is storing 64 bytes.


      6.1.1.1.6  -  Arithmetic intensity
  ---------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.







      6.1.2  -  Loop 62 from exec
  =========================================================================================================

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:61-63,69-75.

The related source loop is unrolled by 144 (including vectorization).

      6.1.2.1  -  Path 1
  ---------------------------------------------------------------------------------------------------------

30% of peak computational performance is used (9.87 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.2.1.1  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is highly vectorized.
98% of vector register length is used (average across all VPU instructions).


Details
98% of VPU instructions are used in vector version (process two or more data elements in vector registers):
 - 88% of VPU addition or subtraction instructions are used in vector version.





      6.1.2.1.2  -  FMA
  ---------------------------------------------------------------------------------------------------------

Detected 44 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.2.1.3  -  Slow data structures access
  ---------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 15 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.2.1.4  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 148 FP arithmetical operations:
 - 76: addition or subtraction (44 inside FMA instructions)
 - 68: multiply (44 inside FMA instructions)
 - 4: divide
The binary loop is loading 864 bytes.
The binary loop is storing 96 bytes.


      6.1.2.1.5  -  Arithmetic intensity
  ---------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.







      6.1.3  -  Loop 44 from exec
  =========================================================================================================

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:71-87,93-99.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/PdV_kernel.f90:74,77-87,93-99.

Warnings:
 - Non-innermost loop: analyzing only self part (ignoring child loops).
 - Ignoring paths for analysis
 - Failed to get the number of paths
 - RecMII not computed since number of paths is unknown or > max_paths
 - Streams not analyzed since number of paths is unknown or > max_paths


      6.1.3.1  -  Path 1
  ---------------------------------------------------------------------------------------------------------

9% of peak computational performance is used (2.91 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.3.1.1  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is highly vectorized.
98% of vector register length is used (average across all VPU instructions).


Details
96% of VPU instructions are used in vector version (process two or more data elements in vector registers):
 - 93% of VPU addition or subtraction instructions are used in vector version.
 - 0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.





      6.1.3.1.2  -  Expensive FP math instructions/calls
  ---------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 56.34 to 17.00 cycles (3.31x speedup).


      6.1.3.1.3  -  FMA
  ---------------------------------------------------------------------------------------------------------

Detected 16 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.3.1.4  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 164 FP arithmetical operations:
 - 72: addition or subtraction (16 inside FMA instructions)
 - 76: multiply (16 inside FMA instructions)
 - 16: divide
The binary loop is loading 544 bytes.
The binary loop is storing 64 bytes.


      6.1.3.1.5  -  Arithmetic intensity
  ---------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.27 FP operations per loaded or stored byte.







      6.1.4  -  Loop 152 from exec
  =========================================================================================================

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:246-248.

The related source loop is unrolled by 4 (including vectorization).

      6.1.4.1  -  Path 1
  ---------------------------------------------------------------------------------------------------------

3% of peak computational performance is used (1.14 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.4.1.1  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is highly vectorized.
91% of vector register length is used (average across all VPU instructions).


Details
90% of VPU instructions are used in vector version (process two or more data elements in vector registers):
 - 50% of VPU addition or subtraction instructions are used in vector version.





      6.1.4.1.2  -  Expensive FP math instructions/calls
  ---------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 14.08 to 3.00 cycles (4.69x speedup).


      6.1.4.1.3  -  FMA
  ---------------------------------------------------------------------------------------------------------

Detected 4 FMA (fused multiply-add) operations.




      6.1.4.1.4  -  Slow data structures access
  ---------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 5 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.4.1.5  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 16 FP arithmetical operations:
 - 8: addition or subtraction (4 inside FMA instructions)
 - 4: multiply (all inside FMA instructions)
 - 4: divide
The binary loop is loading 160 bytes.
The binary loop is storing 32 bytes.


      6.1.4.1.6  -  Arithmetic intensity
  ---------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.







      6.1.5  -  Loop 271 from exec
  =========================================================================================================

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/flux_calc_kernel.f90:55-59.

The related source loop is unrolled by 4 (including vectorization).

      6.1.5.1  -  Path 1
  ---------------------------------------------------------------------------------------------------------

20% of peak computational performance is used (6.67 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.5.1.1  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is highly vectorized.
93% of vector register length is used (average across all VPU instructions).


Details
91% of VPU instructions are used in vector version (process two or more data elements in vector registers):
 - 75% of VPU addition or subtraction instructions are used in vector version.





      6.1.5.1.2  -  FMA
  ---------------------------------------------------------------------------------------------------------

Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.5.1.3  -  Slow data structures access
  ---------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Irregular (variable stride) or indirect: 8 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.


      6.1.5.1.4  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 40 FP arithmetical operations:
 - 24: addition or subtraction
 - 16: multiply
The binary loop is loading 320 bytes.
The binary loop is storing 64 bytes.


      6.1.5.1.5  -  Arithmetic intensity
  ---------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.







      6.1.6  -  Loop 145 from exec
  =========================================================================================================

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:182-184.

The related source loop is unrolled by 4 (including vectorization).

      6.1.6.1  -  Path 1
  ---------------------------------------------------------------------------------------------------------

3% of peak computational performance is used (1.14 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.6.1.1  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is highly vectorized.
91% of vector register length is used (average across all VPU instructions).


Details
90% of VPU instructions are used in vector version (process two or more data elements in vector registers):
 - 50% of VPU addition or subtraction instructions are used in vector version.





      6.1.6.1.2  -  Expensive FP math instructions/calls
  ---------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 14.08 to 3.00 cycles (4.69x speedup).


      6.1.6.1.3  -  FMA
  ---------------------------------------------------------------------------------------------------------

Detected 4 FMA (fused multiply-add) operations.




      6.1.6.1.4  -  Slow data structures access
  ---------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 4 occurrence(s)
 - Irregular (variable stride) or indirect: 1 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.



      6.1.6.1.5  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 16 FP arithmetical operations:
 - 8: addition or subtraction (4 inside FMA instructions)
 - 4: multiply (all inside FMA instructions)
 - 4: divide
The binary loop is loading 160 bytes.
The binary loop is storing 32 bytes.


      6.1.6.1.6  -  Arithmetic intensity
  ---------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.







      6.1.7  -  Loop 351 from exec
  =========================================================================================================

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:48-55.

The related source loop is unrolled by 4 (including vectorization).

      6.1.7.1  -  Path 1
  ---------------------------------------------------------------------------------------------------------

3% of peak computational performance is used (1.28 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.7.1.1  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
93% of vector register length is used (average across all VPU instructions).


Details
85% of VPU instructions are used in vector version (process two or more data elements in vector registers):
 - 0% of VPU addition or subtraction instructions are used in vector version.
 - 0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.





      6.1.7.1.2  -  Expensive FP math instructions/calls
  ---------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 28.17 to 3.50 cycles (8.05x speedup).


      6.1.7.1.3  -  FMA
  ---------------------------------------------------------------------------------------------------------

Detected 4 FMA (fused multiply-add) operations.




      6.1.7.1.4  -  Slow data structures access
  ---------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 4 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.7.1.5  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 36 FP arithmetical operations:
 - 4: addition or subtraction (all inside FMA instructions)
 - 24: multiply (4 inside FMA instructions)
 - 4: divide
 - 4: square root
The binary loop is loading 64 bytes.
The binary loop is storing 64 bytes.


      6.1.7.1.6  -  Arithmetic intensity
  ---------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.28 FP operations per loaded or stored byte.







      6.1.8  -  Loop 80 from exec
  =========================================================================================================

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:252-261.

Analyzed code is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:254-261.

Warnings:
 - Non-innermost loop: analyzing only self part (ignoring child loops).
 - Ignoring paths for analysis
 - Failed to get the number of paths
 - RecMII not computed since number of paths is unknown or > max_paths
 - Streams not analyzed since number of paths is unknown or > max_paths


      6.1.8.1  -  Path 1
  ---------------------------------------------------------------------------------------------------------

4% of peak computational performance is used (1.42 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.8.1.1  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is highly vectorized.
95% of vector register length is used (average across all VPU instructions).


Details
95% of VPU instructions are used in vector version (process two or more data elements in vector registers):
 - 83% of VPU addition or subtraction instructions are used in vector version.





      6.1.8.1.2  -  Expensive FP math instructions/calls
  ---------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 28.17 to 5.50 cycles (5.12x speedup).


      6.1.8.1.3  -  FMA
  ---------------------------------------------------------------------------------------------------------

Detected 4 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.8.1.4  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 40 FP arithmetical operations:
 - 24: addition or subtraction (4 inside FMA instructions)
 - 8: multiply (4 inside FMA instructions)
 - 8: divide
The binary loop is loading 288 bytes.
The binary loop is storing 64 bytes.


      6.1.8.1.5  -  Arithmetic intensity
  ---------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.







      6.1.9  -  Loop 156 from exec
  =========================================================================================================

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:214-215,227-240.

The related source loop is not unrolled or unrolled with no peel/tail loop.
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)


      6.1.9.1  -  Path 1
  ---------------------------------------------------------------------------------------------------------

3% of peak computational performance is used (1.22 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.9.1.1  -  Code clean check
  ---------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 13.99 to 2.83 cycles (4.94x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
 - For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop



      6.1.9.1.2  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
Only 24% of vector register length is used (average across all VPU instructions).
By vectorizing your loop, you can lower the cost of an iteration from 13.99 to 6.99 cycles (2.00x speedup).

Details
All VPU instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)<<image_col_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)





      6.1.9.1.3  -  Expensive FP math instructions/calls
  ---------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 13.99 to 7.13 cycles (1.96x speedup).


      6.1.9.1.4  -  FMA
  ---------------------------------------------------------------------------------------------------------

Detected 1 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.9.1.5  -  Slow data structures access
  ---------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 1 occurrence(s)
 - Constant non-unit stride: 6 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.9.1.6  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 17 FP arithmetical operations:
 - 7: addition or subtraction (1 inside FMA instructions)
 - 6: multiply (1 inside FMA instructions)
 - 4: divide
The binary loop does not load or store any data.




      6.1.9.2  -  Path 2
  ---------------------------------------------------------------------------------------------------------

5% of peak computational performance is used (1.83 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.9.2.1  -  Code clean check
  ---------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 4.38 to 2.17 cycles (2.02x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
 - For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop



      6.1.9.2.2  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
Only 26% of vector register length is used (average across all VPU instructions).
By vectorizing your loop, you can lower the cost of an iteration from 4.38 to 4.00 cycles (1.09x speedup).

Details
All VPU instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)<<image_col_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)





      6.1.9.2.3  -  FMA
  ---------------------------------------------------------------------------------------------------------

Detected 1 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.9.2.4  -  Slow data structures access
  ---------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant non-unit stride: 6 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.9.2.5  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 8 FP arithmetical operations:
 - 4: addition or subtraction (1 inside FMA instructions)
 - 3: multiply (1 inside FMA instructions)
 - 1: divide
The binary loop does not load or store any data.







      6.1.10  -  Loop 83 from exec
  =========================================================================================================

The loop is defined in /home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:199-204,210,216-246.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:
 - Ignoring paths for analysis
 - Failed to get the number of paths
 - RecMII not computed since number of paths is unknown or > max_paths
 - Streams not analyzed since number of paths is unknown or > max_paths


      6.1.10.1  -  Path 1
  ---------------------------------------------------------------------------------------------------------

5% of peak computational performance is used (1.74 out of 32.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.10.1.1  -  Code clean check
  ---------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 16.63 to 4.00 cycles (4.16x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
 - For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop



      6.1.10.1.2  -  Vectorization
  ---------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
Only 23% of vector register length is used (average across all VPU instructions).
By vectorizing your loop, you can lower the cost of an iteration from 16.63 to 5.24 cycles (3.17x speedup).

Details
All VPU instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)<<image_col_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)





      6.1.10.1.3  -  FMA
  ---------------------------------------------------------------------------------------------------------

Detected 2 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.10.1.4  -  Matching between your loop (in the source code) and the binary loop
  ---------------------------------------------------------------------------------------------------------

The binary loop is composed of 29 FP arithmetical operations:
 - 12: addition or subtraction (2 inside FMA instructions)
 - 14: multiply (2 inside FMA instructions)
 - 3: divide
The binary loop is loading 9 bytes.


      6.1.10.1.5  -  Arithmetic intensity
  ---------------------------------------------------------------------------------------------------------

Arithmetic intensity is 3.22 FP operations per loaded or stored byte.





[MAQAO] Info: STOP THE REPORT GENERATION
[MAQAO] Info: 
[MAQAO] Info: If your application produces files, they can be found in directory "/home/eoseret/qaas/qaas_runs/178-231-1255/intel/CloverLeaf1.3-FC/run/oneview_runs/defaults/orig/oneview_run_1782312114"
[MAQAO] Info: 
