OV - exec - Loop 455

0x4380a0 CMP	W22, #0

0x4380a4 B.LE	43826c

0x4380a8 CMP	W23, W24

0x4380ac B.CC	438c84

0x4380b0 ADD	X13, X1, #8

0x4380b4 ADD	X16, X1, X3

0x4380b8 MOVZ	X15, #0

0x4380bc HINT	#0

  (457) 0x4380c0 LD1D	{Z6.D}, P6/Z, [X13, X15,LSL #3]

  (457) 0x4380c4 ORR	W28, WZR, W15

  (457) 0x4380c8 ADD	W12, W4, W15

  (457) 0x4380cc FNEG	Z6.D, P6/M, Z6.D

  (457) 0x4380d0 ADD	X15, X15, X6

  (457) 0x4380d4 REV	Z7.D, Z6.D

  (457) 0x4380d8 ST1D	{Z7.D}, P6, [X16, MUL VL]

  (457) 0x4380dc ADD	X16, X16, X3

  (457) 0x4380e0 CMP	W7, W15

  (457) 0x4380e4 B.CS	4380c0

0x4380e8 ADD	W27, W28, W25

0x4380ec CMP	W22, W12

0x4380f0 B.EQ	43826c

0x4380f4 SBFM	X17, X27, #0, #31

0x4380f8 ADD	X2, X18, X1

0x4380fc ADD	X14, X2, #8

0x438100 SUB	W30, W22, W27

0x438104 SUB	X26, X14, W27,SXTW #3

0x438108 LDR	D1, [X1, X17,LSL #3]

0x43810c ADD	X9, X10, X26

0x438110 ADD	X0, X17, #1

0x438114 AND	W27, W30, #128

0x438118 SUB	X28, X9, #8

0x43811c FNEG	D16, D1

0x438120 STR	D16, [X10, X26]

0x438124 CMP	W22, W0

0x438128 B.LT	43826c

0x43812c CBZ	W27, 4381dc

  (456) 0x4381dc LDR	D30, [X1, X0,LSL #3]

  (456) 0x4381e0 ORR	X2, XZR, X28

  (456) 0x4381e4 ADD	X13, X0, #1

  (456) 0x4381e8 ADD	X17, X0, #2

  (456) 0x4381ec ADD	X16, X0, #3

  (456) 0x4381f0 ADD	X15, X0, #4

  (456) 0x4381f4 ADD	X14, X0, #5

  (456) 0x4381f8 ADD	X30, X0, #6

  (456) 0x4381fc ADD	X12, X0, #7

  (456) 0x438200 ADD	X0, X0, #8

  (456) 0x438204 SUB	X28, X28, #64

  (456) 0x438208 FNEG	D31, D30

  (456) 0x43820c STR	D31, [X2], #504

  (456) 0x438210 LDR	D2, [X1, X13,LSL #3]

  (456) 0x438214 FNEG	D3, D2

  (456) 0x438218 STR	D3, [X28, #56]

  (456) 0x43821c LDR	D4, [X1, X17,LSL #3]

  (456) 0x438220 FNEG	D5, D4

  (456) 0x438224 STUR	D5, [X2, #504]

  (456) 0x438228 LDR	D6, [X1, X16,LSL #3]

  (456) 0x43822c FNEG	D7, D6

  (456) 0x438230 STR	D7, [X28, #40]

  (456) 0x438234 LDR	D1, [X1, X15,LSL #3]

  (456) 0x438238 FNEG	D16, D1

  (456) 0x43823c STR	D16, [X28, #32]

  (456) 0x438240 LDR	D17, [X1, X14,LSL #3]

  (456) 0x438244 FNEG	D18, D17

  (456) 0x438248 STR	D18, [X28, #24]

  (456) 0x43824c LDR	D19, [X1, X30,LSL #3]

  (456) 0x438250 FNEG	D20, D19

  (456) 0x438254 STR	D20, [X28, #16]

  (456) 0x438258 LDR	D21, [X1, X12,LSL #3]

  (456) 0x43825c FNEG	D22, D21

  (456) 0x438260 STR	D22, [X28, #8]

  (456) 0x438264 CMP	W22, W0

  (456) 0x438268 B.GE	4381dc

0x43826c ADD	W5, W5, #1

0x438270 ADD	X1, X1, X11

0x438274 CMP	W8, W5

0x438278 B.GT	4380a0

0x438c84 MOVZ	W27, #1

0x438c88 B	4380f4

/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90: 426 - 430

--------------------------------------------------------------------------------

426:         !$OMP DO

427:         DO k=y_min-depth,y_max+1+depth

428:         !$OMP SIMD

429:           DO j=1,depth

430:             xvel0(1-j,k)=-xvel0(1+j,k)

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	update_halo_kernel	update_halo_kernel.f90:754	exec
○	update_halo	update_halo.f90:78	exec
○	timestep	timestep.f90:74	exec
○	hydro	hydro.f90:54	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec

Path /

Metric	Value
CQA speedup if no scalar integer	6.30
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.35
Bottlenecks	P2, P3, P4, P5,
Function	update_halo_kernel._omp_fn.0
Source	update_halo_kernel.f90:426-426,update_halo_kernel.f90:430-430
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.25
CQA cycles if no scalar integer	0.83
CQA cycles if FP arith vectorized	5.25
CQA cycles if fully vectorized	0.88
Front-end cycles	3.88
DIV/SQRT cycles	3.50
P0 cycles	3.50
P1 cycles	5.25
P2 cycles	5.25
P3 cycles	5.25
P4 cycles	5.25
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.83
P10 cycles	0.50
P11 cycles	0.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	32.00
Nb uops	31.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.05
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	19.44
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	22.22
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.29

Metric	Value
CQA speedup if no scalar integer	6.30
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.35
Bottlenecks	P2, P3, P4, P5,
Function	update_halo_kernel._omp_fn.0
Source	update_halo_kernel.f90:426-426,update_halo_kernel.f90:430-430
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.25
CQA cycles if no scalar integer	0.83
CQA cycles if FP arith vectorized	5.25
CQA cycles if fully vectorized	0.88
Front-end cycles	3.88
DIV/SQRT cycles	3.50
P0 cycles	3.50
P1 cycles	5.25
P2 cycles	5.25
P3 cycles	5.25
P4 cycles	5.25
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.83
P10 cycles	0.50
P11 cycles	0.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	32.00
Nb uops	31.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.05
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	19.44
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	22.22
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.29

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	update_halo_kernel._omp_fn.0
Source file and lines	update_halo_kernel.f90:426-430
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90:426-430.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90:426,430.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.25 to 0.83 cycles (6.30x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 19% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.25 to 0.87 cycles (6.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization and with fassociative-math (included in Ofast or ffast-math) to extend vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	5.25	5.25	5.25	5.25	0.50	0.50	0.50	0.50	0.83	0.50	0.67	0.00	0.00
cycles	3.50	3.50	5.25	5.25	5.25	5.25	0.50	0.50	0.50	0.50	0.83	0.50	0.67	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.88
Overall L1	5.25

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.25 cycles. At this rate:

1% of peak load performance is reached (1.52 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.52 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4380a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
CMP W22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 43826c <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x9dcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W23, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 438c84 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0xa7e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X13, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
ADD W27, W28, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W22, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 43826c <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x9dcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X17, X27, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X18, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W30, W22, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X26, X14, W27,SXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
LDR D1, [X1, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X9, X10, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W27, W30, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X28, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FNEG D16, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D16, [X10, X26]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP W22, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 43826c <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x9dcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W27, 4381dc <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x9d3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W5, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W8, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 4380a0 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x9c00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4380f4 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x9c54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	update_halo_kernel._omp_fn.0
Source file and lines	update_halo_kernel.f90:426-430
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90:426-430.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90:426,430.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.25 to 0.83 cycles (6.30x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 19% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.25 to 0.87 cycles (6.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization and with fassociative-math (included in Ofast or ffast-math) to extend vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	5.25	5.25	5.25	5.25	0.50	0.50	0.50	0.50	0.83	0.50	0.67	0.00	0.00
cycles	3.50	3.50	5.25	5.25	5.25	5.25	0.50	0.50	0.50	0.50	0.83	0.50	0.67	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.88
Overall L1	5.25

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.25 cycles. At this rate:

1% of peak load performance is reached (1.52 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.52 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4380a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
CMP W22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 43826c <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x9dcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W23, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 438c84 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0xa7e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X13, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X15, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
ADD W27, W28, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W22, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 43826c <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x9dcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X17, X27, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X18, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W30, W22, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X26, X14, W27,SXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
LDR D1, [X1, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X9, X10, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W27, W30, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X28, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FNEG D16, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D16, [X10, X26]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP W22, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 43826c <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x9dcc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W27, 4381dc <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x9d3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W5, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W8, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 4380a0 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x9c00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4380f4 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x9c54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

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Matching between your loop (in the source code) and the binary loop

General properties

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Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code