OV - exec - Loop 238

	Loop Id: 238	Module: exec	Source: generate_chunk_kernel.f90:129-155 [...]	Coverage: 0.05%

0x426738 LDR	W9, [X14]    [3]

0x42673c CMP	W6, W9

0x426740 B.EQ	42684c

0x426744 LDR	W9, [X21]    [3]

0x426748 CMP	W6, W9

0x42674c B.EQ	4267d8

0x426750 ADD	X0, X0, #8

0x426754 ADD	X8, X8, #8

0x426758 ADD	X7, X7, #8

0x42675c ADD	X5, X5, #8

0x426760 ADD	X4, X4, #8

0x426764 ADD	X2, X2, #8

0x426768 ADD	X1, X1, #8

0x42676c ADD	X3, X3, #8

0x426770 CMP	X0, X12

0x426774 B.EQ	426878

0x426778 CMP	W6, W27

0x42677c B.NE	426738

0x426780 LDUR	D24, [X0, #504]    [15]

0x426784 LDR	D23, [X20, X19,LSL #3]    [6]

0x426788 FCMPE	D24, D23

0x42678c B.GE	426794

0x426790 B	426750

0x426794 LDUR	D26, [X0, #496]    [15]

0x426798 LDR	D25, [X30, X19,LSL #3]    [7]

0x42679c FCMPE	D26, D25

0x4267a0 B.MI	4267a8

0x4267a4 B	426750

0x4267a8 LDR	X9, [SP, #152]    [11]

0x4267ac LDR	D27, [X16, #8]    [17]

0x4267b0 LDR	D28, [X9, X19,LSL #3]    [9]

0x4267b4 FCMPE	D27, D28

0x4267b8 B.GE	4267c0

0x4267bc B	426750

0x4267c0 LDR	X9, [SP, #288]    [11]

0x4267c4 LDR	D29, [X16]    [17]

0x4267c8 LDR	D30, [X9, X19,LSL #3]    [10]

0x4267cc FCMPE	D29, D30

0x4267d0 B.MI	4267f0

0x4267d4 B	426750

0x4267d8 LDUR	D5, [X0, #496]    [15]

0x4267dc FCMP	D2, D5

0x4267e0 B.NE	426750

0x4267e4 LDR	D6, [X16]    [17]

0x4267e8 FCMP	D4, D6

0x4267ec B.NE	426750

0x4267f0 LDR	X9, [SP, #256]    [11]

0x4267f4 LDR	D31, [X9, X19,LSL #3]    [2]

0x4267f8 LDR	X9, [SP, #264]    [11]

0x4267fc STR	D31, [X8]    [8]

0x426800 LDR	D0, [X9, X19,LSL #3]    [4]

0x426804 STR	D0, [X7]    [5]

0x426808 LDR	D1, [X26, X13]    [12]

0x42680c STUR	D1, [X5, #496]    [1]

0x426810 LDR	D3, [X25, X13]    [12]

0x426814 STUR	D3, [X4, #496]    [16]

0x426818 LDR	D5, [X26, X13]    [12]

0x42681c STUR	D5, [X5, #504]    [1]

0x426820 LDR	D6, [X25, X13]    [12]

0x426824 STUR	D6, [X4, #504]    [16]

0x426828 LDR	D7, [X26, X13]    [12]

0x42682c STUR	D7, [X2, #496]    [19]

0x426830 LDR	D16, [X25, X13]    [12]

0x426834 STUR	D16, [X1, #496]    [18]

0x426838 LDR	D17, [X26, X13]    [12]

0x42683c STUR	D17, [X2, #504]    [19]

0x426840 LDR	D18, [X25, X13]    [12]

0x426844 STUR	D18, [X1, #504]    [18]

0x426848 B	426750

0x42684c LDR	D18, [X15]    [14]

0x426850 LDR	D16, [X3]    [20]

0x426854 LDR	D7, [X28, X19,LSL #3]    [13]

0x426858 FSUB	D19, D18, S4

0x42685c FSUB	D17, D16, S2

0x426860 FMUL	D20, D19, D19

0x426864 FMADD	D21, D17, D17, D20

0x426868 FSQRT	D22, D21

0x42686c FCMPE	D22, D7

0x426870 B.LS	4267f0

0x426874 B	426750

/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/generate_chunk_kernel.f90: 129 - 155

--------------------------------------------------------------------------------

129:           IF(state_geometry(state).EQ.g_rect ) THEN

130:             IF(vertexx(j+1).GE.state_xmin(state).AND.vertexx(j).LT.state_xmax(state)) THEN

131:               IF(vertexy(k+1).GE.state_ymin(state).AND.vertexy(k).LT.state_ymax(state)) THEN

132:                 energy0(j,k)=state_energy(state)

133:                 density0(j,k)=state_density(state)

134:                 DO kt=k,k+1

135:                   DO jt=j,j+1

136:                     xvel0(jt,kt)=state_xvel(state)

137:                     yvel0(jt,kt)=state_yvel(state)

138:                   ENDDO

139:                 ENDDO

140:               ENDIF

141:             ENDIF

142:           ELSEIF(state_geometry(state).EQ.g_circ ) THEN

143:             radius=SQRT((cellx(j)-x_cent)*(cellx(j)-x_cent)+(celly(k)-y_cent)*(celly(k)-y_cent))

144:             IF(radius.LE.state_radius(state))THEN

[...]

154:           ELSEIF(state_geometry(state).EQ.g_point) THEN

155:             IF(vertexx(j).EQ.x_cent .AND. vertexy(k).EQ.y_cent) THEN

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk_kernel	generate_chunk_kernel.f90:174	exec
○	generate_chunk	generate_chunk.f90:75	exec
○	start	start.f90:104	exec
○	initialise	initialise.f90:141	exec
○	main	clover_leaf.f90:72	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.18
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.30
Bottlenecks	P10, P11, P12,
Function	generate_chunk_kernel._omp_fn.0
Source	generate_chunk_kernel.f90:129-144,generate_chunk_kernel.f90:154-155
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	13.00
CQA cycles if fully vectorized	3.00
Front-end cycles	10.00
DIV/SQRT cycles	8.50
P0 cycles	8.50
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	8.50
P6 cycles	8.50
P7 cycles	2.50
P8 cycles	2.50
P9 cycles	13.00
P10 cycles	13.00
P11 cycles	13.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	80.00
Nb uops	80.00
Nb loads	NA
Nb stores	10.00
Nb stack references	0.00
FLOP/cycle	0.46
Nb FLOP add-sub	2.00
Nb FLOP mul	1.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.38
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	80.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.99
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.63

Metric	Value
CQA speedup if no scalar integer	1.18
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.30
Bottlenecks	P10, P11, P12,
Function	generate_chunk_kernel._omp_fn.0
Source	generate_chunk_kernel.f90:129-144,generate_chunk_kernel.f90:154-155
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	13.00
CQA cycles if fully vectorized	3.00
Front-end cycles	10.00
DIV/SQRT cycles	8.50
P0 cycles	8.50
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	8.50
P6 cycles	8.50
P7 cycles	2.50
P8 cycles	2.50
P9 cycles	13.00
P10 cycles	13.00
P11 cycles	13.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	80.00
Nb uops	80.00
Nb loads	NA
Nb stores	10.00
Nb stack references	0.00
FLOP/cycle	0.46
Nb FLOP add-sub	2.00
Nb FLOP mul	1.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.38
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	80.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.99
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.63

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	generate_chunk_kernel._omp_fn.0
Source file and lines	generate_chunk_kernel.f90:129-155
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:129-144,154-155.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=11
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 11 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.00 to 11.00 cycles (1.18x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 13.00 to 3.00 cycles (4.33x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization and with fassociative-math (included in Ofast or ffast-math) to extend vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

3: addition or subtraction (1 inside FMA instructions)
2: multiply (1 inside FMA instructions)
1: square root

The binary loop is loading 224 bytes. The binary loop is storing 80 bytes.

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	80
loop length	320
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.50	8.50	3.00	3.00	3.00	3.00	8.50	8.50	2.50	2.50	13.00	13.00	13.00	0.00	0.00
cycles	8.50	8.50	3.00	3.00	3.00	3.00	8.50	8.50	2.50	2.50	13.00	13.00	13.00	0.00	0.00

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	10.00
Overall L1	13.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.00 cycles. At this rate:

17% of peak load performance is reached (17.23 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.15 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 426778

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR W9, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP W6, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 42684c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x80c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP W6, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4267d8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x798>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X7, X7, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X3, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X0, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 426878 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x838>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W6, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 426738 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x6f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR D24, [X0, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D23, [X20, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D24, D23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GE 426794 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x754>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 426750 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x710>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR D26, [X0, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D25, [X30, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D26, D25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 4267a8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x768>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 426750 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x710>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D27, [X16, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D28, [X9, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D27, D28	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GE 4267c0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x780>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 426750 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x710>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D29, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D30, [X9, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D29, D30	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 4267f0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x7b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 426750 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x710>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR D5, [X0, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMP D2, D5	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.NE 426750 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x710>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D6, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMP D4, D6	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.NE 426750 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x710>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D31, [X9, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X9, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
STR D31, [X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D0, [X9, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D0, [X7]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D1, [X26, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STUR D1, [X5, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D3, [X25, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STUR D3, [X4, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D5, [X26, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STUR D5, [X5, #504]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D6, [X25, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STUR D6, [X4, #504]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D7, [X26, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STUR D7, [X2, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D16, [X25, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STUR D16, [X1, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D17, [X26, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STUR D17, [X2, #504]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D18, [X25, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STUR D18, [X1, #504]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 426750 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x710>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D18, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D16, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D7, [X28, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSUB D19, D18, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D17, D16, S2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D20, D19, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D21, D17, D17, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FSQRT D22, D21	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	1-0.50
FCMPE D22, D7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LS 4267f0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x7b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 426750 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x710>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	generate_chunk_kernel._omp_fn.0
Source file and lines	generate_chunk_kernel.f90:129-155
Module	exec

Ignoring paths for analysis
Too many paths. Rerun with max-paths=11
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization and with fassociative-math (included in Ofast or ffast-math) to extend vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

3: addition or subtraction (1 inside FMA instructions)
2: multiply (1 inside FMA instructions)
1: square root

The binary loop is loading 224 bytes. The binary loop is storing 80 bytes.

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	80
loop length	320
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.50	8.50	3.00	3.00	3.00	3.00	8.50	8.50	2.50	2.50	13.00	13.00	13.00	0.00	0.00
cycles	8.50	8.50	3.00	3.00	3.00	3.00	8.50	8.50	2.50	2.50	13.00	13.00	13.00	0.00	0.00

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	10.00
Overall L1	13.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.00 cycles. At this rate:

17% of peak load performance is reached (17.23 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.15 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 426778

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR W9, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP W6, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 42684c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x80c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP W6, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4267d8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x798>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X7, X7, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X3, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X0, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 426878 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x838>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W6, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 426738 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x6f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR D24, [X0, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D23, [X20, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D24, D23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GE 426794 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x754>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 426750 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x710>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR D26, [X0, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D25, [X30, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D26, D25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 4267a8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x768>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 426750 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x710>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D27, [X16, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D28, [X9, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D27, D28	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GE 4267c0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x780>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 426750 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x710>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D29, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D30, [X9, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D29, D30	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 4267f0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x7b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 426750 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x710>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR D5, [X0, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMP D2, D5	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.NE 426750 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x710>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D6, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMP D4, D6	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.NE 426750 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x710>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D31, [X9, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X9, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
STR D31, [X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D0, [X9, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D0, [X7]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D1, [X26, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STUR D1, [X5, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D3, [X25, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STUR D3, [X4, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D5, [X26, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STUR D5, [X5, #504]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D6, [X25, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STUR D6, [X4, #504]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D7, [X26, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STUR D7, [X2, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D16, [X25, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STUR D16, [X1, #496]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D17, [X26, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STUR D17, [X2, #504]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D18, [X25, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STUR D18, [X1, #504]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 426750 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x710>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D18, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D16, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D7, [X28, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSUB D19, D18, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D17, D16, S2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D20, D19, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D21, D17, D17, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FSQRT D22, D21	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	1-0.50
FCMPE D22, D7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LS 4267f0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x7b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 426750 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x710>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code