OV - exec - Loop 223

	Loop Id: 223	Module: exec	Source: field_summary_kernel.f90:62-71	Coverage: 0.47%

0x4251e8 LDR	D7, [X5, X1,LSL #3]    [11]

0x4251ec ADD	X26, X1, #1

0x4251f0 ADD	X2, X3, #1

0x4251f4 LDR	D23, [X6, X1,LSL #3]    [7]

0x4251f8 LDR	D24, [X5, X3,LSL #3]    [16]

0x4251fc FMUL	D26, D7, D7

0x425200 LDR	D25, [X5, X26,LSL #3]    [14]

0x425204 LDR	D27, [X6, X3,LSL #3]    [9]

0x425208 LDR	D16, [X7, X1,LSL #3]    [12]

0x42520c FMUL	D28, D24, D24

0x425210 FMADD	D29, D23, D23, D26

0x425214 LDR	D30, [X6, X26,LSL #3]    [6]

0x425218 FMUL	D31, D25, D25

0x42521c LDR	D20, [X5, X2,LSL #3]    [15]

0x425220 FMADD	D19, D27, D27, D28

0x425224 LDR	D4, [X8, X1,LSL #3]    [18]

0x425228 FMADD	D0, D29, D2, D17

0x42522c FMUL	D21, D16, D16

0x425230 LDR	D3, [X7, X3,LSL #3]    [17]

0x425234 FMADD	D1, D30, D30, D31

0x425238 LDR	D5, [X6, X2,LSL #3]    [24]

0x42523c FMUL	D22, D20, D20

0x425240 FMADD	D23, D19, D2, D0

0x425244 LDR	D6, [X7, X26,LSL #3]    [22]

0x425248 FMADD	D24, D4, D4, D21

0x42524c FMADD	D25, D1, D2, D17

0x425250 LDR	D26, [X12, X1,LSL #3]    [8]

0x425254 FMUL	D27, D3, D3

0x425258 LDR	D28, [X11, X1,LSL #3]    [4]

0x42525c FMADD	D7, D5, D5, D22

0x425260 FMADD	D29, D24, D2, D23

0x425264 LDR	D30, [X8, X3,LSL #3]    [19]

0x425268 FMUL	D16, D6, D6

0x42526c ADD	X3, X3, #2

0x425270 LDR	D31, [X8, X26,LSL #3]    [13]

0x425274 FADD	D10, D10, D26

0x425278 FMADD	D4, D7, D2, D25

0x42527c LDR	D0, [X7, X2,LSL #3]    [1]

0x425280 FMUL	D3, D26, D28

0x425284 LDR	D20, [X12, X26,LSL #3]    [3]

0x425288 FMADD	D19, D30, D30, D27

0x42528c LDR	D5, [X11, X26,LSL #3]    [10]

0x425290 FMADD	D1, D31, D31, D16

0x425294 LDR	D23, [X8, X2,LSL #3]    [2]

0x425298 FMUL	D6, D0, D0

0x42529c FMUL	D22, D3, D18

0x4252a0 FMADD	D24, D19, D2, D29

0x4252a4 LDR	D21, [X10, X1,LSL #3]    [23]

0x4252a8 FADD	D9, D9, D3

0x4252ac FADD	D10, D10, D20

0x4252b0 FMADD	D25, D1, D2, D4

0x4252b4 FMUL	D27, D20, D5

0x4252b8 LDR	D28, [X9, X1,LSL #3]    [21]

0x4252bc ADD	X1, X1, #2

0x4252c0 FMADD	D29, D23, D23, D6

0x4252c4 LDR	D30, [X10, X26,LSL #3]    [20]

0x4252c8 FMADD	D16, D24, D22, D8

0x4252cc LDR	D7, [X9, X26,LSL #3]    [5]

0x4252d0 FMADD	D11, D3, D21, D11

0x4252d4 FMADD	D12, D26, D28, D12

0x4252d8 FMADD	D31, D29, D2, D25

0x4252dc FMUL	D8, D27, D18

0x4252e0 FADD	D9, D9, D27

0x4252e4 FMADD	D11, D27, D30, D11

0x4252e8 FMADD	D12, D20, D7, D12

0x4252ec FMADD	D8, D31, D8, D16

0x4252f0 CMP	W13, W1

0x4252f4 B.GE	4251e8

/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/field_summary_kernel.f90: 62 - 71

--------------------------------------------------------------------------------

62:             vsqrd=vsqrd+0.25*(xvel0(jv,kv)**2+yvel0(jv,kv)**2)

63:           ENDDO

64:         ENDDO

65:         cell_vol=volume(j,k)

66:         cell_mass=cell_vol*density0(j,k)

67:         vol=vol+cell_vol

68:         mass=mass+cell_mass

69:         ie=ie+cell_mass*energy0(j,k)

70:         ke=ke+cell_mass*0.5*vsqrd

71:         press=press+cell_vol*pressure(j,k)

Coverage (%)	Name	Source Location	Module
►80.00+	GOMP_parallel		libgomp.so.1.0.0
○	field_summary_kernel	field_summary_kernel.f90:54	exec
○	field_summary	field_summary.f90:84	exec
○	hydro	hydro.f90:74	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec
►10.00+	GOMP_parallel		libgomp.so.1.0.0
○	field_summary_kernel	field_summary_kernel.f90:54	exec
○	field_summary	field_summary.f90:84	exec
○	hydro	hydro.f90:88	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec
►10.00+	GOMP_parallel		libgomp.so.1.0.0
○	field_summary_kernel	field_summary_kernel.f90:54	exec
○	field_summary	field_summary.f90:84	exec
○	start	start.f90:145	exec
○	initialise	initialise.f90:141	exec
○	main	clover_leaf.f90:72	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.19
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.12
Bottlenecks	P6, P7, P8, P9,
Function	field_summary_kernel._omp_fn.0
Source	field_summary_kernel.f90:62-71
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.50
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	9.50
CQA cycles if fully vectorized	2.38
Front-end cycles	8.50
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.25
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	9.50
P6 cycles	9.50
P7 cycles	9.50
P8 cycles	9.50
P9 cycles	8.00
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	68.00
Nb uops	68.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	6.32
Nb FLOP add-sub	4.00
Nb FLOP mul	12.00
Nb FLOP fma	22.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.21
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.19
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.12
Bottlenecks	P6, P7, P8, P9,
Function	field_summary_kernel._omp_fn.0
Source	field_summary_kernel.f90:62-71
Source loop unroll info	multi-versionned
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.50
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	9.50
CQA cycles if fully vectorized	2.38
Front-end cycles	8.50
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.25
P2 cycles	1.25
P3 cycles	1.25
P4 cycles	1.25
P5 cycles	9.50
P6 cycles	9.50
P7 cycles	9.50
P8 cycles	9.50
P9 cycles	8.00
P10 cycles	8.00
P11 cycles	8.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	68.00
Nb uops	68.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	6.32
Nb FLOP add-sub	4.00
Nb FLOP mul	12.00
Nb FLOP fma	22.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.21
Bytes prefetched	0.00
Bytes loaded	192.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	25.00
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	field_summary_kernel._omp_fn.0
Source file and lines	field_summary_kernel.f90:62-71
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/field_summary_kernel.f90:62-71.

The related source loop is multi-versionned.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.50 to 8.00 cycles (1.19x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 9.50 to 2.37 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization and with fassociative-math (included in Ofast or ffast-math) to extend vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 22 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 60 FP arithmetical operations:

26: addition or subtraction (22 inside FMA instructions)
34: multiply (22 inside FMA instructions)

The binary loop is loading 192 bytes.

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

General properties

nb instructions	68
loop length	272
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.25	1.25	1.25	1.25	9.50	9.50	9.50	9.50	8.00	8.00	8.00	0.00	0.00
cycles	0.50	0.50	1.25	1.25	1.25	1.25	9.50	9.50	9.50	9.50	8.00	8.00	8.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	8.50
Data deps.	4.00
Overall L1	9.50

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.50 cycles. At this rate:

21% of peak load performance is reached (20.21 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4251e8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR D7, [X5, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X26, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X2, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D23, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D24, [X5, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D26, D7, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D25, [X5, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D27, [X6, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D16, [X7, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D28, D24, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D29, D23, D23, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D30, [X6, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D31, D25, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D20, [X5, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D19, D27, D27, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D4, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D29, D2, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D21, D16, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D3, [X7, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D1, D30, D30, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D5, [X6, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D22, D20, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D23, D19, D2, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D6, [X7, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D24, D4, D4, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D25, D1, D2, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D26, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D27, D3, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D28, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D7, D5, D5, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D29, D24, D2, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D30, [X8, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D16, D6, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
ADD X3, X3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D31, [X8, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D10, D10, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMADD D4, D7, D2, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D0, [X7, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D3, D26, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D20, [X12, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D19, D30, D30, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D5, [X11, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D1, D31, D31, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D23, [X8, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D6, D0, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL D22, D3, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D24, D19, D2, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D21, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D9, D9, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D10, D10, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMADD D25, D1, D2, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D27, D20, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D28, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMADD D29, D23, D23, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D30, [X10, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D16, D24, D22, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D7, [X9, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D11, D3, D21, D11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D12, D26, D28, D12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D31, D29, D2, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D8, D27, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FADD D9, D9, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMADD D11, D27, D30, D11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D12, D20, D7, D12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D8, D31, D8, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
CMP W13, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 4251e8 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	field_summary_kernel._omp_fn.0
Source file and lines	field_summary_kernel.f90:62-71
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.50 to 8.00 cycles (1.19x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. 4 data elements could be processed at once in vector registers. By vectorizing your loop, you can lower the cost of an iteration from 9.50 to 2.37 cycles (4.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization and with fassociative-math (included in Ofast or ffast-math) to extend vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 22 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 60 FP arithmetical operations:

26: addition or subtraction (22 inside FMA instructions)
34: multiply (22 inside FMA instructions)

The binary loop is loading 192 bytes.

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

General properties

nb instructions	68
loop length	272
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.25	1.25	1.25	1.25	9.50	9.50	9.50	9.50	8.00	8.00	8.00	0.00	0.00
cycles	0.50	0.50	1.25	1.25	1.25	1.25	9.50	9.50	9.50	9.50	8.00	8.00	8.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	8.50
Data deps.	4.00
Overall L1	9.50

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.50 cycles. At this rate:

21% of peak load performance is reached (20.21 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4251e8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR D7, [X5, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X26, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X2, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D23, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D24, [X5, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D26, D7, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D25, [X5, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D27, [X6, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D16, [X7, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D28, D24, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D29, D23, D23, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D30, [X6, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D31, D25, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D20, [X5, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D19, D27, D27, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D4, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D0, D29, D2, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D21, D16, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D3, [X7, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D1, D30, D30, D31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D5, [X6, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D22, D20, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D23, D19, D2, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D6, [X7, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D24, D4, D4, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D25, D1, D2, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D26, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D27, D3, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D28, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D7, D5, D5, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D29, D24, D2, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D30, [X8, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D16, D6, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
ADD X3, X3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D31, [X8, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D10, D10, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMADD D4, D7, D2, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D0, [X7, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D3, D26, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D20, [X12, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D19, D30, D30, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D5, [X11, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D1, D31, D31, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D23, [X8, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D6, D0, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL D22, D3, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D24, D19, D2, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D21, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADD D9, D9, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D10, D10, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMADD D25, D1, D2, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D27, D20, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D28, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMADD D29, D23, D23, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D30, [X10, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D16, D24, D22, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D7, [X9, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D11, D3, D21, D11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D12, D26, D28, D12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D31, D29, D2, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D8, D27, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FADD D9, D9, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMADD D11, D27, D30, D11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D12, D20, D7, D12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D8, D31, D8, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
CMP W13, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 4251e8 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code