| Loop Id: 212 | Module: exec | Source: calc_dt_kernel.f90:96-129 | Coverage: 0.02% |
|---|
| Loop Id: 212 | Module: exec | Source: calc_dt_kernel.f90:96-129 | Coverage: 0.02% |
|---|
0x423c84 LDR W1, [SP, #128] |
0x423c88 CMP W1, W13 |
0x423c8c B.GT 423dd8 |
0x423c90 LDR X1, [SP, #192] |
0x423c94 LDR D6, [X19, X16] |
0x423c98 LDR D0, [X27, X16] |
0x423c9c LDR D21, [X1] |
0x423ca0 LDR X1, [SP, #168] |
0x423ca4 FADD D6, D6, D0 |
0x423ca8 LDR D17, [X21] |
0x423cac FADD D21, D21, D21 |
0x423cb0 STR X1, [SP, #112] |
0x423cb4 LDR X1, [SP, #200] |
0x423cb8 LDR D20, [X1] |
0x423cbc LDR X1, [SP, #176] |
0x423cc0 FADD D20, D20, D20 |
0x423cc4 LDR D18, [X1] |
0x423cc8 LDR X1, [SP, #208] |
0x423ccc FNEG D22, D18 |
0x423cd0 LDR D24, [X1, X15,LSL #3] |
0x423cd4 LDR X15, [SP, #184] |
0x423cd8 LDR X1, [SP, #216] |
0x423cdc LDR D23, [X15] |
0x423ce0 LDR X15, [SP, #224] |
0x423ce4 LDR D16, [X1, X17] |
0x423ce8 LDR X1, [SP, #112] |
0x423cec LDR D7, [X15, X17] |
(213) 0x423cf0 FMUL D8, D6, D17 |
(213) 0x423cf4 FMOV D4, D7 |
(213) 0x423cf8 LDR D1, [X6, X1,LSL #3] |
(213) 0x423cfc FMOV D31, D16 |
(213) 0x423d00 LDR D2, [X2, X1,LSL #3] |
(213) 0x423d04 LDR D17, [X3, X1,LSL #3] |
(213) 0x423d08 FABS D28, D8 |
(213) 0x423d0c LDR D7, [X4, X1,LSL #3] |
(213) 0x423d10 FADD D6, D1, D2 |
(213) 0x423d14 LDR D27, [X10, X1,LSL #3] |
(213) 0x423d18 LDR D30, [X7, X1,LSL #3] |
(213) 0x423d1c FADD D29, D7, D4 |
(213) 0x423d20 LDR D16, [X5, X1,LSL #3] |
(213) 0x423d24 FMUL D3, D6, D17 |
(213) 0x423d28 LDR D5, [X9, X1,LSL #3] |
(213) 0x423d2c LDR D9, [X11, X1,LSL #3] |
(213) 0x423d30 FMUL D4, D29, D27 |
(213) 0x423d34 FADD D29, D30, D30 |
(213) 0x423d38 LDR D2, [X12, X1,LSL #3] |
(213) 0x423d3c FADD D31, D16, D31 |
(213) 0x423d40 FADD D0, D3, D25 |
(213) 0x423d44 FABS D27, D3 |
(213) 0x423d48 LDR D30, [X14, X1,LSL #3] |
(213) 0x423d4c FMINNM D3, D30, D24 |
(213) 0x423d50 FMUL D3, D3, D23 |
(213) 0x423d54 LDR D1, [X8, X1,LSL #3] |
(213) 0x423d58 FDIV D29, D29, D5 |
(213) 0x423d5c FADD D30, D2, D2 |
(213) 0x423d60 FMUL D31, D31, D9 |
(213) 0x423d64 FSUB D0, D0, S8 |
(213) 0x423d68 FMUL D5, D2, D21 |
(213) 0x423d6c FMUL D8, D2, D20 |
(213) 0x423d70 FMUL D2, D18, D2 |
(213) 0x423d74 FMAXNM D28, D28, D2 |
(213) 0x423d78 FMAXNM D28, D28, D27 |
(213) 0x423d7c FABS D9, D4 |
(213) 0x423d80 FABS D27, D31 |
(213) 0x423d84 FMAXNM D9, D27, D9 |
(213) 0x423d88 FADD D0, D0, D4 |
(213) 0x423d8c FDIV D5, D5, D28 |
(213) 0x423d90 FMAXNM D27, D9, D2 |
(213) 0x423d94 FSUB D31, D0, S31 |
(213) 0x423d98 FDIV D4, D8, D27 |
(213) 0x423d9c FMADD D1, D1, D1, D29 |
(213) 0x423da0 FDIV D29, D31, D30 |
(213) 0x423da4 FSQRT D30, D1 |
(213) 0x423da8 FMAXNM D8, D30, D18 |
(213) 0x423dac FDIV D3, D3, D8 |
(213) 0x423db0 FMINNM D2, D5, D3 |
(213) 0x423db4 FCMPE D29, D22 |
(213) 0x423db8 B.MI 423e48 |
(213) 0x423dbc LDR D27, [X20] |
(213) 0x423dc0 ADD X1, X1, #1 |
(213) 0x423dc4 FMINNM D5, D27, D4 |
(213) 0x423dc8 FMINNM D0, D5, D2 |
(213) 0x423dcc FMINNM D19, D19, D0 |
(213) 0x423dd0 CMP W13, W1 |
(213) 0x423dd4 B.GE 423cf0 |
0x423dd8 LDR W1, [SP, #132] |
0x423ddc ADD X6, X6, X22 |
0x423de0 ADD X2, X2, X22 |
0x423de4 ADD X3, X3, X24 |
0x423de8 ADD X5, X5, X18 |
0x423dec ADD X11, X11, X23 |
0x423df0 ADD X4, X4, X18 |
0x423df4 ADD X10, X10, X23 |
0x423df8 ADD X21, X21, X24 |
0x423dfc ADD X16, X16, X22 |
0x423e00 ADD X17, X17, X18 |
0x423e04 CMP W26, W1 |
0x423e08 LDR X1, [SP, #152] |
0x423e0c ORR X15, XZR, X0 |
0x423e10 CSEL W28, W28, W26, #1 |
0x423e14 CSINC W25, W25, WZR, #1 |
0x423e18 ADD X8, X8, X1 |
0x423e1c LDR X1, [SP, #144] |
0x423e20 ADD X7, X7, X1 |
0x423e24 LDR X1, [SP, #136] |
0x423e28 ADD X9, X9, X1 |
0x423e2c LDR X1, [SP, #160] |
0x423e30 ADD X12, X12, X1 |
0x423e34 LDR W1, [SP, #124] |
0x423e38 CMP W1, W0 |
0x423e3c B.LE 423e94 |
0x423e40 ADD X0, X0, #1 |
0x423e44 B 423c84 |
(213) 0x423e48 FDIV D28, D26, D29 |
(213) 0x423e4c LDR D9, [X30] |
(213) 0x423e50 FNMUL D27, D28, D9 |
(213) 0x423e54 B 423dc0 |
/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/calc_dt_kernel.f90: 96 - 129 |
-------------------------------------------------------------------------------- |
96: dsx=celldx(j) |
97: dsy=celldy(k) |
98: |
99: cc=soundspeed(j,k)*soundspeed(j,k) |
100: cc=cc+2.0_8*viscosity_a(j,k)/density0(j,k) |
101: cc=MAX(SQRT(cc),g_small) |
102: |
103: dtct=dtc_safe*MIN(dsx,dsy)/cc |
104: |
105: div=0.0 |
106: |
107: dv1=(xvel0(j ,k)+xvel0(j ,k+1))*xarea(j ,k) |
108: dv2=(xvel0(j+1,k)+xvel0(j+1,k+1))*xarea(j+1,k) |
109: |
110: div=div+dv2-dv1 |
111: |
112: dtut=dtu_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k)) |
113: |
114: dv1=(yvel0(j,k )+yvel0(j+1,k ))*yarea(j,k ) |
115: dv2=(yvel0(j,k+1)+yvel0(j+1,k+1))*yarea(j,k+1) |
116: |
117: div=div+dv2-dv1 |
118: |
119: dtvt=dtv_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k)) |
120: |
121: div=div/(2.0_8*volume(j,k)) |
122: |
123: IF(div.LT.-g_small)THEN |
124: dtdivt=dtdiv_safe*(-1.0_8/div) |
125: ELSE |
126: dtdivt=g_big |
127: ENDIF |
128: |
129: dt_min_val=MIN(dt_min_val,dtct,dtut,dtvt,dtdivt) |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►100.00+ | GOMP_parallel | libgomp.so.1.0.0 | |
| ○ | calc_dt_kernel | calc_dt_kernel.f90:140 | exec |
| ○ | calc_dt | calc_dt.f90:81 | exec |
| ○ | timestep | timestep.f90:87 | exec |
| ○ | hydro | hydro.f90:54 | exec |
| ○ | main | clover_leaf.f90:41 | exec |
| ○ | __libc_start_main | libc-2.31.so | |
| ○ | _start | clover_leaf.f90:41 | exec |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.98 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 5.55 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.08 |
| Bottlenecks | |
| Function | calc_dt_kernel._omp_fn.0 |
| Source | calc_dt_kernel.f90:97-97,calc_dt_kernel.f90:101-103,calc_dt_kernel.f90:107-107,calc_dt_kernel.f90:112-115,calc_dt_kernel.f90:119-119,calc_dt_kernel.f90:123-123,calc_dt_kernel.f90:129-129 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 7.86 |
| CQA cycles if no scalar integer | 3.97 |
| CQA cycles if FP arith vectorized | 7.86 |
| CQA cycles if fully vectorized | 1.42 |
| Front-end cycles | 5.88 |
| DIV/SQRT cycles | 1.50 |
| P0 cycles | 1.50 |
| P1 cycles | 5.25 |
| P2 cycles | 5.25 |
| P3 cycles | 5.25 |
| P4 cycles | 5.25 |
| P5 cycles | 0.67 |
| P6 cycles | 0.67 |
| P7 cycles | 0.67 |
| P8 cycles | 0.67 |
| P9 cycles | 6.89 |
| P10 cycles | 6.67 |
| P11 cycles | 6.78 |
| P12 cycles | 0.33 |
| P13 cycles | 0.33 |
| P14 cycles | 0.00 |
| Inter-iter dependencies cycles | 2 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 47.00 |
| Nb uops | 47.00 |
| Nb loads | NA |
| Nb stores | 0.67 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.25 |
| Nb FLOP add-sub | 2.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 17.63 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 145.33 |
| Bytes stored | 5.33 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 23.26 |
| Vector-efficiency ratio load | 25.00 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 25.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 13.54 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 4.67 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.35 |
| Bottlenecks | P2, P3, P4, P5, |
| Function | calc_dt_kernel._omp_fn.0 |
| Source | calc_dt_kernel.f90:97-97,calc_dt_kernel.f90:101-103,calc_dt_kernel.f90:107-107,calc_dt_kernel.f90:112-115,calc_dt_kernel.f90:119-119,calc_dt_kernel.f90:123-123,calc_dt_kernel.f90:129-129 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 5.25 |
| CQA cycles if no scalar integer | 5.25 |
| CQA cycles if FP arith vectorized | 5.25 |
| CQA cycles if fully vectorized | 1.13 |
| Front-end cycles | 3.88 |
| DIV/SQRT cycles | 1.50 |
| P0 cycles | 1.50 |
| P1 cycles | 5.25 |
| P2 cycles | 5.25 |
| P3 cycles | 5.25 |
| P4 cycles | 5.25 |
| P5 cycles | 0.00 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| P8 cycles | 0.00 |
| P9 cycles | 2.33 |
| P10 cycles | 2.33 |
| P11 cycles | 2.33 |
| P12 cycles | 0.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| Inter-iter dependencies cycles | 2 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 31.00 |
| Nb uops | 31.00 |
| Nb loads | NA |
| Nb stores | 0.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 8.38 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 44.00 |
| Bytes stored | 0.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | NA |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 22.92 |
| Vector-efficiency ratio load | NA |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 25.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 15.63 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 2.75 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 5.87 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.02 |
| Bottlenecks | P10, |
| Function | calc_dt_kernel._omp_fn.0 |
| Source | calc_dt_kernel.f90:97-97,calc_dt_kernel.f90:101-103,calc_dt_kernel.f90:107-107,calc_dt_kernel.f90:112-115,calc_dt_kernel.f90:119-119,calc_dt_kernel.f90:123-123,calc_dt_kernel.f90:129-129 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 9.17 |
| CQA cycles if no scalar integer | 3.33 |
| CQA cycles if FP arith vectorized | 9.17 |
| CQA cycles if fully vectorized | 1.56 |
| Front-end cycles | 6.88 |
| DIV/SQRT cycles | 1.50 |
| P0 cycles | 1.50 |
| P1 cycles | 5.25 |
| P2 cycles | 5.25 |
| P3 cycles | 5.25 |
| P4 cycles | 5.25 |
| P5 cycles | 1.00 |
| P6 cycles | 1.00 |
| P7 cycles | 1.00 |
| P8 cycles | 1.00 |
| P9 cycles | 9.17 |
| P10 cycles | 8.83 |
| P11 cycles | 9.00 |
| P12 cycles | 0.50 |
| P13 cycles | 0.50 |
| P14 cycles | 0.00 |
| Inter-iter dependencies cycles | 2 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 55.00 |
| Nb uops | 55.00 |
| Nb loads | NA |
| Nb stores | 1.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.33 |
| Nb FLOP add-sub | 3.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 22.25 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 196.00 |
| Bytes stored | 8.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | 0.00 |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 23.44 |
| Vector-efficiency ratio load | 25.00 |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 25.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 12.50 |
| Path / |
| Function | calc_dt_kernel._omp_fn.0 |
| Source file and lines | calc_dt_kernel.f90:96-129 |
| Module | exec |
| nb instructions | 47 |
| loop length | 188 |
| nb stack references | 0 |
| front end | 5.88 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.50 | 1.50 | 5.25 | 5.25 | 5.25 | 5.25 | 0.67 | 0.67 | 0.67 | 0.67 | 6.89 | 6.67 | 6.78 | 0.33 | 0.33 |
| cycles | 1.50 | 1.50 | 5.25 | 5.25 | 5.25 | 5.25 | 0.67 | 0.67 | 0.67 | 0.67 | 6.89 | 6.67 | 6.78 | 0.33 | 0.33 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 2.00 |
| Front-end | 5.88 |
| Data deps. | 2.00 |
| Overall L1 | 7.86 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| Function | calc_dt_kernel._omp_fn.0 |
| Source file and lines | calc_dt_kernel.f90:96-129 |
| Module | exec |
| nb instructions | 31 |
| loop length | 124 |
| nb stack references | 0 |
| front end | 3.88 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.50 | 1.50 | 5.25 | 5.25 | 5.25 | 5.25 | 0.00 | 0.00 | 0.00 | 0.00 | 2.33 | 2.33 | 2.33 | 0.00 | 0.00 |
| cycles | 1.50 | 1.50 | 5.25 | 5.25 | 5.25 | 5.25 | 0.00 | 0.00 | 0.00 | 0.00 | 2.33 | 2.33 | 2.33 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 2.00 |
| Front-end | 3.88 |
| Data deps. | 2.00 |
| Overall L1 | 5.25 |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LDR W1, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W1, W13 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 423dd8 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x398> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR W1, [SP, #132] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X6, X6, X22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X2, X2, X22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X3, X3, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, X5, X18 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X11, X11, X23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X4, X4, X18 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X10, X10, X23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X21, X21, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X16, X16, X22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X17, X17, X18 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CMP W26, W1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| LDR X1, [SP, #152] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X15, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CSEL W28, W28, W26, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CSINC W25, W25, WZR, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X8, X8, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X1, [SP, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X7, X7, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X1, [SP, #136] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X9, X9, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X1, [SP, #160] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X12, X12, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W1, [SP, #124] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W1, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LE 423e94 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x454> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ADD X0, X0, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 423c84 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x244> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| Function | calc_dt_kernel._omp_fn.0 |
| Source file and lines | calc_dt_kernel.f90:96-129 |
| Module | exec |
| nb instructions | 55 |
| loop length | 220 |
| nb stack references | 0 |
| front end | 6.88 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.50 | 1.50 | 5.25 | 5.25 | 5.25 | 5.25 | 1.00 | 1.00 | 1.00 | 1.00 | 9.17 | 8.83 | 9.00 | 0.50 | 0.50 |
| cycles | 1.50 | 1.50 | 5.25 | 5.25 | 5.25 | 5.25 | 1.00 | 1.00 | 1.00 | 1.00 | 9.17 | 8.83 | 9.00 | 0.50 | 0.50 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 2.00 |
| Front-end | 6.88 |
| Data deps. | 2.00 |
| Overall L1 | 9.17 |
| all | 0% |
| load | 0% |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LDR W1, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W1, W13 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 423dd8 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x398> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X1, [SP, #192] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR D6, [X19, X16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| LDR D0, [X27, X16] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| LDR D21, [X1] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| LDR X1, [SP, #168] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| FADD D6, D6, D0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| LDR D17, [X21] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| FADD D21, D21, D21 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| STR X1, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0.50 | 0 | 0.50 | 0.50 | 1 | 0.50 |
| LDR X1, [SP, #200] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR D20, [X1] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| LDR X1, [SP, #176] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| FADD D20, D20, D20 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| LDR D18, [X1] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| LDR X1, [SP, #208] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| FNEG D22, D18 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 2 | 0.25 |
| LDR D24, [X1, X15,LSL #3] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| LDR X15, [SP, #184] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X1, [SP, #216] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR D23, [X15] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| LDR X15, [SP, #224] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR D16, [X1, X17] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| LDR X1, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR D7, [X15, X17] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 6 | 0.33 |
| LDR W1, [SP, #132] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X6, X6, X22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X2, X2, X22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X3, X3, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, X5, X18 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X11, X11, X23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X4, X4, X18 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X10, X10, X23 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X21, X21, X24 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X16, X16, X22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X17, X17, X18 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CMP W26, W1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| LDR X1, [SP, #152] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ORR X15, XZR, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CSEL W28, W28, W26, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CSINC W25, W25, WZR, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X8, X8, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X1, [SP, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X7, X7, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X1, [SP, #136] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X9, X9, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X1, [SP, #160] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X12, X12, X1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W1, [SP, #124] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W1, W0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.LE 423e94 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x454> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| ADD X0, X0, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| B 423c84 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x244> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |