OV - exec - Loop 162

0x421fa8 CMP	W18, W23

0x421fac B.GE	42205c

0x421fb0 LDR	X5, [SP, #144]

0x421fb4 SUB	W13, W12, #1

0x421fb8 SUB	X14, X8, #8

0x421fbc SBFM	X1, X13, #0, #31

0x421fc0 MOVZ	X0, #0

0x421fc4 ORR	P0.B, P9/Z, P9.B, P9.B

0x421fc8 LDR	X9, [SP, #112]

0x421fcc SUB	X13, X7, #8

0x421fd0 MADD	X10, X22, X1, X5

0x421fd4 UBFM	X6, X10, #61, #60

0x421fd8 SUB	X5, X6, #8

0x421fdc ADD	X6, X17, X6

0x421fe0 ADD	X10, X17, X5

0x421fe4 LDR	X5, [SP, #136]

0x421fe8 MADD	X5, X21, X1, X5

0x421fec MADD	X1, X9, X1, X28

0x421ff0 UBFM	X5, X5, #61, #60

0x421ff4 SUB	X9, X5, #8

0x421ff8 ADD	X1, X27, X1,LSL #3

0x421ffc ADD	X5, X16, X5

0x422000 ADD	X9, X16, X9

  (163) 0x422004 LD1D	{Z22.D}, P0/Z, [X8, X0,LSL #3]

  (163) 0x422008 LD1D	{Z23.D}, P0/Z, [X7, X0,LSL #3]

  (163) 0x42200c LD1D	{Z24.D}, P0/Z, [X6, X0,LSL #3]

  (163) 0x422010 LD1D	{Z26.D}, P0/Z, [X5, X0,LSL #3]

  (163) 0x422014 LD1D	{Z27.D}, P0/Z, [X10, X0,LSL #3]

  (163) 0x422018 LD1D	{Z28.D}, P0/Z, [X9, X0,LSL #3]

  (163) 0x42201c LD1D	{Z29.D}, P0/Z, [X14, X0,LSL #3]

  (163) 0x422020 LD1D	{Z30.D}, P0/Z, [X13, X0,LSL #3]

  (163) 0x422024 FMUL	Z25.D, Z23.D, Z22.D

  (163) 0x422028 FMAD	Z26.D, P1/M, Z24.D, Z25.D

  (163) 0x42202c FMAD	Z27.D, P1/M, Z28.D, Z26.D

  (163) 0x422030 FMAD	Z30.D, P1/M, Z29.D, Z27.D

  (163) 0x422034 FMUL	Z31.D, Z30.D, Z21.D

  (163) 0x422038 ST1D	{Z31.D}, P0, [X3, X0,LSL #3]

  (163) 0x42203c LD1D	{Z0.D}, P0/Z, [X1, X0,LSL #3]

  (163) 0x422040 LD1D	{Z2.D}, P0/Z, [X11, X0,LSL #3]

  (163) 0x422044 FSUB	Z1.D, Z31.D, Z0.D

  (163) 0x422048 FADD	Z3.D, Z1.D, Z2.D

  (163) 0x42204c ST1D	{Z3.D}, P0, [X2, X0,LSL #3]

  (163) 0x422050 ADD	X0, X0, X15

  (163) 0x422054 WHILELO	P0.D, X0, X4

  (163) 0x422058 B.NE	422004

0x42205c ADD	W12, W12, #1

0x422060 ADD	X8, X8, X25

0x422064 ADD	X7, X7, X26

0x422068 ADD	X3, X3, X19

0x42206c ADD	X11, X11, X30

0x422070 ADD	X2, X2, X20

0x422074 CMP	W24, W12

0x422078 B.GT	421fa8

/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 207 - 208

--------------------------------------------------------------------------------

207:               +density1(j-1,k  )*post_vol(j-1,k  ))

208:             node_mass_pre(j,k)=node_mass_post(j,k)-node_flux(j,k-1)+node_flux(j,k)

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	advec_mom_kernel	advec_mom_kernel.f90:256	exec
○	advec_mom_driver	advec_mom_driver.f90:81	exec
○	advection	advection.f90:77	exec
○	hydro	hydro.f90:64	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec

Path /

Metric	Value
CQA speedup if no scalar integer	2.83
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.86
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.66
Bottlenecks
Function	advec_mom_kernel._omp_fn.0
Source	advec_mom_kernel.f90:207-208
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.25
CQA cycles if no scalar integer	1.50
CQA cycles if FP arith vectorized	4.25
CQA cycles if fully vectorized	0.88
Front-end cycles	2.56
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	4.25
P2 cycles	4.25
P3 cycles	4.25
P4 cycles	4.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.50
P10 cycles	0.50
P11 cycles	0.50
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	20.50
Nb uops	20.50
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.85
Bytes prefetched	0.00
Bytes loaded	12.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	2.38
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	16.67
Vector-efficiency ratio all	23.07
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	24.58
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.58

Metric	Value
CQA speedup if no scalar integer	6.50
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.84
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.68
Bottlenecks	P2, P3, P4, P5,
Function	advec_mom_kernel._omp_fn.0
Source	advec_mom_kernel.f90:207-208
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.50
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	6.50
CQA cycles if fully vectorized	1.34
Front-end cycles	3.88
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	6.50
P2 cycles	6.50
P3 cycles	6.50
P4 cycles	6.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.00
P10 cycles	1.00
P11 cycles	1.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	31.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.69
Bytes prefetched	0.00
Bytes loaded	24.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	4.76
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	33.33
Vector-efficiency ratio all	23.21
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	24.17
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.67

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.92
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.60
Bottlenecks	P2, P3, P4, P5,
Function	advec_mom_kernel._omp_fn.0
Source	advec_mom_kernel.f90:207-208
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.00
CQA cycles if no scalar integer	2.00
CQA cycles if FP arith vectorized	2.00
CQA cycles if fully vectorized	0.41
Front-end cycles	1.25
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	10.00
Nb uops	10.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	22.92
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel._omp_fn.0
Source file and lines	advec_mom_kernel.f90:207-208
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/advec_mom_kernel.f90:207-208.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.25 to 0.87 cycles (4.86x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization and with fassociative-math (included in Ofast or ffast-math) to extend vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 12 bytes.

General properties

nb instructions	20.50
loop length	82
nb stack references	0

Front-end

front end

2.56 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	0.50	0.50	0.50	0.00	0.00
cycles	1.00	1.00	4.25	4.25	4.25	4.25	0.00	0.00	0.00	0.00	0.50	0.50	0.50	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.56
Data deps.	1.00
Overall L1	4.25

Vectorization ratios

all	2%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.25 cycles. At this rate:

1% of peak load performance is reached (1.85 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Function	advec_mom_kernel._omp_fn.0
Source file and lines	advec_mom_kernel.f90:207-208
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/advec_mom_kernel.f90:207-208.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.50 to 1.00 cycles (6.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is probably not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.50 to 1.34 cycles (4.84x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization and with fassociative-math (included in Ofast or ffast-math) to extend vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 24 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	6.50	6.50	6.50	6.50	0.00	0.00	0.00	0.00	1.00	1.00	1.00	0.00	0.00
cycles	1.00	1.00	6.50	6.50	6.50	6.50	0.00	0.00	0.00	0.00	1.00	1.00	1.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.88
Data deps.	1.00
Overall L1	6.50

Vectorization ratios

all	4%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	33%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.50 cycles. At this rate:

3% of peak load performance is reached (3.69 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 421fa8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
CMP W18, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GE 42205c <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0xf1c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X5, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB W13, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X14, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SBFM X1, X13, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR P0.B, P9/Z, P9.B, P9.B	1	0	0	0	0	1	0	0	0	0	1	1
LDR X9, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB X13, X7, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
MADD X10, X22, X1, X5	1	0	0	0	0	1	0	0	0	0	2	1
UBFM X6, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X5, X6, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X6, X17, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X10, X17, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X5, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
MADD X5, X21, X1, X5	1	0	0	0	0	1	0	0	0	0	2	1
MADD X1, X9, X1, X28	1	0	0	0	0	1	0	0	0	0	2	1
UBFM X5, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB X9, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X1, X27, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X5, X16, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X9, X16, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W12, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X8, X8, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X7, X7, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X3, X3, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X11, X11, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X2, X2, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W24, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GT 421fa8 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0xe68>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	advec_mom_kernel._omp_fn.0
Source file and lines	advec_mom_kernel.f90:207-208
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/advec_mom_kernel.f90:207-208.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.00 to 0.41 cycles (4.92x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization and with fassociative-math (included in Ofast or ffast-math) to extend vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	10
loop length	40
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	2.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.25
Data deps.	1.00
Overall L1	2.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.00 cycles. At this rate:

ASM code

In the binary file, the address of the loop is: 421fa8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	Latency	Recip. throughput
CMP W18, W23	1	0	0	0.25	0.25	0.25	0.25	1	0.33
B.GE 42205c <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0xf1c>	1	0.50	0.50	0	0	0	0	1	0.50
ADD W12, W12, #1	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ADD X8, X8, X25	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ADD X7, X7, X26	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ADD X3, X3, X19	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ADD X11, X11, X30	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ADD X2, X2, X20	1	0	0	0.25	0.25	0.25	0.25	1	0.25
CMP W24, W12	1	0	0	0.25	0.25	0.25	0.25	1	0.33
B.GT 421fa8 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0xe68>	1	0.50	0.50	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code