OV - exec - Loop 161

0x4219a8 ADD	X6, X24, #1

0x4219ac ORR	W16, WZR, W9

0x4219b0 ADD	X15, X19, X6

0x4219b4 ORR	X3, XZR, X24

0x4219b8 CMP	W26, W25

0x4219bc B.LE	4219c8

0x4219c0 B	421a64

  (160) 0x4219c4 ADD	X6, X6, #1

  (160) 0x4219c8 LDR	D4, [X13, X3,LSL #3]

  (160) 0x4219cc ORR	X2, XZR, X9

  (160) 0x4219d0 SBFM	X7, X14, #0, #31

  (160) 0x4219d4 ORR	X5, XZR, X9

  (160) 0x4219d8 ORR	W0, WZR, W16

  (160) 0x4219dc FCMPE	D4, #0

  (160) 0x4219e0 B.MI	422140

  (160) 0x4219e4 SBFM	X7, X11, #0, #31

  (160) 0x4219e8 ORR	X5, XZR, X10

  (160) 0x4219ec ORR	W0, WZR, W11

  (160) 0x4219f0 ADD	X4, X22, W0,SXTW

  (160) 0x4219f4 ADD	X0, X27, X3

  (160) 0x4219f8 MOVI	D29, #0

  (160) 0x4219fc FABS	D20, D4

  (160) 0x421a00 LDR	D7, [X18, X10,LSL #3]

  (160) 0x421a04 MADD	X1, X7, X20, X0

  (160) 0x421a08 ADD	X7, X28, X3

  (160) 0x421a0c MADD	X2, X20, X2, X0

  (160) 0x421a10 MADD	X0, X20, X5, X0

  (160) 0x421a14 LDR	D21, [X8, X1,LSL #3]

  (160) 0x421a18 MADD	X5, X21, X5, X7

  (160) 0x421a1c LDR	D5, [X8, X0,LSL #3]

  (160) 0x421a20 LDR	D22, [X8, X2,LSL #3]

  (160) 0x421a24 LDR	D16, [X17, X5,LSL #3]

  (160) 0x421a28 FSUB	D23, D5, S21

  (160) 0x421a2c FSUB	D24, D22, S5

  (160) 0x421a30 FDIV	D25, D20, D16

  (160) 0x421a34 FABS	D26, D23

  (160) 0x421a38 FMUL	D28, D23, D24

  (160) 0x421a3c FABS	D27, D24

  (160) 0x421a40 FCMPE	D28, D29

  (160) 0x421a44 B.GT	422100

  (160) 0x421a48 FSUB	D24, D6, S25

  (160) 0x421a4c FMADD	D5, D29, D24, D5

  (160) 0x421a50 FMUL	D4, D4, D5

  (160) 0x421a54 STR	D4, [X12, X3,LSL #3]

  (160) 0x421a58 ORR	X3, XZR, X6

  (160) 0x421a5c CMP	X6, X15

  (160) 0x421a60 B.NE	4219c4

0x421a64 LDR	X15, [SP, #112]

0x421a68 ADD	X10, X10, #1

0x421a6c ADD	X9, X9, #1

0x421a70 ADD	W14, W14, #1

0x421a74 ADD	W11, W11, #1

0x421a78 LDR	X16, [SP, #136]

0x421a7c ADD	X12, X12, X15

0x421a80 ADD	X13, X13, X16

0x421a84 CMP	W23, W10

0x421a88 B.GT	4219a8

  (160) 0x422100 FADD	D31, D25, D6

  (160) 0x422104 FSUB	D2, D18, S25

  (160) 0x422108 LDR	D29, [X30, X4,LSL #3]

  (160) 0x42210c FCMPE	D24, #0

  (160) 0x422110 FMINNM	D30, D26, D27

  (160) 0x422114 FMUL	D0, D31, D26

  (160) 0x422118 FMUL	D3, D2, D27

  (160) 0x42211c FCSEL	D1, D19, D6, #9

  (160) 0x422120 FDIV	D20, D0, D29

  (160) 0x422124 FDIV	D21, D3, D7

  (160) 0x422128 FADD	D22, D20, D21

  (160) 0x42212c FMUL	D7, D22, D7

  (160) 0x422130 FDIV	D16, D7, D17

  (160) 0x422134 FMINNM	D23, D16, D30

  (160) 0x422138 FMUL	D29, D23, D1

  (160) 0x42213c B	421a48

  (160) 0x422140 ORR	X2, XZR, X10

  (160) 0x422144 B	4219f0

/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 214 - 240

--------------------------------------------------------------------------------

214:         DO j=x_min,x_max+1

215:           IF(node_flux(j,k).LT.0.0)THEN

216:             upwind=k+2

217:             donor=k+1

218:             downwind=k

219:             dif=donor

220:           ELSE

221:             upwind=k-1

222:             donor=k

223:             downwind=k+1

224:             dif=upwind

225:           ENDIF

226:

227:           sigma=ABS(node_flux(j,k))/(node_mass_pre(j,donor))

228:           width=celldy(k)

229:           vdiffuw=vel1(j,donor)-vel1(j,upwind)

230:           vdiffdw=vel1(j,downwind)-vel1(j,donor)

231:           limiter=0.0

232:           IF(vdiffuw*vdiffdw.GT.0.0)THEN

233:             auw=ABS(vdiffuw)

234:             adw=ABS(vdiffdw)

235:             wind=1.0_8

236:             IF(vdiffdw.LE.0.0) wind=-1.0_8

237:             limiter=wind*MIN(width*((2.0_8-sigma)*adw/width+(1.0_8+sigma)*auw/celldy(dif))/6.0_8,auw,adw)

238:           ENDIF

239:           advec_vel_s=vel1(j,donor)+(1.0_8-sigma)*limiter

240:           mom_flux(j,k)=advec_vel_s*node_flux(j,k)

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	advec_mom_kernel	advec_mom_kernel.f90:256	exec
○	advec_mom_driver	advec_mom_driver.f90:81	exec
○	advection	advection.f90:105	exec
○	hydro	hydro.f90:64	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.41
Bottlenecks	P2, P3, P4, P5,
Function	advec_mom_kernel._omp_fn.0
Source	advec_mom_kernel.f90:214-214,advec_mom_kernel.f90:227-227
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.56
Front-end cycles	2.13
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.67
P10 cycles	0.67
P11 cycles	0.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	17.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.33
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	20.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	21.43
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.67

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.41
Bottlenecks	P2, P3, P4, P5,
Function	advec_mom_kernel._omp_fn.0
Source	advec_mom_kernel.f90:214-214,advec_mom_kernel.f90:227-227
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.00
CQA cycles if no scalar integer	3.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	0.56
Front-end cycles	2.13
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.67
P10 cycles	0.67
P11 cycles	0.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	17.00
Nb uops	17.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	5.33
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	20.00
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	21.43
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.67

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel._omp_fn.0
Source file and lines	advec_mom_kernel.f90:214-240
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/advec_mom_kernel.f90:214-240.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/advec_mom_kernel.f90:214,227.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=9
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 9 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 20% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.56 cycles (5.33x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization and with fassociative-math (included in Ofast or ffast-math) to extend vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 16 bytes.

General properties

nb instructions	17
loop length	68
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00
cycles	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.13
Overall L1	3.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

5% of peak load performance is reached (5.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4219a8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
ADD X6, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W16, WZR, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X15, X19, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR X3, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W26, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LE 4219c8 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x888>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
B 421a64 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x924>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X15, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X10, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W14, W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W11, W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X16, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X12, X12, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X13, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W23, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GT 4219a8 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x868>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	advec_mom_kernel._omp_fn.0
Source file and lines	advec_mom_kernel.f90:214-240
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/advec_mom_kernel.f90:214-240.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/advec_mom_kernel.f90:214,227.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=9
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 9 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 20% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.00 to 0.56 cycles (5.33x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization and with fassociative-math (included in Ofast or ffast-math) to extend vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 16 bytes.

General properties

nb instructions	17
loop length	68
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00
cycles	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.13
Overall L1	3.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.00 cycles. At this rate:

5% of peak load performance is reached (5.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4219a8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
ADD X6, X24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR W16, WZR, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X15, X19, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ORR X3, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W26, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.LE 4219c8 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x888>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
B 421a64 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x924>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X15, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X10, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X9, X9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W14, W14, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD W11, W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X16, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X12, X12, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X13, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W23, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GT 4219a8 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x868>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code