OV - exec - Loop 128

0x41f9d0 ADD	X17, X30, X27,LSL #3

0x41f9d4 SBFM	X0, X28, #0, #31

0x41f9d8 CMP	W28, W13

0x41f9dc B.GT	41fad8

  (129) 0x41f9e0 LDR	D23, [X17, X0,LSL #3]

  (129) 0x41f9e4 ORR	X6, XZR, X0

  (129) 0x41f9e8 ADD	W3, W0, #1

  (129) 0x41f9ec SUB	X1, X0, #1

  (129) 0x41f9f0 FCMPE	D23, #0

  (129) 0x41f9f4 B.GT	41fec4

  (129) 0x41f9f8 CMP	W3, W13

  (129) 0x41f9fc CSEL	W2, W3, W13, #13

  (129) 0x41fa00 SBFM	X11, X2, #0, #31

  (129) 0x41fa04 ORR	X6, XZR, X1

  (129) 0x41fa08 ORR	X2, XZR, X11

  (129) 0x41fa0c ORR	X1, XZR, X0

  (129) 0x41fa10 ADD	X10, X16, X1

  (129) 0x41fa14 FABS	D1, D23

  (129) 0x41fa18 ADD	X3, X25, X11

  (129) 0x41fa1c ADD	X4, X7, X6

  (129) 0x41fa20 ADD	X11, X7, X1

  (129) 0x41fa24 LDR	D7, [X24, X0,LSL #3]

  (129) 0x41fa28 LDR	D2, [X12, X10,LSL #3]

  (129) 0x41fa2c LDR	D18, [X18, X3,LSL #3]

  (129) 0x41fa30 ADD	X3, X7, X2

  (129) 0x41fa34 LDR	D17, [X5, X11,LSL #3]

  (129) 0x41fa38 FDIV	D27, D1, D2

  (129) 0x41fa3c LDR	D0, [X5, X4,LSL #3]

  (129) 0x41fa40 LDR	D21, [X5, X3,LSL #3]

  (129) 0x41fa44 FDIV	D16, D7, D18

  (129) 0x41fa48 FSUB	D28, D0, S17

  (129) 0x41fa4c FSUB	D29, D17, S21

  (129) 0x41fa50 FCMPE	D28, #0

  (129) 0x41fa54 FMUL	D30, D29, D28

  (129) 0x41fa58 FADD	D31, D27, D3

  (129) 0x41fa5c FSUB	D24, D6, S27

  (129) 0x41fa60 FCSEL	D25, D22, D3, #9

  (129) 0x41fa64 FCMPE	D30, #0

  (129) 0x41fa68 FMUL	D26, D16, D31

  (129) 0x41fa6c B.GT	41fe98

  (129) 0x41fa70 MOVI	D21, #0

  (129) 0x41fa74 FADD	D17, D21, D17

  (129) 0x41fa78 ADD	X1, X8, X1

  (129) 0x41fa7c ADD	X6, X8, X6

  (129) 0x41fa80 ADD	X2, X8, X2

  (129) 0x41fa84 FMUL	D23, D17, D23

  (129) 0x41fa88 STR	D23, [X15, X0,LSL #3]

  (129) 0x41fa8c LDR	D16, [X9, X1,LSL #3]

  (129) 0x41fa90 LDR	D28, [X9, X6,LSL #3]

  (129) 0x41fa94 LDR	D29, [X9, X2,LSL #3]

  (129) 0x41fa98 LDR	D30, [X5, X11,LSL #3]

  (129) 0x41fa9c FSUB	D31, D28, S16

  (129) 0x41faa0 LDR	D25, [X12, X10,LSL #3]

  (129) 0x41faa4 FSUB	D4, D16, S29

  (129) 0x41faa8 FCMPE	D31, #0

  (129) 0x41faac FMUL	D19, D4, D31

  (129) 0x41fab0 FCSEL	D20, D22, D3, #9

  (129) 0x41fab4 FCMPE	D19, #0

  (129) 0x41fab8 B.GT	41fe60

  (129) 0x41fabc MOVI	D30, #0

  (129) 0x41fac0 FADD	D16, D30, D16

  (129) 0x41fac4 FMUL	D23, D16, D23

  (129) 0x41fac8 STR	D23, [X14, X0,LSL #3]

  (129) 0x41facc ADD	X0, X0, #1

  (129) 0x41fad0 CMP	W13, W0

  (129) 0x41fad4 B.GE	41f9e0

0x41fad8 LDR	W10, [SP, #112]

0x41fadc ADD	W26, W26, #1

0x41fae0 ADD	X14, X14, X19

0x41fae4 ADD	X15, X15, X20

0x41fae8 ADD	X8, X8, X21

0x41faec LDR	X17, [SP, #96]

0x41faf0 ADD	X16, X16, X23

0x41faf4 ADD	X7, X7, X22

0x41faf8 ADD	X27, X27, X17

0x41fafc CMP	W10, W26

0x41fb00 B.GT	41f9d0

  (129) 0x41fe60 FMUL	D18, D30, D25

  (129) 0x41fe64 FABS	D2, D23

  (129) 0x41fe68 FABS	D1, D31

  (129) 0x41fe6c FABS	D7, D4

  (129) 0x41fe70 FMINNM	D27, D1, D7

  (129) 0x41fe74 FMUL	D24, D24, D1

  (129) 0x41fe78 FDIV	D0, D2, D18

  (129) 0x41fe7c FMADD	D26, D26, D7, D24

  (129) 0x41fe80 FMUL	D21, D26, D5

  (129) 0x41fe84 FMINNM	D17, D21, D27

  (129) 0x41fe88 FSUB	D28, D3, S0

  (129) 0x41fe8c FMUL	D29, D28, D20

  (129) 0x41fe90 FMUL	D30, D29, D17

  (129) 0x41fe94 B	41fac0

  (129) 0x41fe98 FABS	D20, D28

  (129) 0x41fe9c FABS	D4, D29

  (129) 0x41fea0 FMINNM	D19, D20, D4

  (129) 0x41fea4 FSUB	D1, D3, S27

  (129) 0x41fea8 FMUL	D7, D24, D20

  (129) 0x41feac FMUL	D2, D1, D25

  (129) 0x41feb0 FMADD	D18, D26, D4, D7

  (129) 0x41feb4 FMUL	D27, D18, D5

  (129) 0x41feb8 FMINNM	D0, D27, D19

  (129) 0x41febc FMUL	D21, D0, D2

  (129) 0x41fec0 B	41fa74

  (129) 0x41fec4 SUB	W4, W0, #2

  (129) 0x41fec8 ORR	X11, XZR, X1

  (129) 0x41fecc SBFM	X2, X4, #0, #31

  (129) 0x41fed0 B	41fa10

/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 110 - 155

--------------------------------------------------------------------------------

110:         DO j=x_min,x_max+2

111:

112:           IF(vol_flux_x(j,k).GT.0.0)THEN

[...]

118:             upwind   =MIN(j+1,x_max+2)

[...]

124:           sigmat=ABS(vol_flux_x(j,k))/pre_vol(donor,k)

125:           sigma3=(1.0_8+sigmat)*(vertexdx(j)/vertexdx(dif))

126:           sigma4=2.0_8-sigmat

127:

128:           sigma=sigmat

129:           sigmav=sigmat

130:

131:           diffuw=density1(donor,k)-density1(upwind,k)

132:           diffdw=density1(downwind,k)-density1(donor,k)

133:           wind=1.0_8

134:           IF(diffdw.LE.0.0) wind=-1.0_8

135:           IF(diffuw*diffdw.GT.0.0)THEN

136:             limiter=(1.0_8-sigmav)*wind*MIN(ABS(diffuw),ABS(diffdw)&

137:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

138:           ELSE

139:             limiter=0.0

140:           ENDIF

141:           mass_flux_x(j,k)=vol_flux_x(j,k)*(density1(donor,k)+limiter)

142:

143:           sigmam=ABS(mass_flux_x(j,k))/(density1(donor,k)*pre_vol(donor,k))

144:           diffuw=energy1(donor,k)-energy1(upwind,k)

145:           diffdw=energy1(downwind,k)-energy1(donor,k)

146:           wind=1.0_8

147:           IF(diffdw.LE.0.0) wind=-1.0_8

148:           IF(diffuw*diffdw.GT.0.0)THEN

149:             limiter=(1.0_8-sigmam)*wind*MIN(ABS(diffuw),ABS(diffdw)&

150:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

151:           ELSE

152:             limiter=0.0

153:           ENDIF

154:

155:           ener_flux(j,k)=mass_flux_x(j,k)*(energy1(donor,k)+limiter)

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	advec_cell_kernel	advec_cell_kernel.f90:270	exec
○	advec_cell_driver	advec_cell_driver.f90:84	exec
○	advection	advection.f90:57	exec
○	hydro	hydro.f90:64	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.89
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.47
Bottlenecks	P2, P3, P4, P5,
Function	advec_cell_kernel._omp_fn.0
Source	advec_cell_kernel.f90:110-110,advec_cell_kernel.f90:124-124
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.75
CQA cycles if no scalar integer	2.75
CQA cycles if FP arith vectorized	2.75
CQA cycles if fully vectorized	0.56
Front-end cycles	1.88
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	2.75
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	2.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.67
P10 cycles	0.67
P11 cycles	0.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	15.00
Nb uops	15.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.36
Bytes prefetched	0.00
Bytes loaded	12.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.44
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.89
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.47
Bottlenecks	P2, P3, P4, P5,
Function	advec_cell_kernel._omp_fn.0
Source	advec_cell_kernel.f90:110-110,advec_cell_kernel.f90:124-124
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.75
CQA cycles if no scalar integer	2.75
CQA cycles if FP arith vectorized	2.75
CQA cycles if fully vectorized	0.56
Front-end cycles	1.88
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	2.75
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	2.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.67
P10 cycles	0.67
P11 cycles	0.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	15.00
Nb uops	15.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.36
Bytes prefetched	0.00
Bytes loaded	12.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.44
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_cell_kernel._omp_fn.0
Source file and lines	advec_cell_kernel.f90:110-155
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/advec_cell_kernel.f90:110-112,118,124-155.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/advec_cell_kernel.f90:110,124.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=9
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 9 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.75 to 0.56 cycles (4.89x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization and with fassociative-math (included in Ofast or ffast-math) to extend vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 12 bytes.

General properties

nb instructions	15
loop length	60
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00
cycles	1.00	1.00	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.88
Overall L1	2.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.75 cycles. At this rate:

4% of peak load performance is reached (4.36 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41f9d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
ADD X17, X30, X27,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SBFM X0, X28, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W28, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GT 41fad8 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x9f8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W10, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD W26, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X14, X14, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X15, X15, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X8, X8, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X17, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X16, X16, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X7, X7, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X27, X27, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W10, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GT 41f9d0 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x8f0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	advec_cell_kernel._omp_fn.0
Source file and lines	advec_cell_kernel.f90:110-155
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/advec_cell_kernel.f90:110-112,118,124-155.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/advec_cell_kernel.f90:110,124.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=9
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 9 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.75 to 0.56 cycles (4.89x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization and with fassociative-math (included in Ofast or ffast-math) to extend vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 12 bytes.

General properties

nb instructions	15
loop length	60
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00
cycles	1.00	1.00	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	1.88
Overall L1	2.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.75 cycles. At this rate:

4% of peak load performance is reached (4.36 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41f9d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
ADD X17, X30, X27,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SBFM X0, X28, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W28, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GT 41fad8 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x9f8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR W10, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD W26, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X14, X14, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X15, X15, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X8, X8, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X17, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X16, X16, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X7, X7, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X27, X27, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP W10, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
B.GT 41f9d0 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x8f0>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

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ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code