OV - exec - Loop 121

	Loop Id: 121	Module: exec	Source: advec_cell_kernel.f90:202-246 [...]	Coverage: 6.27%

0x41f448 LDR	D27, [X14, X1,LSL #3]    [5]

0x41f44c ORR	X5, XZR, X8

0x41f450 FCMPE	D27, #0

0x41f454 B.GT	41ff38

0x41f458 CMP	W26, W20

0x41f45c CSEL	W6, W26, W20, #13

0x41f460 SBFM	X12, X6, #0, #31

0x41f464 ORR	X10, XZR, X12

0x41f468 ORR	X7, XZR, X8

0x41f46c ORR	X5, XZR, X16

0x41f470 MADD	X2, X23, X5, X27

0x41f474 FABS	D1, D27

0x41f478 ADD	X4, X19, X1

0x41f47c MADD	X3, X22, X5, X19

0x41f480 ADD	X6, X24, X12

0x41f484 LDR	D3, [X18, X8,LSL #3]    [3]

0x41f488 MADD	X12, X22, X7, X4

0x41f48c ADD	X2, X2, X1

0x41f490 MADD	X4, X22, X10, X4

0x41f494 LDR	D2, [X25, X6,LSL #3]    [4]

0x41f498 ADD	X3, X3, X1

0x41f49c LDR	D4, [X11, X2,LSL #3]    [12]

0x41f4a0 LDR	D5, [X0, X3,LSL #3]    [11]

0x41f4a4 LDR	D0, [X0, X12,LSL #3]    [7]

0x41f4a8 FDIV	D6, D3, D2

0x41f4ac LDR	D7, [X0, X4,LSL #3]    [2]

0x41f4b0 FDIV	D17, D1, D4

0x41f4b4 FSUB	D21, D0, S5

0x41f4b8 FSUB	D22, D5, S7

0x41f4bc FCMPE	D21, #0

0x41f4c0 FMUL	D16, D22, D21

0x41f4c4 FCSEL	D20, D29, D28, #9

0x41f4c8 FCMPE	D16, #0

0x41f4cc FADD	D19, D17, D28

0x41f4d0 FSUB	D18, D31, S17

0x41f4d4 FMUL	D23, D6, D19

0x41f4d8 B.GT	41ff0c

0x41f4dc MOVI	D7, #0

0x41f4e0 FADD	D5, D7, D5

0x41f4e4 ADD	X6, X28, X1

0x41f4e8 MADD	X5, X21, X5, X6

0x41f4ec MADD	X7, X21, X7, X6

0x41f4f0 MADD	X10, X21, X10, X6

0x41f4f4 FMUL	D27, D5, D27

0x41f4f8 STR	D27, [X15, X1,LSL #3]    [1]

0x41f4fc LDR	D17, [X9, X5,LSL #3]    [9]

0x41f500 LDR	D21, [X9, X7,LSL #3]    [10]

0x41f504 LDR	D22, [X9, X10,LSL #3]    [8]

0x41f508 LDR	D16, [X0, X3,LSL #3]    [11]

0x41f50c FSUB	D24, D21, S17

0x41f510 LDR	D25, [X11, X2,LSL #3]    [12]

0x41f514 FSUB	D26, D17, S22

0x41f518 FCMPE	D24, #0

0x41f51c FMUL	D19, D26, D24

0x41f520 FCSEL	D20, D29, D28, #9

0x41f524 FCMPE	D19, #0

0x41f528 B.GT	41fed4

0x41f52c MOVI	D16, #0

0x41f530 FADD	D17, D16, D17

0x41f534 FMUL	D27, D17, D27

0x41f538 STR	D27, [X13, X1,LSL #3]    [6]

0x41f53c ADD	X1, X1, #1

0x41f540 CMP	W17, W1

0x41f544 B.GE	41f448

0x41fed4 FMUL	D3, D16, D25

0x41fed8 FABS	D2, D27

0x41fedc FABS	D1, D24

0x41fee0 FABS	D4, D26

0x41fee4 FMINNM	D0, D1, D4

0x41fee8 FMUL	D18, D18, D1

0x41feec FDIV	D6, D2, D3

0x41fef0 FMADD	D23, D23, D4, D18

0x41fef4 FMUL	D7, D23, D30

0x41fef8 FMINNM	D5, D7, D0

0x41fefc FSUB	D21, D28, S6

0x41ff00 FMUL	D22, D21, D20

0x41ff04 FMUL	D16, D22, D5

0x41ff08 B	41f530

0x41ff0c FABS	D24, D21

0x41ff10 FABS	D25, D22

0x41ff14 FMINNM	D26, D24, D25

0x41ff18 FSUB	D1, D28, S17

0x41ff1c FMUL	D3, D18, D24

0x41ff20 FMUL	D2, D1, D20

0x41ff24 FMADD	D4, D23, D25, D3

0x41ff28 FMUL	D0, D4, D30

0x41ff2c FMINNM	D6, D0, D26

0x41ff30 FMUL	D7, D6, D2

0x41ff34 B	41f4e0

0x41ff38 ORR	X10, XZR, X30

0x41ff3c ORR	X7, XZR, X16

0x41ff40 ORR	X12, XZR, X8

0x41ff44 B	41f470

/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 202 - 246

--------------------------------------------------------------------------------

202:         DO j=x_min,x_max

203:

204:           IF(vol_flux_y(j,k).GT.0.0)THEN

[...]

210:             upwind   =MIN(k+1,y_max+2)

[...]

216:           sigmat=ABS(vol_flux_y(j,k))/pre_vol(j,donor)

217:           sigma3=(1.0_8+sigmat)*(vertexdy(k)/vertexdy(dif))

218:           sigma4=2.0_8-sigmat

219:

220:           sigma=sigmat

221:           sigmav=sigmat

222:

223:           diffuw=density1(j,donor)-density1(j,upwind)

224:           diffdw=density1(j,downwind)-density1(j,donor)

225:           wind=1.0_8

226:           IF(diffdw.LE.0.0) wind=-1.0_8

227:           IF(diffuw*diffdw.GT.0.0)THEN

228:             limiter=(1.0_8-sigmav)*wind*MIN(ABS(diffuw),ABS(diffdw)&

229:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

230:           ELSE

231:             limiter=0.0

232:           ENDIF

233:           mass_flux_y(j,k)=vol_flux_y(j,k)*(density1(j,donor)+limiter)

234:

235:           sigmam=ABS(mass_flux_y(j,k))/(density1(j,donor)*pre_vol(j,donor))

236:           diffuw=energy1(j,donor)-energy1(j,upwind)

237:           diffdw=energy1(j,downwind)-energy1(j,donor)

238:           wind=1.0_8

239:           IF(diffdw.LE.0.0) wind=-1.0_8

240:           IF(diffuw*diffdw.GT.0.0)THEN

241:             limiter=(1.0_8-sigmam)*wind*MIN(ABS(diffuw),ABS(diffdw)&

242:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

243:           ELSE

244:             limiter=0.0

245:           ENDIF

246:           ener_flux(j,k)=mass_flux_y(j,k)*(energy1(j,donor)+limiter)

Coverage (%)	Name	Source Location	Module
►50.56+	GOMP_parallel		libgomp.so.1.0.0
○	advec_cell_kernel	advec_cell_kernel.f90:270	exec
○	advec_cell_driver	advec_cell_driver.f90:84	exec
○	advection	advection.f90:88	exec
○	hydro	hydro.f90:64	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec
►49.44+	GOMP_parallel		libgomp.so.1.0.0
○	advec_cell_kernel	advec_cell_kernel.f90:270	exec
○	advec_cell_driver	advec_cell_driver.f90:84	exec
○	advection	advection.f90:57	exec
○	hydro	hydro.f90:64	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec

Path /

Metric	Value
CQA speedup if no scalar integer	2.68
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.48
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	P6, P7, P8, P9,
Function	advec_cell_kernel._omp_fn.0
Source	advec_cell_kernel.f90:202-204,advec_cell_kernel.f90:210-210,advec_cell_kernel.f90:216-246
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.50
CQA cycles if no scalar integer	4.67
CQA cycles if FP arith vectorized	12.50
CQA cycles if fully vectorized	1.67
Front-end cycles	11.63
DIV/SQRT cycles	3.50
P0 cycles	3.50
P1 cycles	5.75
P2 cycles	5.75
P3 cycles	7.00
P4 cycles	5.50
P5 cycles	12.50
P6 cycles	12.50
P7 cycles	12.50
P8 cycles	12.50
P9 cycles	4.67
P10 cycles	4.67
P11 cycles	4.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	3.00 - 1.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	93.00
Nb uops	93.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.48
Nb FLOP add-sub	10.00
Nb FLOP mul	14.00
Nb FLOP fma	2.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.96
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.61
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Metric	Value
CQA speedup if no scalar integer	2.68
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.48
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	P6, P7, P8, P9,
Function	advec_cell_kernel._omp_fn.0
Source	advec_cell_kernel.f90:202-204,advec_cell_kernel.f90:210-210,advec_cell_kernel.f90:216-246
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.50
CQA cycles if no scalar integer	4.67
CQA cycles if FP arith vectorized	12.50
CQA cycles if fully vectorized	1.67
Front-end cycles	11.63
DIV/SQRT cycles	3.50
P0 cycles	3.50
P1 cycles	5.75
P2 cycles	5.75
P3 cycles	7.00
P4 cycles	5.50
P5 cycles	12.50
P6 cycles	12.50
P7 cycles	12.50
P8 cycles	12.50
P9 cycles	4.67
P10 cycles	4.67
P11 cycles	4.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	3.00 - 1.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	93.00
Nb uops	93.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.48
Nb FLOP add-sub	10.00
Nb FLOP mul	14.00
Nb FLOP fma	2.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.96
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.61
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_cell_kernel._omp_fn.0
Source file and lines	advec_cell_kernel.f90:202-246
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/advec_cell_kernel.f90:202-204,210,216-246.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.50 to 4.67 cycles (2.68x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 12.50 to 1.67 cycles (7.48x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization and with fassociative-math (included in Ofast or ffast-math) to extend vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 2 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 31 FP arithmetical operations:

12: addition or subtraction (2 inside FMA instructions)
16: multiply (2 inside FMA instructions)
3: divide

The binary loop is loading 96 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.28 FP operations per loaded or stored byte.

General properties

nb instructions	93
loop length	372
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	5.75	5.75	7.00	5.50	12.50	12.50	12.50	12.50	4.67	4.67	4.67	0.00	0.00
cycles	3.50	3.50	5.75	5.75	7.00	5.50	12.50	12.50	12.50	12.50	4.67	4.67	4.67	0.00	0.00

Cycles executing div or sqrt instructions

3.00-1.50

Cycles summary

Front-end	11.63
Overall L1	12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.50 cycles. At this rate:

8% of peak load performance is reached (7.68 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.28 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41f448

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR D27, [X14, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ORR X5, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FCMPE D27, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GT 41ff38 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0xe58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W26, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
CSEL W6, W26, W20, #13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X12, X6, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X10, XZR, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X7, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X5, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X2, X23, X5, X27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FABS D1, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
ADD X4, X19, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X3, X22, X5, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X6, X24, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D3, [X18, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MADD X12, X22, X7, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X2, X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X4, X22, X10, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR D2, [X25, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X3, X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D4, [X11, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D5, [X0, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D0, [X0, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FDIV D6, D3, D2	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
LDR D7, [X0, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FDIV D17, D1, D4	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FSUB D21, D0, S5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D22, D5, S7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMPE D21, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FMUL D16, D22, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCSEL D20, D29, D28, #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMPE D16, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FADD D19, D17, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D18, D31, S17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D23, D6, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
B.GT 41ff0c <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0xe2c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVI D7, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D5, D7, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
ADD X6, X28, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X5, X21, X5, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X7, X21, X7, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X10, X21, X10, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FMUL D27, D5, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR D27, [X15, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D17, [X9, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D21, [X9, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D22, [X9, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D16, [X0, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSUB D24, D21, S17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR D25, [X11, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSUB D26, D17, S22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMPE D24, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FMUL D19, D26, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCSEL D20, D29, D28, #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMPE D19, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GT 41fed4 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0xdf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVI D16, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D17, D16, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D27, D17, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR D27, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W17, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 41f448 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMUL D3, D16, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FABS D2, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FABS D1, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FABS D4, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMINNM D0, D1, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D18, D18, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FDIV D6, D2, D3	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FMADD D23, D23, D4, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D7, D23, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMINNM D5, D7, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D21, D28, S6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D22, D21, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL D16, D22, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
B 41f530 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FABS D24, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FABS D25, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMINNM D26, D24, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D1, D28, S17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D3, D18, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL D2, D1, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D4, D23, D25, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D0, D4, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMINNM D6, D0, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D7, D6, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
B 41f4e0 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X10, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X7, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X12, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B 41f470 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	advec_cell_kernel._omp_fn.0
Source file and lines	advec_cell_kernel.f90:202-246
Module	exec

Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.50 to 4.67 cycles (2.68x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization and with fassociative-math (included in Ofast or ffast-math) to extend vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 2 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 31 FP arithmetical operations:

12: addition or subtraction (2 inside FMA instructions)
16: multiply (2 inside FMA instructions)
3: divide

The binary loop is loading 96 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.28 FP operations per loaded or stored byte.

General properties

nb instructions	93
loop length	372
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.50	3.50	5.75	5.75	7.00	5.50	12.50	12.50	12.50	12.50	4.67	4.67	4.67	0.00	0.00
cycles	3.50	3.50	5.75	5.75	7.00	5.50	12.50	12.50	12.50	12.50	4.67	4.67	4.67	0.00	0.00

Cycles executing div or sqrt instructions

3.00-1.50

Cycles summary

Front-end	11.63
Overall L1	12.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.50 cycles. At this rate:

8% of peak load performance is reached (7.68 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.28 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41f448

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR D27, [X14, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ORR X5, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FCMPE D27, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GT 41ff38 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0xe58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W26, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
CSEL W6, W26, W20, #13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X12, X6, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X10, XZR, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X7, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X5, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X2, X23, X5, X27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FABS D1, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
ADD X4, X19, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X3, X22, X5, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X6, X24, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D3, [X18, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MADD X12, X22, X7, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X2, X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X4, X22, X10, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR D2, [X25, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X3, X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D4, [X11, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D5, [X0, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D0, [X0, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FDIV D6, D3, D2	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
LDR D7, [X0, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FDIV D17, D1, D4	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FSUB D21, D0, S5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D22, D5, S7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMPE D21, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FMUL D16, D22, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCSEL D20, D29, D28, #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMPE D16, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FADD D19, D17, D28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D18, D31, S17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D23, D6, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
B.GT 41ff0c <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0xe2c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVI D7, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D5, D7, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
ADD X6, X28, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X5, X21, X5, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X7, X21, X7, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X10, X21, X10, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FMUL D27, D5, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR D27, [X15, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D17, [X9, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D21, [X9, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D22, [X9, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D16, [X0, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSUB D24, D21, S17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR D25, [X11, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSUB D26, D17, S22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMPE D24, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FMUL D19, D26, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCSEL D20, D29, D28, #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMPE D19, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GT 41fed4 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0xdf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVI D16, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D17, D16, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D27, D17, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR D27, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W17, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 41f448 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMUL D3, D16, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FABS D2, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FABS D1, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FABS D4, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMINNM D0, D1, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D18, D18, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FDIV D6, D2, D3	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FMADD D23, D23, D4, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D7, D23, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMINNM D5, D7, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D21, D28, S6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D22, D21, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL D16, D22, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
B 41f530 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FABS D24, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FABS D25, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMINNM D26, D24, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D1, D28, S17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D3, D18, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL D2, D1, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D4, D23, D25, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D0, D4, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMINNM D6, D0, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D7, D6, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
B 41f4e0 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X10, XZR, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X7, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X12, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B 41f470 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code