OV - exec - Loop 120

0x41f428 LDR	W7, [SP, #96]

0x41f42c ADD	X16, X8, #1

0x41f430 LDR	W3, [SP, #168]

0x41f434 ADD	W20, W7, #3

0x41f438 SBFM	X30, X7, #0, #31

0x41f43c SBFM	X1, X3, #0, #31

0x41f440 CMP	W3, W17

0x41f444 B.GT	41f548

  (121) 0x41f448 LDR	D27, [X14, X1,LSL #3]

  (121) 0x41f44c ORR	X5, XZR, X8

  (121) 0x41f450 FCMPE	D27, #0

  (121) 0x41f454 B.GT	41ff38

  (121) 0x41f458 CMP	W26, W20

  (121) 0x41f45c CSEL	W6, W26, W20, #13

  (121) 0x41f460 SBFM	X12, X6, #0, #31

  (121) 0x41f464 ORR	X10, XZR, X12

  (121) 0x41f468 ORR	X7, XZR, X8

  (121) 0x41f46c ORR	X5, XZR, X16

  (121) 0x41f470 MADD	X2, X23, X5, X27

  (121) 0x41f474 FABS	D1, D27

  (121) 0x41f478 ADD	X4, X19, X1

  (121) 0x41f47c MADD	X3, X22, X5, X19

  (121) 0x41f480 ADD	X6, X24, X12

  (121) 0x41f484 LDR	D3, [X18, X8,LSL #3]

  (121) 0x41f488 MADD	X12, X22, X7, X4

  (121) 0x41f48c ADD	X2, X2, X1

  (121) 0x41f490 MADD	X4, X22, X10, X4

  (121) 0x41f494 LDR	D2, [X25, X6,LSL #3]

  (121) 0x41f498 ADD	X3, X3, X1

  (121) 0x41f49c LDR	D4, [X11, X2,LSL #3]

  (121) 0x41f4a0 LDR	D5, [X0, X3,LSL #3]

  (121) 0x41f4a4 LDR	D0, [X0, X12,LSL #3]

  (121) 0x41f4a8 FDIV	D6, D3, D2

  (121) 0x41f4ac LDR	D7, [X0, X4,LSL #3]

  (121) 0x41f4b0 FDIV	D17, D1, D4

  (121) 0x41f4b4 FSUB	D21, D0, S5

  (121) 0x41f4b8 FSUB	D22, D5, S7

  (121) 0x41f4bc FCMPE	D21, #0

  (121) 0x41f4c0 FMUL	D16, D22, D21

  (121) 0x41f4c4 FCSEL	D20, D29, D28, #9

  (121) 0x41f4c8 FCMPE	D16, #0

  (121) 0x41f4cc FADD	D19, D17, D28

  (121) 0x41f4d0 FSUB	D18, D31, S17

  (121) 0x41f4d4 FMUL	D23, D6, D19

  (121) 0x41f4d8 B.GT	41ff0c

  (121) 0x41f4dc MOVI	D7, #0

  (121) 0x41f4e0 FADD	D5, D7, D5

  (121) 0x41f4e4 ADD	X6, X28, X1

  (121) 0x41f4e8 MADD	X5, X21, X5, X6

  (121) 0x41f4ec MADD	X7, X21, X7, X6

  (121) 0x41f4f0 MADD	X10, X21, X10, X6

  (121) 0x41f4f4 FMUL	D27, D5, D27

  (121) 0x41f4f8 STR	D27, [X15, X1,LSL #3]

  (121) 0x41f4fc LDR	D17, [X9, X5,LSL #3]

  (121) 0x41f500 LDR	D21, [X9, X7,LSL #3]

  (121) 0x41f504 LDR	D22, [X9, X10,LSL #3]

  (121) 0x41f508 LDR	D16, [X0, X3,LSL #3]

  (121) 0x41f50c FSUB	D24, D21, S17

  (121) 0x41f510 LDR	D25, [X11, X2,LSL #3]

  (121) 0x41f514 FSUB	D26, D17, S22

  (121) 0x41f518 FCMPE	D24, #0

  (121) 0x41f51c FMUL	D19, D26, D24

  (121) 0x41f520 FCSEL	D20, D29, D28, #9

  (121) 0x41f524 FCMPE	D19, #0

  (121) 0x41f528 B.GT	41fed4

  (121) 0x41f52c MOVI	D16, #0

  (121) 0x41f530 FADD	D17, D16, D17

  (121) 0x41f534 FMUL	D27, D17, D27

  (121) 0x41f538 STR	D27, [X13, X1,LSL #3]

  (121) 0x41f53c ADD	X1, X1, #1

  (121) 0x41f540 CMP	W17, W1

  (121) 0x41f544 B.GE	41f448

0x41f548 LDR	W12, [SP, #96]

0x41f54c ORR	X8, XZR, X16

0x41f550 LDR	W3, [SP, #144]

0x41f554 LDR	X16, [SP, #176]

0x41f558 ADD	W2, W12, #1

0x41f55c LDR	X30, [SP, #192]

0x41f560 STR	W2, [SP, #96]

0x41f564 LDR	X4, [SP, #200]

0x41f568 ADD	X13, X13, X16

0x41f56c ADD	X15, X15, X30

0x41f570 ADD	X14, X14, X4

0x41f574 CMP	W3, W20

0x41f578 B.GT	41f428

  (121) 0x41fed4 FMUL	D3, D16, D25

  (121) 0x41fed8 FABS	D2, D27

  (121) 0x41fedc FABS	D1, D24

  (121) 0x41fee0 FABS	D4, D26

  (121) 0x41fee4 FMINNM	D0, D1, D4

  (121) 0x41fee8 FMUL	D18, D18, D1

  (121) 0x41feec FDIV	D6, D2, D3

  (121) 0x41fef0 FMADD	D23, D23, D4, D18

  (121) 0x41fef4 FMUL	D7, D23, D30

  (121) 0x41fef8 FMINNM	D5, D7, D0

  (121) 0x41fefc FSUB	D21, D28, S6

  (121) 0x41ff00 FMUL	D22, D21, D20

  (121) 0x41ff04 FMUL	D16, D22, D5

  (121) 0x41ff08 B	41f530

  (121) 0x41ff0c FABS	D24, D21

  (121) 0x41ff10 FABS	D25, D22

  (121) 0x41ff14 FMINNM	D26, D24, D25

  (121) 0x41ff18 FSUB	D1, D28, S17

  (121) 0x41ff1c FMUL	D3, D18, D24

  (121) 0x41ff20 FMUL	D2, D1, D20

  (121) 0x41ff24 FMADD	D4, D23, D25, D3

  (121) 0x41ff28 FMUL	D0, D4, D30

  (121) 0x41ff2c FMINNM	D6, D0, D26

  (121) 0x41ff30 FMUL	D7, D6, D2

  (121) 0x41ff34 B	41f4e0

  (121) 0x41ff38 ORR	X10, XZR, X30

  (121) 0x41ff3c ORR	X7, XZR, X16

  (121) 0x41ff40 ORR	X12, XZR, X8

  (121) 0x41ff44 B	41f470

/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 202 - 246

--------------------------------------------------------------------------------

202:         DO j=x_min,x_max

203:

204:           IF(vol_flux_y(j,k).GT.0.0)THEN

[...]

210:             upwind   =MIN(k+1,y_max+2)

[...]

216:           sigmat=ABS(vol_flux_y(j,k))/pre_vol(j,donor)

217:           sigma3=(1.0_8+sigmat)*(vertexdy(k)/vertexdy(dif))

218:           sigma4=2.0_8-sigmat

219:

220:           sigma=sigmat

221:           sigmav=sigmat

222:

223:           diffuw=density1(j,donor)-density1(j,upwind)

224:           diffdw=density1(j,downwind)-density1(j,donor)

225:           wind=1.0_8

226:           IF(diffdw.LE.0.0) wind=-1.0_8

227:           IF(diffuw*diffdw.GT.0.0)THEN

228:             limiter=(1.0_8-sigmav)*wind*MIN(ABS(diffuw),ABS(diffdw)&

229:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

230:           ELSE

231:             limiter=0.0

232:           ENDIF

233:           mass_flux_y(j,k)=vol_flux_y(j,k)*(density1(j,donor)+limiter)

234:

235:           sigmam=ABS(mass_flux_y(j,k))/(density1(j,donor)*pre_vol(j,donor))

236:           diffuw=energy1(j,donor)-energy1(j,upwind)

237:           diffdw=energy1(j,downwind)-energy1(j,donor)

238:           wind=1.0_8

239:           IF(diffdw.LE.0.0) wind=-1.0_8

240:           IF(diffuw*diffdw.GT.0.0)THEN

241:             limiter=(1.0_8-sigmam)*wind*MIN(ABS(diffuw),ABS(diffdw)&

242:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

243:           ELSE

244:             limiter=0.0

245:           ENDIF

246:           ener_flux(j,k)=mass_flux_y(j,k)*(energy1(j,donor)+limiter)

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	advec_cell_kernel	advec_cell_kernel.f90:270	exec
○	advec_cell_driver	advec_cell_driver.f90:84	exec
○	advection	advection.f90:57	exec
○	hydro	hydro.f90:64	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	P10,
Function	advec_cell_kernel._omp_fn.0
Source	advec_cell_kernel.f90:202-202,advec_cell_kernel.f90:223-223
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.83
CQA cycles if no scalar integer	2.83
CQA cycles if FP arith vectorized	2.83
CQA cycles if fully vectorized	0.50
Front-end cycles	2.63
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	2.75
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	2.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.83
P10 cycles	2.50
P11 cycles	2.67
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	21.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.53
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	21.43
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	22.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	P10,
Function	advec_cell_kernel._omp_fn.0
Source	advec_cell_kernel.f90:202-202,advec_cell_kernel.f90:223-223
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.83
CQA cycles if no scalar integer	2.83
CQA cycles if FP arith vectorized	2.83
CQA cycles if fully vectorized	0.50
Front-end cycles	2.63
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	2.75
P2 cycles	2.75
P3 cycles	2.75
P4 cycles	2.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.83
P10 cycles	2.50
P11 cycles	2.67
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	21.00
Nb uops	21.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.53
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	4.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	21.43
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	22.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_cell_kernel._omp_fn.0
Source file and lines	advec_cell_kernel.f90:202-246
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/advec_cell_kernel.f90:202-204,210,216-246.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/advec_cell_kernel.f90:202,223.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=9
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 9 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 21% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.83 to 0.50 cycles (5.67x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization and with fassociative-math (included in Ofast or ffast-math) to extend vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 40 bytes. The binary loop is storing 4 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	0.50	0.50
cycles	1.00	1.00	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	0.50	0.50

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.63
Overall L1	2.83

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.83 cycles. At this rate:

14% of peak load performance is reached (14.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.41 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41f428

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR W7, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W3, [SP, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W20, W7, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SBFM X30, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SBFM X1, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W3, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 41f548 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x468>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR W12, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X8, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W3, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [SP, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W2, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X30, [SP, #192]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W2, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [SP, #200]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X15, X15, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X14, X14, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W3, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 41f428 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x348>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	advec_cell_kernel._omp_fn.0
Source file and lines	advec_cell_kernel.f90:202-246
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/advec_cell_kernel.f90:202-204,210,216-246.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/advec_cell_kernel.f90:202,223.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=9
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 9 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 21% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.83 to 0.50 cycles (5.67x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization and with fassociative-math (included in Ofast or ffast-math) to extend vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 40 bytes. The binary loop is storing 4 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	0.50	0.50
cycles	1.00	1.00	2.75	2.75	2.75	2.75	0.00	0.00	0.00	0.00	2.83	2.50	2.67	0.50	0.50

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	2.63
Overall L1	2.83

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.83 cycles. At this rate:

14% of peak load performance is reached (14.12 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.41 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41f428

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR W7, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W3, [SP, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W20, W7, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SBFM X30, X7, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SBFM X1, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W3, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 41f548 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x468>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR W12, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X8, XZR, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W3, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X16, [SP, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W2, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X30, [SP, #192]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W2, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [SP, #200]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X13, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X15, X15, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X14, X14, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W3, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 41f428 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x348>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code