OV - exec - Loop 112

	Loop Id: 112	Module: exec	Source: accelerate_kernel.f90:67-76	Coverage: 5.26%

0x41ea40 LD1D	{Z0.D}, P3/Z, [X17, X0,LSL #3]    [18]

0x41ea44 LD1D	{Z1.D}, P3/Z, [X16, X0,LSL #3]    [5]

0x41ea48 LD1D	{Z3.D}, P3/Z, [X21, X0,LSL #3]    [16]

0x41ea4c LD1D	{Z2.D}, P3/Z, [X30, X0,LSL #3]    [3]

0x41ea50 LD1D	{Z17.D}, P3/Z, [X24, X0,LSL #3]    [8]

0x41ea54 LD1D	{Z7.D}, P3/Z, [X20, X0,LSL #3]    [1]

0x41ea58 LD1D	{Z16.D}, P3/Z, [X18, X0,LSL #3]    [19]

0x41ea5c FMUL	Z6.D, Z1.D, Z0.D

0x41ea60 FMAD	Z7.D, P1/M, Z3.D, Z6.D

0x41ea64 FMAD	Z16.D, P1/M, Z2.D, Z7.D

0x41ea68 LD1D	{Z19.D}, P3/Z, [X5, X0,LSL #3]    [17]

0x41ea6c LD1D	{Z20.D}, P3/Z, [X10, X0,LSL #3]    [4]

0x41ea70 LD1D	{Z23.D}, P3/Z, [X3, X0,LSL #3]    [13]

0x41ea74 LD1D	{Z24.D}, P3/Z, [X8, X0,LSL #3]    [24]

0x41ea78 LD1D	{Z29.D}, P3/Z, [X19, X0,LSL #3]    [7]

0x41ea7c LD1D	{Z18.D}, P3/Z, [X23, X0,LSL #3]    [23]

0x41ea80 LD1D	{Z26.D}, P3/Z, [X14, X0,LSL #3]    [9]

0x41ea84 LD1D	{Z27.D}, P3/Z, [X11, X0,LSL #3]    [14]

0x41ea88 FMAD	Z18.D, P1/M, Z17.D, Z16.D

0x41ea8c FSUB	Z22.D, Z19.D, Z20.D

0x41ea90 FSUB	Z28.D, Z24.D, Z26.D

0x41ea94 FMUL	Z25.D, Z22.D, Z23.D

0x41ea98 FMUL	Z21.D, Z18.D, Z5.D

0x41ea9c FMAD	Z27.D, P1/M, Z28.D, Z25.D

0x41eaa0 FDIVR	Z21.D, P1/M, Z21.D, Z4.D

0x41eaa4 FMSB	Z27.D, P1/M, Z21.D, Z29.D

0x41eaa8 ST1D	{Z27.D}, P3, [X2, X0,LSL #3]    [15]

0x41eaac LD1D	{Z30.D}, P3/Z, [X14, X0,LSL #3]    [9]

0x41eab0 LD1D	{Z31.D}, P3/Z, [X10, X0,LSL #3]    [4]

0x41eab4 LD1D	{Z0.D}, P3/Z, [X13, X0,LSL #3]    [22]

0x41eab8 LD1D	{Z3.D}, P3/Z, [X8, X0,LSL #3]    [24]

0x41eabc LD1D	{Z6.D}, P3/Z, [X5, X0,LSL #3]    [17]

0x41eac0 LD1D	{Z2.D}, P3/Z, [X7, X0,LSL #3]    [20]

0x41eac4 LD1D	{Z17.D}, P3/Z, [X22, X0,LSL #3]    [21]

0x41eac8 FSUB	Z1.D, Z30.D, Z31.D

0x41eacc FSUB	Z16.D, Z3.D, Z6.D

0x41ead0 FMUL	Z7.D, Z1.D, Z0.D

0x41ead4 FMAD	Z2.D, P1/M, Z16.D, Z7.D

0x41ead8 FMSB	Z2.D, P1/M, Z21.D, Z17.D

0x41eadc ST1D	{Z2.D}, P3, [X1, X0,LSL #3]    [11]

0x41eae0 LD1D	{Z18.D}, P3/Z, [X2, X0,LSL #3]    [15]

0x41eae4 LD1D	{Z19.D}, P3/Z, [X11, X0,LSL #3]    [14]

0x41eae8 LD1D	{Z20.D}, P3/Z, [X6, X0,LSL #3]    [12]

0x41eaec LD1D	{Z22.D}, P3/Z, [X12, X0,LSL #3]    [2]

0x41eaf0 LD1D	{Z23.D}, P3/Z, [X3, X0,LSL #3]    [13]

0x41eaf4 LD1D	{Z25.D}, P3/Z, [X4, X0,LSL #3]    [6]

0x41eaf8 FSUB	Z24.D, Z20.D, Z22.D

0x41eafc LD1D	{Z26.D}, P3/Z, [X9, X0,LSL #3]    [10]

0x41eb00 FSUB	Z27.D, Z25.D, Z26.D

0x41eb04 FMUL	Z28.D, Z27.D, Z23.D

0x41eb08 FMAD	Z19.D, P1/M, Z24.D, Z28.D

0x41eb0c FMSB	Z19.D, P1/M, Z21.D, Z18.D

0x41eb10 ST1D	{Z19.D}, P3, [X2, X0,LSL #3]    [15]

0x41eb14 LD1D	{Z29.D}, P3/Z, [X12, X0,LSL #3]    [2]

0x41eb18 LD1D	{Z30.D}, P3/Z, [X9, X0,LSL #3]    [10]

0x41eb1c LD1D	{Z31.D}, P3/Z, [X13, X0,LSL #3]    [22]

0x41eb20 LD1D	{Z3.D}, P3/Z, [X6, X0,LSL #3]    [12]

0x41eb24 LD1D	{Z7.D}, P3/Z, [X4, X0,LSL #3]    [6]

0x41eb28 LD1D	{Z2.D}, P3/Z, [X7, X0,LSL #3]    [20]

0x41eb2c LD1D	{Z6.D}, P3/Z, [X1, X0,LSL #3]    [11]

0x41eb30 FSUB	Z0.D, Z29.D, Z30.D

0x41eb34 FSUB	Z16.D, Z3.D, Z7.D

0x41eb38 FMUL	Z1.D, Z0.D, Z31.D

0x41eb3c FMLA	Z1.D, P1/M, Z2.D, Z16.D

0x41eb40 FMSB	Z21.D, P1/M, Z1.D, Z6.D

0x41eb44 ST1D	{Z21.D}, P3, [X1, X0,LSL #3]    [11]

0x41eb48 ADD	X0, X0, X26

0x41eb4c WHILELO	P3.D, X0, X15

0x41eb50 B.NE	41ea40

/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/accelerate_kernel.f90: 67 - 76

--------------------------------------------------------------------------------

67:           *0.25_8)

68:

69:         xvel1(j,k)=xvel0(j,k)-stepbymass_s*(xarea(j  ,k  )*(pressure(j  ,k  )-pressure(j-1,k  ))    &

70:           +xarea(j  ,k-1)*(pressure(j  ,k-1)-pressure(j-1,k-1)))

71:         yvel1(j,k)=yvel0(j,k)-stepbymass_s*(yarea(j  ,k  )*(pressure(j  ,k  )-pressure(j  ,k-1))    &

72:           +yarea(j-1,k  )*(pressure(j-1,k  )-pressure(j-1,k-1)))

73:         xvel1(j,k)=xvel1(j,k)-stepbymass_s*(xarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j-1,k  )) &

74:           +xarea(j  ,k-1)*(viscosity(j  ,k-1)-viscosity(j-1,k-1)))

75:         yvel1(j,k)=yvel1(j,k)-stepbymass_s*(yarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j  ,k-1)) &

76:           +yarea(j-1,k  )*(viscosity(j-1,k  )-viscosity(j-1,k-1)))

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	accelerate_kernel	accelerate_kernel.f90:57	exec
○	accelerate	accelerate.f90:41	exec
○	hydro	hydro.f90:58	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.54
Bottlenecks	P10, P11,
Function	accelerate_kernel._omp_fn.0
Source	accelerate_kernel.f90:67-76
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	20.00
CQA cycles if no scalar integer	20.00
CQA cycles if FP arith vectorized	20.00
CQA cycles if fully vectorized	20.00
Front-end cycles	8.63
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	1.00
P4 cycles	0.25
P5 cycles	13.00
P6 cycles	13.00
P7 cycles	12.50
P8 cycles	12.50
P9 cycles	20.00
P10 cycles	20.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	69.00
Nb uops	69.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	7.40
Nb FLOP add-sub	32.00
Nb FLOP mul	24.00
Nb FLOP fma	44.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	1152.00
Bytes stored	128.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.54
Bottlenecks	P10, P11,
Function	accelerate_kernel._omp_fn.0
Source	accelerate_kernel.f90:67-76
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	20.00
CQA cycles if no scalar integer	20.00
CQA cycles if FP arith vectorized	20.00
CQA cycles if fully vectorized	20.00
Front-end cycles	8.63
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	1.00
P4 cycles	0.25
P5 cycles	13.00
P6 cycles	13.00
P7 cycles	12.50
P8 cycles	12.50
P9 cycles	20.00
P10 cycles	20.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	69.00
Nb uops	69.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	7.40
Nb FLOP add-sub	32.00
Nb FLOP mul	24.00
Nb FLOP fma	44.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	1152.00
Bytes stored	128.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	accelerate_kernel._omp_fn.0
Source file and lines	accelerate_kernel.f90:67-76
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/accelerate_kernel.f90:67-76.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

FMA

Detected 44 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 148 FP arithmetical operations:

76: addition or subtraction (44 inside FMA instructions)
68: multiply (44 inside FMA instructions)
4: divide

The binary loop is loading 1152 bytes. The binary loop is storing 128 bytes.

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

General properties

nb instructions	69
loop length	276
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	13.00	13.00	2.00	2.00	20.00	20.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	13.00	13.00	12.50	12.50	20.00	20.00	0.00	0.00	0.00

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.63
Data deps.	1.00
Overall L1	20.00

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.00 cycles. At this rate:

60% of peak load performance is reached (57.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41ea40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LD1D {Z0.D}, P3/Z, [X17, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z1.D}, P3/Z, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z3.D}, P3/Z, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z2.D}, P3/Z, [X30, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z17.D}, P3/Z, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z7.D}, P3/Z, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z16.D}, P3/Z, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z6.D, Z1.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z7.D, P1/M, Z3.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z16.D, P1/M, Z2.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1D {Z19.D}, P3/Z, [X5, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P3/Z, [X10, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P3/Z, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z24.D}, P3/Z, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z29.D}, P3/Z, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z18.D}, P3/Z, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z26.D}, P3/Z, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z27.D}, P3/Z, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z18.D, P1/M, Z17.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FSUB Z22.D, Z19.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z28.D, Z24.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z25.D, Z22.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z21.D, Z18.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z27.D, P1/M, Z28.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FDIVR Z21.D, P1/M, Z21.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMSB Z27.D, P1/M, Z21.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z27.D}, P3, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z30.D}, P3/Z, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P3/Z, [X10, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z0.D}, P3/Z, [X13, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z3.D}, P3/Z, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z6.D}, P3/Z, [X5, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z2.D}, P3/Z, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z17.D}, P3/Z, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z1.D, Z30.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z16.D, Z3.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z7.D, Z1.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z2.D, P1/M, Z16.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMSB Z2.D, P1/M, Z21.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z2.D}, P3, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z18.D}, P3/Z, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z19.D}, P3/Z, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P3/Z, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z22.D}, P3/Z, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P3/Z, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z25.D}, P3/Z, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z24.D, Z20.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z26.D}, P3/Z, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z27.D, Z25.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z28.D, Z27.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z19.D, P1/M, Z24.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMSB Z19.D, P1/M, Z21.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z19.D}, P3, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z29.D}, P3/Z, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z30.D}, P3/Z, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P3/Z, [X13, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z3.D}, P3/Z, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z7.D}, P3/Z, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z2.D}, P3/Z, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z6.D}, P3/Z, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z0.D, Z29.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z16.D, Z3.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z1.D, Z0.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z1.D, P1/M, Z2.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMSB Z21.D, P1/M, Z1.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z21.D}, P3, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X0, X0, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
WHILELO P3.D, X0, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2
B.NE 41ea40 <__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0+0x2c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	accelerate_kernel._omp_fn.0
Source file and lines	accelerate_kernel.f90:67-76
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

FMA

Detected 44 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 148 FP arithmetical operations:

76: addition or subtraction (44 inside FMA instructions)
68: multiply (44 inside FMA instructions)
4: divide

The binary loop is loading 1152 bytes. The binary loop is storing 128 bytes.

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

General properties

nb instructions	69
loop length	276
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	13.00	13.00	2.00	2.00	20.00	20.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	13.00	13.00	12.50	12.50	20.00	20.00	0.00	0.00	0.00

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	8.63
Data deps.	1.00
Overall L1	20.00

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 20.00 cycles. At this rate:

60% of peak load performance is reached (57.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41ea40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LD1D {Z0.D}, P3/Z, [X17, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z1.D}, P3/Z, [X16, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z3.D}, P3/Z, [X21, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z2.D}, P3/Z, [X30, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z17.D}, P3/Z, [X24, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z7.D}, P3/Z, [X20, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z16.D}, P3/Z, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z6.D, Z1.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z7.D, P1/M, Z3.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMAD Z16.D, P1/M, Z2.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1D {Z19.D}, P3/Z, [X5, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P3/Z, [X10, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P3/Z, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z24.D}, P3/Z, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z29.D}, P3/Z, [X19, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z18.D}, P3/Z, [X23, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z26.D}, P3/Z, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z27.D}, P3/Z, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMAD Z18.D, P1/M, Z17.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FSUB Z22.D, Z19.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z28.D, Z24.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z25.D, Z22.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z21.D, Z18.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z27.D, P1/M, Z28.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FDIVR Z21.D, P1/M, Z21.D, Z4.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMSB Z27.D, P1/M, Z21.D, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z27.D}, P3, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z30.D}, P3/Z, [X14, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P3/Z, [X10, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z0.D}, P3/Z, [X13, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z3.D}, P3/Z, [X8, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z6.D}, P3/Z, [X5, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z2.D}, P3/Z, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z17.D}, P3/Z, [X22, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z1.D, Z30.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z16.D, Z3.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z7.D, Z1.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z2.D, P1/M, Z16.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMSB Z2.D, P1/M, Z21.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z2.D}, P3, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z18.D}, P3/Z, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z19.D}, P3/Z, [X11, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P3/Z, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z22.D}, P3/Z, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P3/Z, [X3, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z25.D}, P3/Z, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z24.D, Z20.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z26.D}, P3/Z, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z27.D, Z25.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z28.D, Z27.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z19.D, P1/M, Z24.D, Z28.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMSB Z19.D, P1/M, Z21.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z19.D}, P3, [X2, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z29.D}, P3/Z, [X12, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z30.D}, P3/Z, [X9, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z31.D}, P3/Z, [X13, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z3.D}, P3/Z, [X6, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z7.D}, P3/Z, [X4, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z2.D}, P3/Z, [X7, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z6.D}, P3/Z, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z0.D, Z29.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z16.D, Z3.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z1.D, Z0.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMLA Z1.D, P1/M, Z2.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMSB Z21.D, P1/M, Z1.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z21.D}, P3, [X1, X0,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X0, X0, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
WHILELO P3.D, X0, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2
B.NE 41ea40 <__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0+0x2c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code