| Loop Id: 102 | Module: exec | Source: PdV_kernel.f90:78-99 [...] | Coverage: 0.02% |
|---|
| Loop Id: 102 | Module: exec | Source: PdV_kernel.f90:78-99 [...] | Coverage: 0.02% |
|---|
0x41d8c0 LDP W19, W20, [SP, #100] |
0x41d8c4 ADD W11, W11, #1 |
0x41d8c8 CMP W20, W19 |
0x41d8cc B.GT 41d9fc |
0x41d8d0 LDR X17, [SP, #192] |
0x41d8d4 ADD X21, X10, #8 |
0x41d8d8 ADD X20, X6, #8 |
0x41d8dc ADD X19, X8, #8 |
0x41d8e0 ADD X18, X5, #8 |
0x41d8e4 ORR P5.B, P4/Z, P4.B, P4.B |
0x41d8e8 ADD X16, X7, #8 |
0x41d8ec MOVZ X0, #0 |
0x41d8f0 ADD X17, X17, X9 |
0x41d8f4 HINT #0 |
0x41d8f8 HINT #0 |
0x41d8fc HINT #0 |
(103) 0x41d900 LD1D {Z20.D}, P5/Z, [X20, X0,LSL #3] |
(103) 0x41d904 LD1D {Z21.D}, P5/Z, [X19, X0,LSL #3] |
(103) 0x41d908 LD1D {Z26.D}, P5/Z, [X6, X0,LSL #3] |
(103) 0x41d90c LD1D {Z22.D}, P5/Z, [X21, X0,LSL #3] |
(103) 0x41d910 FADD Z23.D, Z21.D, Z20.D |
(103) 0x41d914 FADD Z25.D, Z23.D, Z20.D |
(103) 0x41d918 FADD Z27.D, Z25.D, Z21.D |
(103) 0x41d91c LD1D {Z28.D}, P5/Z, [X8, X0,LSL #3] |
(103) 0x41d920 LD1D {Z18.D}, P5/Z, [X7, X0,LSL #3] |
(103) 0x41d924 LD1D {Z7.D}, P5/Z, [X16, X0,LSL #3] |
(103) 0x41d928 LD1D {Z25.D}, P5/Z, [X5, X0,LSL #3] |
(103) 0x41d92c LD1RD {Z24.D}, P3/Z, [X23] |
(103) 0x41d930 LD1D {Z2.D}, P5/Z, [X10, X0,LSL #3] |
(103) 0x41d934 LD1D {Z23.D}, P5/Z, [X17, X0,LSL #3] |
(103) 0x41d938 FMUL Z29.D, Z27.D, Z22.D |
(103) 0x41d93c FADD Z30.D, Z28.D, Z26.D |
(103) 0x41d940 LD1D {Z27.D}, P5/Z, [X18, X0,LSL #3] |
(103) 0x41d944 FADD Z1.D, Z30.D, Z26.D |
(103) 0x41d948 FADD Z17.D, Z7.D, Z18.D |
(103) 0x41d94c FADD Z0.D, Z1.D, Z28.D |
(103) 0x41d950 FADD Z21.D, Z17.D, Z18.D |
(103) 0x41d954 FMUL Z16.D, Z0.D, Z2.D |
(103) 0x41d958 FADD Z22.D, Z21.D, Z7.D |
(103) 0x41d95c FMUL Z31.D, Z29.D, Z3.D |
(103) 0x41d960 FMUL Z26.D, Z22.D, Z23.D |
(103) 0x41d964 FMUL Z5.D, Z31.D, Z24.D |
(103) 0x41d968 FMUL Z6.D, Z16.D, Z3.D |
(103) 0x41d96c FMUL Z5.D, P3/M, Z5.D, #0 |
(103) 0x41d970 FMUL Z20.D, Z6.D, Z24.D |
(103) 0x41d974 FMSB Z20.D, P3/M, Z4.D, Z5.D |
(103) 0x41d978 LD1D {Z17.D}, P5/Z, [X15, X0,LSL #3] |
(103) 0x41d97c LD1D {Z16.D}, P5/Z, [X2, X0,LSL #3] |
(103) 0x41d980 LD1D {Z5.D}, P5/Z, [X9, X0,LSL #3] |
(103) 0x41d984 LD1D {Z18.D}, P5/Z, [X14, X0,LSL #3] |
(103) 0x41d988 LD1D {Z7.D}, P5/Z, [X13, X0,LSL #3] |
(103) 0x41d98c FADD Z29.D, Z27.D, Z25.D |
(103) 0x41d990 FMUL Z28.D, Z26.D, Z3.D |
(103) 0x41d994 FADD Z31.D, Z29.D, Z25.D |
(103) 0x41d998 FMUL Z30.D, Z28.D, Z24.D |
(103) 0x41d99c LD1D {Z25.D}, P5/Z, [X12, X0,LSL #3] |
(103) 0x41d9a0 FMAD Z30.D, P3/M, Z4.D, Z20.D |
(103) 0x41d9a4 FADD Z1.D, Z31.D, Z27.D |
(103) 0x41d9a8 FDIV Z18.D, P3/M, Z18.D, Z16.D |
(103) 0x41d9ac FMUL Z0.D, Z1.D, Z5.D |
(103) 0x41d9b0 MOVPRFX Z6, Z7 |
(103) 0x41d9b4 FDIV Z6.D, P3/M, Z6.D, Z16.D |
(103) 0x41d9b8 FMUL Z2.D, Z0.D, Z3.D |
(103) 0x41d9bc FADD Z20.D, Z6.D, Z18.D |
(103) 0x41d9c0 FMUL Z24.D, Z2.D, Z24.D |
(103) 0x41d9c4 FMSB Z24.D, P3/M, Z4.D, Z30.D |
(103) 0x41d9c8 FADD Z21.D, Z17.D, Z24.D |
(103) 0x41d9cc FMUL Z22.D, Z20.D, Z24.D |
(103) 0x41d9d0 MOVPRFX Z23, Z17 |
(103) 0x41d9d4 FDIV Z23.D, P3/M, Z23.D, Z21.D |
(103) 0x41d9d8 FDIVR Z17.D, P3/M, Z17.D, Z19.D |
(103) 0x41d9dc FMSB Z22.D, P3/M, Z17.D, Z25.D |
(103) 0x41d9e0 ST1D {Z22.D}, P5, [X3, X0,LSL #3] |
(103) 0x41d9e4 LD1D {Z26.D}, P5/Z, [X2, X0,LSL #3] |
(103) 0x41d9e8 FMUL Z27.D, Z26.D, Z23.D |
(103) 0x41d9ec ST1D {Z27.D}, P5, [X1, X0,LSL #3] |
(103) 0x41d9f0 ADD X0, X0, X25 |
(103) 0x41d9f4 WHILELO P5.D, X0, X4 |
(103) 0x41d9f8 B.NE 41d900 |
0x41d9fc LDR X21, [SP, #136] |
0x41da00 CMP W27, W22 |
0x41da04 ADD X6, X6, X30 |
0x41da08 ADD X8, X8, X30 |
0x41da0c ADD X5, X5, X28 |
0x41da10 CSEL W24, W24, W27, #1 |
0x41da14 LDR X20, [SP, #168] |
0x41da18 ADD X7, X7, X28 |
0x41da1c CSINC W26, W26, WZR, #1 |
0x41da20 LDR X19, [SP, #176] |
0x41da24 ADD X10, X10, X21 |
0x41da28 LDR X16, [SP, #112] |
0x41da2c ADD X9, X9, X20 |
0x41da30 LDR X17, [SP, #120] |
0x41da34 ADD X15, X15, X19 |
0x41da38 LDR W19, [SP, #160] |
0x41da3c ADD X2, X2, X16 |
0x41da40 LDR X0, [SP, #128] |
0x41da44 ADD X13, X13, X17 |
0x41da48 LDR X21, [SP, #144] |
0x41da4c LDR X20, [SP, #152] |
0x41da50 ADD X12, X12, X0 |
0x41da54 LDR X18, [SP, #184] |
0x41da58 ADD X3, X3, X21 |
0x41da5c ADD X1, X1, X20 |
0x41da60 ADD X14, X14, X18 |
0x41da64 CMP W19, W11 |
0x41da68 B.GT 41d8c0 |
/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/PdV_kernel.f90: 78 - 99 |
-------------------------------------------------------------------------------- |
78: +xvel0(j ,k )+xvel0(j ,k+1)))*0.25_8*dt*0.5 |
79: right_flux= (xarea(j+1,k )*(xvel0(j+1,k )+xvel0(j+1,k+1) & |
80: +xvel0(j+1,k )+xvel0(j+1,k+1)))*0.25_8*dt*0.5 |
81: bottom_flux=(yarea(j ,k )*(yvel0(j ,k )+yvel0(j+1,k ) & |
82: +yvel0(j ,k )+yvel0(j+1,k )))*0.25_8*dt*0.5 |
83: top_flux= (yarea(j ,k+1)*(yvel0(j ,k+1)+yvel0(j+1,k+1) & |
84: +yvel0(j ,k+1)+yvel0(j+1,k+1)))*0.25_8*dt*0.5 |
85: total_flux=right_flux-left_flux+top_flux-bottom_flux |
86: |
87: volume_change_s=volume(j,k)/(volume(j,k)+total_flux) |
[...] |
93: recip_volume=1.0/volume(j,k) |
94: |
95: energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume |
96: |
97: energy1(j,k)=energy0(j,k)-energy_change |
98: |
99: density1(j,k)=density0(j,k)*volume_change_s |
| Coverage (%) | Name | Source Location | Module |
|---|---|---|---|
| ►100.00+ | GOMP_parallel | libgomp.so.1.0.0 | |
| ○ | pdv_kernel | PdV_kernel.f90:145 | exec |
| ○ | pdv | PdV.f90:58 | exec |
| ○ | hydro | hydro.f90:56 | exec |
| ○ | main | clover_leaf.f90:41 | exec |
| ○ | __libc_start_main | libc-2.31.so | |
| ○ | _start | clover_leaf.f90:41 | exec |
| Path / |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 2.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 4.78 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.26 |
| Bottlenecks | |
| Function | pdv_kernel._omp_fn.0 |
| Source | PdV_kernel.f90:78-78,PdV_kernel.f90:99-99 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 5.75 |
| CQA cycles if no scalar integer | 2.88 |
| CQA cycles if FP arith vectorized | 5.75 |
| CQA cycles if fully vectorized | 1.20 |
| Front-end cycles | 4.56 |
| DIV/SQRT cycles | 1.00 |
| P0 cycles | 1.00 |
| P1 cycles | 5.75 |
| P2 cycles | 5.75 |
| P3 cycles | 5.75 |
| P4 cycles | 5.75 |
| P5 cycles | 0.00 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| P8 cycles | 0.00 |
| P9 cycles | 3.83 |
| P10 cycles | 3.83 |
| P11 cycles | 3.83 |
| P12 cycles | 0.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 38.00 |
| Nb uops | 36.50 |
| Nb loads | NA |
| Nb stores | 0.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 15.66 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 88.00 |
| Bytes stored | 0.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 2.27 |
| Vectorization ratio load | NA |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 12.50 |
| Vector-efficiency ratio all | 23.31 |
| Vector-efficiency ratio load | NA |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 25.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 14.06 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 6.75 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 4.80 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.32 |
| Bottlenecks | P2, P3, P4, P5, |
| Function | pdv_kernel._omp_fn.0 |
| Source | PdV_kernel.f90:78-78,PdV_kernel.f90:99-99 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 6.75 |
| CQA cycles if no scalar integer | 1.00 |
| CQA cycles if FP arith vectorized | 6.75 |
| CQA cycles if fully vectorized | 1.41 |
| Front-end cycles | 5.13 |
| DIV/SQRT cycles | 1.00 |
| P0 cycles | 1.00 |
| P1 cycles | 6.75 |
| P2 cycles | 6.75 |
| P3 cycles | 6.75 |
| P4 cycles | 6.75 |
| P5 cycles | 0.00 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| P8 cycles | 0.00 |
| P9 cycles | 4.00 |
| P10 cycles | 4.00 |
| P11 cycles | 4.00 |
| P12 cycles | 0.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 44.00 |
| Nb uops | 41.00 |
| Nb loads | NA |
| Nb stores | 0.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 13.63 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 92.00 |
| Bytes stored | 0.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 4.55 |
| Vectorization ratio load | NA |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 25.00 |
| Vector-efficiency ratio all | 23.30 |
| Vector-efficiency ratio load | NA |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 25.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 15.63 |
| Metric | Value |
|---|---|
| CQA speedup if no scalar integer | 1.00 |
| CQA speedup if FP arith vectorized | 1.00 |
| CQA speedup if fully vectorized | 4.75 |
| CQA speedup if no inter-iteration dependency | NA |
| CQA speedup if next bottleneck killed | 1.19 |
| Bottlenecks | P2, P3, P4, P5, |
| Function | pdv_kernel._omp_fn.0 |
| Source | PdV_kernel.f90:78-78,PdV_kernel.f90:99-99 |
| Source loop unroll info | NA |
| Source loop unroll confidence level | NA |
| Unroll/vectorization loop type | NA |
| Unroll factor | NA |
| CQA cycles | 4.75 |
| CQA cycles if no scalar integer | 4.75 |
| CQA cycles if FP arith vectorized | 4.75 |
| CQA cycles if fully vectorized | 1.00 |
| Front-end cycles | 4.00 |
| DIV/SQRT cycles | 1.00 |
| P0 cycles | 1.00 |
| P1 cycles | 4.75 |
| P2 cycles | 4.75 |
| P3 cycles | 4.75 |
| P4 cycles | 4.75 |
| P5 cycles | 0.00 |
| P6 cycles | 0.00 |
| P7 cycles | 0.00 |
| P8 cycles | 0.00 |
| P9 cycles | 3.67 |
| P10 cycles | 3.67 |
| P11 cycles | 3.67 |
| P12 cycles | 0.00 |
| P13 cycles | 0.00 |
| P14 cycles | 0.00 |
| Inter-iter dependencies cycles | 1 |
| FE+BE cycles (UFS) | NA |
| Stall cycles (UFS) | NA |
| Nb insns | 32.00 |
| Nb uops | 32.00 |
| Nb loads | NA |
| Nb stores | 0.00 |
| Nb stack references | 0.00 |
| FLOP/cycle | 0.00 |
| Nb FLOP add-sub | 0.00 |
| Nb FLOP mul | 0.00 |
| Nb FLOP fma | 0.00 |
| Nb FLOP div | 0.00 |
| Nb FLOP rcp | 0.00 |
| Nb FLOP sqrt | 0.00 |
| Nb FLOP rsqrt | 0.00 |
| Bytes/cycle | 17.68 |
| Bytes prefetched | 0.00 |
| Bytes loaded | 84.00 |
| Bytes stored | 0.00 |
| Stride 0 | NA |
| Stride 1 | NA |
| Stride n | NA |
| Stride unknown | NA |
| Stride indirect | NA |
| Vectorization ratio all | 0.00 |
| Vectorization ratio load | NA |
| Vectorization ratio store | NA |
| Vectorization ratio mul | NA |
| Vectorization ratio add_sub | 0.00 |
| Vectorization ratio fma | NA |
| Vectorization ratio div_sqrt | NA |
| Vectorization ratio other | 0.00 |
| Vector-efficiency ratio all | 23.33 |
| Vector-efficiency ratio load | NA |
| Vector-efficiency ratio store | NA |
| Vector-efficiency ratio mul | NA |
| Vector-efficiency ratio add_sub | 25.00 |
| Vector-efficiency ratio fma | NA |
| Vector-efficiency ratio div_sqrt | NA |
| Vector-efficiency ratio other | 12.50 |
| Path / |
| Function | pdv_kernel._omp_fn.0 |
| Source file and lines | PdV_kernel.f90:78-99 |
| Module | exec |
| nb instructions | 38 |
| loop length | 152 |
| nb stack references | 0 |
| front end | 4.56 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.00 | 1.00 | 5.75 | 5.75 | 5.75 | 5.75 | 0.00 | 0.00 | 0.00 | 0.00 | 3.83 | 3.83 | 3.83 | 0.00 | 0.00 |
| cycles | 1.00 | 1.00 | 5.75 | 5.75 | 5.75 | 5.75 | 0.00 | 0.00 | 0.00 | 0.00 | 3.83 | 3.83 | 3.83 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 4.56 |
| Data deps. | 1.00 |
| Overall L1 | 5.75 |
| all | 2% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 12% |
| Function | pdv_kernel._omp_fn.0 |
| Source file and lines | PdV_kernel.f90:78-99 |
| Module | exec |
| nb instructions | 44 |
| loop length | 176 |
| nb stack references | 0 |
| front end | 5.13 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.00 | 1.00 | 6.75 | 6.75 | 6.75 | 6.75 | 0.00 | 0.00 | 0.00 | 0.00 | 4.00 | 4.00 | 4.00 | 0.00 | 0.00 |
| cycles | 1.00 | 1.00 | 6.75 | 6.75 | 6.75 | 6.75 | 0.00 | 0.00 | 0.00 | 0.00 | 4.00 | 4.00 | 4.00 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 5.13 |
| Data deps. | 1.00 |
| Overall L1 | 6.75 |
| all | 4% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 25% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LDP W19, W20, [SP, #100] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD W11, W11, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CMP W20, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41d9fc <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x39c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X17, [SP, #192] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X21, X10, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X20, X6, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X19, X8, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X18, X5, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ORR P5.B, P4/Z, P4.B, P4.B | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 |
| ADD X16, X7, #8 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| MOVZ X0, #0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X17, X17, X9 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| HINT #0 | ||||||||||||||||||
| LDR X21, [SP, #136] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W27, W22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| ADD X6, X6, X30 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X8, X8, X30 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, X5, X28 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CSEL W24, W24, W27, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X20, [SP, #168] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X7, X7, X28 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CSINC W26, W26, WZR, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X19, [SP, #176] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X10, X10, X21 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X16, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X9, X9, X20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X17, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X15, X15, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W19, [SP, #160] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X2, X2, X16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X0, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X13, X13, X17 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X21, [SP, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X20, [SP, #152] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X12, X12, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X18, [SP, #184] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X3, X3, X21 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X1, X1, X20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X14, X14, X18 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CMP W19, W11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41d8c0 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x260> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| Function | pdv_kernel._omp_fn.0 |
| Source file and lines | PdV_kernel.f90:78-99 |
| Module | exec |
| nb instructions | 32 |
| loop length | 128 |
| nb stack references | 0 |
| front end | 4.00 cycles |
| P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| uops | 1.00 | 1.00 | 4.75 | 4.75 | 4.75 | 4.75 | 0.00 | 0.00 | 0.00 | 0.00 | 3.67 | 3.67 | 3.67 | 0.00 | 0.00 |
| cycles | 1.00 | 1.00 | 4.75 | 4.75 | 4.75 | 4.75 | 0.00 | 0.00 | 0.00 | 0.00 | 3.67 | 3.67 | 3.67 | 0.00 | 0.00 |
| Cycles executing div or sqrt instructions | NA |
| Longest recurrence chain latency (RecMII) | 1.00 |
| Front-end | 4.00 |
| Data deps. | 1.00 |
| Overall L1 | 4.75 |
| all | 0% |
| load | NA (no load vectorizable/vectorized instructions) |
| store | NA (no store vectorizable/vectorized instructions) |
| mul | NA (no mul vectorizable/vectorized instructions) |
| add-sub | 0% |
| fma | NA (no fma vectorizable/vectorized instructions) |
| div/sqrt | NA (no div/sqrt vectorizable/vectorized instructions) |
| other | 0% |
| Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | P12 | P13 | P14 | Latency | Recip. throughput |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| LDP W19, W20, [SP, #100] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD W11, W11, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CMP W20, W19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41d9fc <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x39c> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |
| LDR X21, [SP, #136] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| CMP W27, W22 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| ADD X6, X6, X30 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X8, X8, X30 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X5, X5, X28 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CSEL W24, W24, W27, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X20, [SP, #168] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X7, X7, X28 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CSINC W26, W26, WZR, #1 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X19, [SP, #176] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X10, X10, X21 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X16, [SP, #112] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X9, X9, X20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X17, [SP, #120] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X15, X15, X19 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR W19, [SP, #160] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X2, X2, X16 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X0, [SP, #128] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X13, X13, X17 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X21, [SP, #144] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| LDR X20, [SP, #152] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X12, X12, X0 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| LDR X18, [SP, #184] | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 0.33 | 0.33 | 0 | 0 | 4 | 0.33 |
| ADD X3, X3, X21 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X1, X1, X20 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| ADD X14, X14, X18 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.25 |
| CMP W19, W11 | 1 | 0 | 0 | 0.25 | 0.25 | 0.25 | 0.25 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.33 |
| B.GT 41d8c0 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x260> | 1 | 0.50 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0.50 |