OV - exec - Loop 100

	Loop Id: 100	Module: exec	Source: PdV_kernel.f90:114-135 [...]	Coverage: 0.02%

0x41dca4 LDR	W20, [SP, #100]

0x41dca8 LDR	W24, [SP, #128]

0x41dcac LDR	W25, [SP, #120]

0x41dcb0 ADD	W26, W20, #1

0x41dcb4 STR	W26, [SP, #100]

0x41dcb8 CMP	W25, W24

0x41dcbc B.GT	41ddf0

0x41dcc0 ADD	X27, X14, #8

0x41dcc4 ADD	X26, X13, #8

0x41dcc8 ORR	P1.B, P2/Z, P2.B, P2.B

0x41dccc ADD	X25, X7, #8

0x41dcd0 ADD	X24, X12, #8

0x41dcd4 ADD	X23, X6, #8

0x41dcd8 ADD	X22, X11, #8

0x41dcdc ADD	X21, X9, #8

0x41dce0 ADD	X20, X10, #8

0x41dce4 ADD	X19, X8, #8

0x41dce8 MOVZ	X1, #0

  (101) 0x41dcec LD1D	{Z2.D}, P1/Z, [X26, X1,LSL #3]

  (101) 0x41dcf0 LD1D	{Z1.D}, P1/Z, [X25, X1,LSL #3]

  (101) 0x41dcf4 LD1D	{Z0.D}, P1/Z, [X24, X1,LSL #3]

  (101) 0x41dcf8 LD1D	{Z6.D}, P1/Z, [X23, X1,LSL #3]

  (101) 0x41dcfc LD1D	{Z16.D}, P1/Z, [X27, X1,LSL #3]

  (101) 0x41dd00 FADD	Z5.D, Z1.D, Z2.D

  (101) 0x41dd04 FADD	Z7.D, Z5.D, Z0.D

  (101) 0x41dd08 FADD	Z17.D, Z7.D, Z6.D

  (101) 0x41dd0c LD1RD	{Z18.D}, P0/Z, [X28]

  (101) 0x41dd10 LD1D	{Z20.D}, P1/Z, [X13, X1,LSL #3]

  (101) 0x41dd14 LD1D	{Z22.D}, P1/Z, [X7, X1,LSL #3]

  (101) 0x41dd18 LD1D	{Z25.D}, P1/Z, [X12, X1,LSL #3]

  (101) 0x41dd1c LD1D	{Z26.D}, P1/Z, [X6, X1,LSL #3]

  (101) 0x41dd20 LD1D	{Z28.D}, P1/Z, [X14, X1,LSL #3]

  (101) 0x41dd24 LD1D	{Z30.D}, P1/Z, [X10, X1,LSL #3]

  (101) 0x41dd28 LD1D	{Z1.D}, P1/Z, [X20, X1,LSL #3]

  (101) 0x41dd2c LD1D	{Z5.D}, P1/Z, [X8, X1,LSL #3]

  (101) 0x41dd30 LD1D	{Z7.D}, P1/Z, [X19, X1,LSL #3]

  (101) 0x41dd34 LD1D	{Z6.D}, P1/Z, [X15, X1,LSL #3]

  (101) 0x41dd38 FMUL	Z19.D, Z17.D, Z16.D

  (101) 0x41dd3c FADD	Z24.D, Z22.D, Z20.D

  (101) 0x41dd40 FADD	Z0.D, Z30.D, Z1.D

  (101) 0x41dd44 FADD	Z27.D, Z25.D, Z24.D

  (101) 0x41dd48 FADD	Z16.D, Z0.D, Z5.D

  (101) 0x41dd4c FADD	Z29.D, Z27.D, Z26.D

  (101) 0x41dd50 FADD	Z17.D, Z16.D, Z7.D

  (101) 0x41dd54 FMUL	Z31.D, Z29.D, Z28.D

  (101) 0x41dd58 FMUL	Z21.D, Z19.D, Z3.D

  (101) 0x41dd5c FMUL	Z2.D, Z31.D, Z3.D

  (101) 0x41dd60 FMUL	Z23.D, Z21.D, Z18.D

  (101) 0x41dd64 FMSB	Z2.D, P0/M, Z18.D, Z23.D

  (101) 0x41dd68 LD1D	{Z0.D}, P1/Z, [X30, X1,LSL #3]

  (101) 0x41dd6c LD1D	{Z31.D}, P1/Z, [X0, X1,LSL #3]

  (101) 0x41dd70 LD1D	{Z19.D}, P1/Z, [X11, X1,LSL #3]

  (101) 0x41dd74 LD1D	{Z21.D}, P1/Z, [X22, X1,LSL #3]

  (101) 0x41dd78 LD1D	{Z24.D}, P1/Z, [X9, X1,LSL #3]

  (101) 0x41dd7c LD1D	{Z25.D}, P1/Z, [X21, X1,LSL #3]

  (101) 0x41dd80 LD1D	{Z27.D}, P1/Z, [X5, X1,LSL #3]

  (101) 0x41dd84 LD1D	{Z29.D}, P1/Z, [X17, X1,LSL #3]

  (101) 0x41dd88 LD1D	{Z5.D}, P1/Z, [X16, X1,LSL #3]

  (101) 0x41dd8c LD1D	{Z16.D}, P1/Z, [X18, X1,LSL #3]

  (101) 0x41dd90 FMUL	Z20.D, Z17.D, Z6.D

  (101) 0x41dd94 FADD	Z23.D, Z19.D, Z21.D

  (101) 0x41dd98 FMUL	Z22.D, Z20.D, Z3.D

  (101) 0x41dd9c FADD	Z26.D, Z23.D, Z24.D

  (101) 0x41dda0 FMAD	Z22.D, P0/M, Z18.D, Z2.D

  (101) 0x41dda4 FADD	Z28.D, Z26.D, Z25.D

  (101) 0x41dda8 FDIV	Z29.D, P0/M, Z29.D, Z31.D

  (101) 0x41ddac FMUL	Z30.D, Z28.D, Z27.D

  (101) 0x41ddb0 FDIV	Z5.D, P0/M, Z5.D, Z31.D

  (101) 0x41ddb4 FMUL	Z1.D, Z30.D, Z3.D

  (101) 0x41ddb8 FADD	Z7.D, Z5.D, Z29.D

  (101) 0x41ddbc FMSB	Z18.D, P0/M, Z1.D, Z22.D

  (101) 0x41ddc0 FADD	Z2.D, Z18.D, Z0.D

  (101) 0x41ddc4 FMUL	Z18.D, Z7.D, Z18.D

  (101) 0x41ddc8 FDIVR	Z2.D, P0/M, Z2.D, Z0.D

  (101) 0x41ddcc FDIVR	Z0.D, P0/M, Z0.D, Z4.D

  (101) 0x41ddd0 FMSB	Z0.D, P0/M, Z18.D, Z16.D

  (101) 0x41ddd4 ST1D	{Z0.D}, P1, [X3, X1,LSL #3]

  (101) 0x41ddd8 LD1D	{Z6.D}, P1/Z, [X0, X1,LSL #3]

  (101) 0x41dddc FMUL	Z17.D, Z2.D, Z6.D

  (101) 0x41dde0 ST1D	{Z17.D}, P1, [X2, X1,LSL #3]

  (101) 0x41dde4 INCD	X1, ALL

  (101) 0x41dde8 WHILELO	P1.D, X1, X4

  (101) 0x41ddec B.NE	41dcec

0x41ddf0 LDR	W27, [SP, #136]

0x41ddf4 LDR	W26, [SP, #152]

0x41ddf8 LDR	W23, [SP, #112]

0x41ddfc LDR	X25, [SP, #160]

0x41de00 CMP	W27, W26

0x41de04 CSEL	W22, W23, W27, #1

0x41de08 STR	W22, [SP, #112]

0x41de0c LDR	X27, [SP, #168]

0x41de10 LDR	X26, [SP, #176]

0x41de14 ADD	X14, X14, X25

0x41de18 LDR	X21, [SP, #192]

0x41de1c ADD	X13, X13, X27

0x41de20 ADD	X7, X7, X27

0x41de24 LDR	X24, [SP, #200]

0x41de28 ADD	X12, X12, X26

0x41de2c ADD	X6, X6, X26

0x41de30 LDR	W19, [SP, #104]

0x41de34 CSINC	W1, W19, WZR, #1

0x41de38 ADD	X11, X11, X21

0x41de3c ADD	X10, X10, X21

0x41de40 STR	W1, [SP, #104]

0x41de44 LDR	W20, [SP, #100]

0x41de48 ADD	X9, X9, X24

0x41de4c ADD	X8, X8, X24

0x41de50 LDR	W26, [SP, #144]

0x41de54 LDR	X25, [SP, #184]

0x41de58 LDR	X24, [SP, #208]

0x41de5c LDR	X23, [SP, #216]

0x41de60 ADD	X5, X5, X25

0x41de64 ADD	X15, X15, X25

0x41de68 LDR	X22, [SP, #224]

0x41de6c ADD	X30, X30, X24

0x41de70 LDR	X21, [SP, #232]

0x41de74 ADD	X17, X17, X23

0x41de78 LDR	X19, [SP, #240]

0x41de7c ADD	X0, X0, X22

0x41de80 LDR	X1, [SP, #248]

0x41de84 ADD	X16, X16, X21

0x41de88 LDR	X27, [SP, #256]

0x41de8c ADD	X18, X18, X19

0x41de90 ADD	X3, X3, X1

0x41de94 ADD	X2, X2, X27

0x41de98 CMP	W26, W20

0x41de9c B.GT	41dca4

/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/PdV_kernel.f90: 114 - 135

--------------------------------------------------------------------------------

114:             +xvel1(j  ,k  )+xvel1(j  ,k+1)))*0.25_8*dt

115:           right_flux= (xarea(j+1,k  )*(xvel0(j+1,k  )+xvel0(j+1,k+1)                     &

116:             +xvel1(j+1,k  )+xvel1(j+1,k+1)))*0.25_8*dt

117:           bottom_flux=(yarea(j  ,k  )*(yvel0(j  ,k  )+yvel0(j+1,k  )                     &

118:             +yvel1(j  ,k  )+yvel1(j+1,k  )))*0.25_8*dt

119:           top_flux=   (yarea(j  ,k+1)*(yvel0(j  ,k+1)+yvel0(j+1,k+1)                     &

120:             +yvel1(j  ,k+1)+yvel1(j+1,k+1)))*0.25_8*dt

121:           total_flux=right_flux-left_flux+top_flux-bottom_flux

122:

123:           volume_change_s=volume(j,k)/(volume(j,k)+total_flux)

[...]

129:           recip_volume=1.0/volume(j,k)

130:

131:           energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume

132:

133:           energy1(j,k)=energy0(j,k)-energy_change

134:

135:           density1(j,k)=density0(j,k)*volume_change_s

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	pdv_kernel	PdV_kernel.f90:145	exec
○	pdv	PdV.f90:58	exec
○	hydro	hydro.f90:60	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.75
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.41
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks
Function	pdv_kernel._omp_fn.0
Source	PdV_kernel.f90:118-118,PdV_kernel.f90:135-135
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.63
CQA cycles if no scalar integer	4.92
CQA cycles if FP arith vectorized	8.63
CQA cycles if fully vectorized	1.59
Front-end cycles	7.06
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	7.38
P2 cycles	7.38
P3 cycles	7.38
P4 cycles	7.38
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	8.50
P10 cycles	8.17
P11 cycles	8.33
P12 cycles	1.50
P13 cycles	1.50
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	56.50
Nb uops	56.50
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.63
Bytes prefetched	0.00
Bytes loaded	140.00
Bytes stored	12.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	1.72
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	12.50
Vector-efficiency ratio all	23.73
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.06

Metric	Value
CQA speedup if no scalar integer	6.56
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.03
Bottlenecks	P2, P3, P4, P5,
Function	pdv_kernel._omp_fn.0
Source	PdV_kernel.f90:118-118,PdV_kernel.f90:135-135
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.75
CQA cycles if no scalar integer	1.33
CQA cycles if FP arith vectorized	8.75
CQA cycles if fully vectorized	1.88
Front-end cycles	7.75
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	8.75
P2 cycles	8.75
P3 cycles	8.75
P4 cycles	8.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	8.50
P10 cycles	8.17
P11 cycles	8.33
P12 cycles	1.50
P13 cycles	1.50
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	62.00
Nb uops	62.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.37
Bytes prefetched	0.00
Bytes loaded	140.00
Bytes stored	12.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	3.45
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	25.00
Vector-efficiency ratio all	23.71
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.63

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.48
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P10,
Function	pdv_kernel._omp_fn.0
Source	PdV_kernel.f90:118-118,PdV_kernel.f90:135-135
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.50
CQA cycles if no scalar integer	8.50
CQA cycles if FP arith vectorized	8.50
CQA cycles if fully vectorized	1.31
Front-end cycles	6.38
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	6.00
P2 cycles	6.00
P3 cycles	6.00
P4 cycles	6.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	8.50
P10 cycles	8.17
P11 cycles	8.33
P12 cycles	1.50
P13 cycles	1.50
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	51.00
Nb uops	51.00
Nb loads	NA
Nb stores	3.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	17.88
Bytes prefetched	0.00
Bytes loaded	140.00
Bytes stored	12.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.75
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	pdv_kernel._omp_fn.0
Source file and lines	PdV_kernel.f90:114-135
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/PdV_kernel.f90:114-123,129-135.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/PdV_kernel.f90:118,135.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is probably not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 8.63 to 1.59 cycles (5.41x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization and with fassociative-math (included in Ofast or ffast-math) to extend vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 140 bytes. The binary loop is storing 12 bytes.

General properties

nb instructions	56.50
loop length	226
nb stack references	0

Front-end

front end

7.06 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	7.38	7.38	7.38	7.38	0.00	0.00	0.00	0.00	8.50	8.17	8.33	1.50	1.50
cycles	1.00	1.00	7.38	7.38	7.38	7.38	0.00	0.00	0.00	0.00	8.50	8.17	8.33	1.50	1.50

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.06
Data deps.	1.00
Overall L1	8.63

Vectorization ratios

all	1%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.63 cycles. At this rate:

16% of peak load performance is reached (16.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.39 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Function	pdv_kernel._omp_fn.0
Source file and lines	PdV_kernel.f90:114-135
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.75 to 1.33 cycles (6.56x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization and with fassociative-math (included in Ofast or ffast-math) to extend vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 140 bytes. The binary loop is storing 12 bytes.

General properties

nb instructions	62
loop length	248
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	8.75	8.75	8.75	8.75	0.00	0.00	0.00	0.00	8.50	8.17	8.33	1.50	1.50
cycles	1.00	1.00	8.75	8.75	8.75	8.75	0.00	0.00	0.00	0.00	8.50	8.17	8.33	1.50	1.50

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.75
Data deps.	1.00
Overall L1	8.75

Vectorization ratios

all	3%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.75 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.37 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41dca4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR W20, [SP, #100]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W24, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W25, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W26, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR W26, [SP, #100]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W25, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 41ddf0 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x790>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X27, X14, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X26, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR P1.B, P2/Z, P2.B, P2.B	1	0	0	0	0	1	0	0	0	0	0	0	1	1
ADD X25, X7, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X24, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X23, X6, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X22, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X21, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X20, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X19, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ X1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W27, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W26, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W23, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W27, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
CSEL W22, W23, W27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR W22, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X27, [SP, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [SP, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X14, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X21, [SP, #192]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X13, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X7, X7, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X24, [SP, #200]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X12, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X6, X6, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W19, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CSINC W1, W19, WZR, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X11, X11, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X10, X10, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR W1, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W20, [SP, #100]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X9, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X8, X8, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W26, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X24, [SP, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [SP, #216]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, X5, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X15, X15, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X22, [SP, #224]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X30, X30, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X21, [SP, #232]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X17, X17, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X19, [SP, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X1, [SP, #248]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X16, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X27, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X18, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X3, X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X2, X2, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W26, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 41dca4 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x644>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	pdv_kernel._omp_fn.0
Source file and lines	PdV_kernel.f90:114-135
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 8.50 to 1.31 cycles (6.48x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with ftree-vectorize (included in O3) to enable loop vectorization and with fassociative-math (included in Ofast or ffast-math) to extend vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 140 bytes. The binary loop is storing 12 bytes.

General properties

nb instructions	51
loop length	204
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	6.00	6.00	6.00	6.00	0.00	0.00	0.00	0.00	8.50	8.17	8.33	1.50	1.50
cycles	1.00	1.00	6.00	6.00	6.00	6.00	0.00	0.00	0.00	0.00	8.50	8.17	8.33	1.50	1.50

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.38
Data deps.	1.00
Overall L1	8.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.50 cycles. At this rate:

17% of peak load performance is reached (16.47 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.41 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41dca4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR W20, [SP, #100]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W24, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W25, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W26, W20, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR W26, [SP, #100]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W25, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 41ddf0 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x790>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR W27, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W26, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W23, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W27, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
CSEL W22, W23, W27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR W22, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X27, [SP, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X26, [SP, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X14, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X21, [SP, #192]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X13, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X7, X7, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X24, [SP, #200]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X12, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X6, X6, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W19, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CSINC W1, W19, WZR, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X11, X11, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X10, X10, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR W1, [SP, #104]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W20, [SP, #100]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X9, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X8, X8, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W26, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X25, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X24, [SP, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [SP, #216]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, X5, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X15, X15, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X22, [SP, #224]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X30, X30, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X21, [SP, #232]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X17, X17, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X19, [SP, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X1, [SP, #248]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X16, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X27, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X18, X19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X3, X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X2, X2, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W26, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 41dca4 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x644>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code