OV - exec - Function ideal_gas_kernel._omp

	Function: ideal_gas_kernel._omp_fn.0	Module: exec	Source: ideal_gas_kernel.f90:45-55	Coverage: 7.28%

/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/ideal_gas_kernel.f90: 45 - 55

--------------------------------------------------------------------------------

45:     !$OMP PARALLEL

46:     !$OMP DO PRIVATE(v,pressurebyenergy,pressurebyvolume,sound_speed_squared)

47:     DO k=y_min,y_max

48:     !$OMP SIMD

49:       DO j=x_min,x_max

50:         v=1.0_8/density(j,k)

51:         pressure(j,k)=(1.4_8-1.0_8)*density(j,k)*energy(j,k)

52:         pressurebyenergy=(1.4_8-1.0_8)*density(j,k)

53:         pressurebyvolume=-density(j,k)*pressure(j,k)

54:         sound_speed_squared=v*v*(pressure(j,k)*pressurebyenergy-pressurebyvolume)

55:         soundspeed(j,k)=SQRT(sound_speed_squared)

0x427400 STP	X29, X30, [SP, #944]!

0x427404 ADD	X29, SP, #0

0x427408 STP	X21, X22, [SP, #32]

0x42740c ORR	X22, XZR, X0

0x427410 LDR	X0, [X0, #16]

0x427414 STP	X19, X20, [SP, #16]

0x427418 STP	X23, X24, [SP, #48]

0x42741c LDP	X21, X19, [X22, #64]

0x427420 STR	X25, [SP, #64]

0x427424 LDR	W25, [X0]

0x427428 BL	401b60

0x42742c ORR	W24, WZR, W0

0x427430 BL	401ad0

0x427434 LDR	X1, [X22, #24]

0x427438 ORR	W8, WZR, W0

0x42743c LDP	X20, X3, [X22, #80]

0x427440 LDP	X17, X2, [X22, #96]

0x427444 LDP	X5, X18, [X22, #112]

0x427448 LDR	W4, [X1]

0x42744c ADD	W6, W4, #1

0x427450 SUB	W7, W6, W25

0x427454 SDIV	W9, W7, W24

0x427458 MSUB	W10, W9, W24, W7

0x42745c CMP	W0, W10

0x427460 B.LT	4275ac

(259) 0x427464 MADD	W11, W9, W8, W10

(259) 0x427468 ADD	W13, W9, W11

(259) 0x42746c CMP	W11, W13

(259) 0x427470 B.GE	427594

(259) 0x427474 LDP	X30, X0, [X22]

(259) 0x427478 ADRP	X12,

(259) 0x42747c ADD	W8, W25, W11

(259) 0x427480 ADD	W25, W25, W13

(259) 0x427484 ADD	X13, X12, #4040

(259) 0x427488 FDUP	Z5.D, #112

(259) 0x42748c SBFM	X1, X8, #0, #31

(259) 0x427490 UBFM	X16, X21, #61, #60

(259) 0x427494 PTRUE	P0.B, ALL

(259) 0x427498 UBFM	X15, X20, #61, #60

(259) 0x42749c CNTD	X7, ALL

(259) 0x4274a0 LDR	X24, [X22, #32]

(259) 0x4274a4 UBFM	X14, X17, #61, #60

(259) 0x4274a8 UBFM	X9, X5, #61, #60

(259) 0x4274ac LDR	W10, [X30]

(259) 0x4274b0 LDR	W11, [X0]

(259) 0x4274b4 MOVZ	W0, #0

(259) 0x4274b8 SBFM	X12, X10, #0, #31

(259) 0x4274bc ADD	X19, X19, X12

(259) 0x4274c0 ADD	X6, X3, X12

(259) 0x4274c4 ADD	X3, X2, X12

(259) 0x4274c8 ADD	X2, X18, X12

(259) 0x4274cc MADD	X21, X1, X21, X19

(259) 0x4274d0 CMP	W10, W11

(259) 0x4274d4 MOVZ	W19, #1

(259) 0x4274d8 MADD	X30, X1, X20, X6

(259) 0x4274dc CSINC	W18, W10, W11, #12

(259) 0x4274e0 MADD	X12, X1, X17, X3

(259) 0x4274e4 ADD	W17, W11, W19

(259) 0x4274e8 MADD	X1, X1, X5, X2

(259) 0x4274ec LDR	X2, [X22, #56]

(259) 0x4274f0 SUB	W5, W17, W10

(259) 0x4274f4 ADD	X4, X24, X21,LSL #3

(259) 0x4274f8 LDP	X24, X20, [X22, #40]

(259) 0x4274fc WHILELO	P2.D, XZR, X5

(259) 0x427500 ADD	X6, X24, X30,LSL #3

(259) 0x427504 ADD	X3, X20, X12,LSL #3

(259) 0x427508 ADD	X30, X2, X1,LSL #3

  (260) 0x42750c CMP	W10, W11

  (260) 0x427510 B.GT	427564

  (260) 0x427514 MOVZ	X21, #0

  (260) 0x427518 ORR	P1.B, P2/Z, P2.B, P2.B

  (260) 0x42751c LD1RD	{Z4.D}, P0/Z, [X13]

    (261) 0x427520 LD1D	{Z0.D}, P1/Z, [X4, X21,LSL #3]

    (261) 0x427524 LD1D	{Z2.D}, P1/Z, [X6, X21,LSL #3]

    (261) 0x427528 FMUL	Z1.D, Z0.D, Z4.D

    (261) 0x42752c FDIVR	Z0.D, P0/M, Z0.D, Z5.D

    (261) 0x427530 FMUL	Z6.D, Z1.D, Z2.D

    (261) 0x427534 FMUL	Z7.D, Z0.D, Z0.D

    (261) 0x427538 ST1D	{Z6.D}, P1, [X3, X21,LSL #3]

    (261) 0x42753c LD1D	{Z3.D}, P1/Z, [X4, X21,LSL #3]

    (261) 0x427540 FMUL	Z16.D, Z3.D, Z4.D

    (261) 0x427544 FMUL	Z17.D, Z16.D, Z6.D

    (261) 0x427548 FMAD	Z6.D, P0/M, Z3.D, Z17.D

    (261) 0x42754c FMUL	Z18.D, Z7.D, Z6.D

    (261) 0x427550 FSQRT	Z18.D, P0/M, Z18.D

    (261) 0x427554 ST1D	{Z18.D}, P1, [X30, X21,LSL #3]

    (261) 0x427558 ADD	X21, X21, X7

    (261) 0x42755c WHILELO	P1.D, X21, X5

    (261) 0x427560 B.NE	427520

  (260) 0x427564 CMP	W17, W18

  (260) 0x427568 ADD	W8, W8, #1

  (260) 0x42756c CSEL	W23, W23, W17, #1

  (260) 0x427570 ADD	X4, X4, X16

  (260) 0x427574 ADD	X6, X6, X15

  (260) 0x427578 CSEL	W0, W0, W19, #1

  (260) 0x42757c ADD	X3, X3, X14

  (260) 0x427580 ADD	X30, X30, X9

  (260) 0x427584 CMP	W25, W8

  (260) 0x427588 B.GT	42750c

(259) 0x42758c CBZ	W0, 427594

0x427590 STR	W23, [X22, #128]

(259) 0x427594 LDP	X19, X20, [SP, #16]

(259) 0x427598 LDP	X21, X22, [SP, #32]

(259) 0x42759c LDP	X23, X24, [SP, #48]

(259) 0x4275a0 LDR	X25, [SP, #64]

(259) 0x4275a4 LDP	X29, X30, [SP], #80

(259) 0x4275a8 RET

(259) 0x4275ac ADD	W9, W9, #1

(259) 0x4275b0 MOVZ	W10, #0

(259) 0x4275b4 B	427464

0x4275b8 HINT	#0

0x4275bc HINT	#0

Coverage (%)	Name	Source Location	Module
►47.10+	GOMP_parallel		libgomp.so.1.0.0
○	ideal_gas_kernel	ideal_gas_kernel.f90:45	exec
○	pdv	PdV.f90:124	exec
○	hydro	hydro.f90:56	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec
►47.10+	GOMP_parallel		libgomp.so.1.0.0
○	ideal_gas_kernel	ideal_gas_kernel.f90:45	exec
○	timestep	timestep.f90:60	exec
○	hydro	hydro.f90:54	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec
►4.52+	GOMP_parallel		libgomp.so.1.0.0
○	ideal_gas_kernel	ideal_gas_kernel.f90:45	exec
○	field_summary	field_summary.f90:53	exec
○	hydro	hydro.f90:74	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	ideal_gas_kernel.f90:45-55
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:45-55.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.67 to 0.58 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.67 to 1.00 cycles (4.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 88 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	28
loop length	112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	4.67	4.67	4.67	3.00	3.00
cycles	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	4.67	4.67	4.67	3.00	3.00

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.25
Overall L1	4.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.67 cycles. At this rate:

19% of peak load performance is reached (18.86 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.29 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 427400

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X21, X19, [X22, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W25, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 401b60 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 401ad0 <@plt_start@+0x320>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W8, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X3, [X22, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X17, X2, [X22, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X5, X18, [X22, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W4, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W6, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W7, W6, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W9, W7, W24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W10, W9, W24, W7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4275ac <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x1ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR W23, [X22, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
HINT #0
HINT #0

Source file and lines	ideal_gas_kernel.f90:45-55
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:45-55.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.67 to 1.00 cycles (4.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 88 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	28
loop length	112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	4.67	4.67	4.67	3.00	3.00
cycles	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	4.67	4.67	4.67	3.00	3.00

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.25
Overall L1	4.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.67 cycles. At this rate:

19% of peak load performance is reached (18.86 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.29 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 427400

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X21, X19, [X22, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X25, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W25, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 401b60 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 401ad0 <@plt_start@+0x320>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X22, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W8, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X3, [X22, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X17, X2, [X22, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X5, X18, [X22, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W4, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W6, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W7, W6, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W9, W7, W24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W10, W9, W24, W7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4275ac <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x1ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR W23, [X22, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
HINT #0
HINT #0

Name	Coverage (%)	Time (s)
▼ideal_gas_kernel._omp_fn.0–	7.28	1.55
▼Loop 259 - ideal_gas_kernel.f90:45-55 - exec–	0	0
▼Loop 260 - ideal_gas_kernel.f90:48-55 - exec–	0	0
○Loop 261 - ideal_gas_kernel.f90:50-55 - exec	7.28	1.55

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Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code