OV - exec - Function generate_chunk_kernel._omp

	Function: generate_chunk_kernel._omp_fn.0	Module: exec	Source: generate_chunk_kernel.f90:85-161 [...]	Coverage: 0.05%

/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/generate_chunk_kernel.f90: 85 - 161

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85:     !$OMP PARALLEL SHARED(x_cent,y_cent)

86:     !$OMP DO

87:     DO k=y_min-2,y_max+2

88:     !$OMP SIMD

89:       DO j=x_min-2,x_max+2

90:         energy0(j,k)=state_energy(1)

91:       ENDDO

92:     ENDDO

93:     !$OMP END DO

94:     !$OMP DO

95:     DO k=y_min-2,y_max+2

96:     !$OMP SIMD

97:       DO j=x_min-2,x_max+2

98:         density0(j,k)=state_density(1)

99:       ENDDO

100:     ENDDO

101:     !$OMP END DO

102:     !$OMP DO

103:     DO k=y_min-2,y_max+2

104:     !$OMP SIMD

105:       DO j=x_min-2,x_max+2

106:         xvel0(j,k)=state_xvel(1)

107:       ENDDO

108:     ENDDO

109:     !$OMP END DO

110:     !$OMP DO

111:     DO k=y_min-2,y_max+2

112:     !$OMP SIMD

113:       DO j=x_min-2,x_max+2

114:         yvel0(j,k)=state_yvel(1)

115:       ENDDO

116:     ENDDO

117:     !$OMP END DO

118:

119:     DO state=2,number_of_states

120:

121:       ! Could the velocity setting be thread unsafe?

122:       x_cent=state_xmin(state)

123:       y_cent=state_ymin(state)

124:

125:       !$OMP DO PRIVATE(radius,jt,kt)

126:       DO k=y_min-2,y_max+2

127:       !$OMP SIMD

128:         DO j=x_min-2,x_max+2

129:           IF(state_geometry(state).EQ.g_rect ) THEN

130:             IF(vertexx(j+1).GE.state_xmin(state).AND.vertexx(j).LT.state_xmax(state)) THEN

131:               IF(vertexy(k+1).GE.state_ymin(state).AND.vertexy(k).LT.state_ymax(state)) THEN

132:                 energy0(j,k)=state_energy(state)

133:                 density0(j,k)=state_density(state)

134:                 DO kt=k,k+1

135:                   DO jt=j,j+1

136:                     xvel0(jt,kt)=state_xvel(state)

137:                     yvel0(jt,kt)=state_yvel(state)

138:                   ENDDO

139:                 ENDDO

140:               ENDIF

141:             ENDIF

142:           ELSEIF(state_geometry(state).EQ.g_circ ) THEN

143:             radius=SQRT((cellx(j)-x_cent)*(cellx(j)-x_cent)+(celly(k)-y_cent)*(celly(k)-y_cent))

144:             IF(radius.LE.state_radius(state))THEN

[...]

154:           ELSEIF(state_geometry(state).EQ.g_point) THEN

155:             IF(vertexx(j).EQ.x_cent .AND. vertexy(k).EQ.y_cent) THEN

156:               energy0(j,k)=state_energy(state)

157:               density0(j,k)=state_density(state)

158:               DO kt=k,k+1

159:                 DO jt=j,j+1

160:                   xvel0(jt,kt)=state_xvel(state)

161:                   yvel0(jt,kt)=state_yvel(state)

0x426040 STP	X29, X30, [SP, #656]!

0x426044 ADD	X29, SP, #0

0x426048 STP	X27, X28, [SP, #80]

0x42604c ORR	X27, XZR, X0

0x426050 LDR	X0, [X0, #16]

0x426054 STP	X19, X20, [SP, #16]

0x426058 LDR	X1, [X27, #208]

0x42605c STP	X21, X22, [SP, #32]

0x426060 LDR	W8, [X0]

0x426064 STP	X23, X24, [SP, #48]

0x426068 LDR	X3, [X27, #216]

0x42606c SUB	W23, W8, #2

0x426070 STR	X1, [SP, #360]

0x426074 LDR	X2, [X27, #224]

0x426078 LDR	X4, [X27, #232]

0x42607c STR	X3, [SP, #352]

0x426080 STR	X2, [SP, #128]

0x426084 STR	X4, [SP, #328]

0x426088 BL	401b60

0x42608c LDR	X5, [X27, #240]

0x426090 ORR	W24, WZR, W0

0x426094 STR	W0, [SP, #276]

0x426098 STR	X5, [SP, #120]

0x42609c BL	401ad0

0x4260a0 LDR	X7, [X27, #24]

0x4260a4 ORR	W6, WZR, W0

0x4260a8 STR	W0, [SP, #136]

0x4260ac LDR	X13, [X27, #248]

0x4260b0 LDR	X15, [X27, #256]

0x4260b4 LDR	W9, [X7]

0x4260b8 STR	X13, [SP, #320]

0x4260bc LDR	X18, [X27, #264]

0x4260c0 STR	X15, [SP, #344]

0x4260c4 LDR	X28, [X27, #272]

0x4260c8 ADD	W10, W9, #3

0x4260cc SUB	W11, W10, W23

0x4260d0 LDR	X0, [X27, #280]

0x4260d4 STR	X18, [SP, #336]

0x4260d8 SDIV	W8, W11, W24

0x4260dc LDR	X12, [X27, #288]

0x4260e0 STR	X28, [SP, #104]

0x4260e4 LDR	X14, [X27, #296]

0x4260e8 STR	X0, [SP, #312]

0x4260ec STR	X12, [SP, #96]

0x4260f0 STR	X14, [SP, #304]

0x4260f4 MSUB	W2, W8, W24, W11

0x4260f8 CMP	W6, W2

0x4260fc B.LT	426920

0x426100 LDR	W16, [SP, #136]

0x426104 MADD	W17, W8, W16, W2

0x426108 ADD	W30, W8, W17

0x42610c CMP	W17, W30

0x426110 B.GE	4261c8

0x426114 LDP	X4, X6, [X27]

0x426118 ADD	W3, W23, W17

0x42611c MOVZ	W7, #0

0x426120 SBFM	X1, X3, #0, #31

0x426124 CNTD	X24, ALL

0x426128 PTRUE	P1.B, ALL

0x42612c MOVZ	W5, #1

0x426130 ADD	W23, W23, W30

0x426134 LDR	X14, [SP, #120]

0x426138 LDR	W10, [X4]

0x42613c LDR	W13, [X6]

0x426140 UBFM	X12, X14, #61, #60

0x426144 LDR	X11, [X27, #72]

0x426148 SUB	W9, W10, #2

0x42614c LDR	X15, [SP, #320]

0x426150 ADD	X18, X15, W10,SXTW

0x426154 MADD	X28, X1, X14, X18

0x426158 ADD	W16, W13, #3

0x42615c ADD	W2, W13, #5

0x426160 LDR	X4, [X27, #112]

0x426164 CMP	W9, W16

0x426168 SUB	W17, W2, W10

0x42616c UBFM	X0, X28, #61, #60

0x426170 CSEL	W30, W9, W16, #10

0x426174 SUB	X8, X0, #16

0x426178 WHILELO	P2.D, XZR, X17

0x42617c ADD	X1, X11, X8

(245) 0x426180 MOVZ	X6, #0

(245) 0x426184 ORR	P0.B, P2/Z, P2.B, P2.B

(245) 0x426188 CMP	W9, W16

(245) 0x42618c B.GE	4261a4

  (246) 0x426190 LD1RD	{Z0.D}, P1/Z, [X4]

  (246) 0x426194 ST1D	{Z0.D}, P0, [X1, X6,LSL #3]

  (246) 0x426198 ADD	X6, X6, X24

  (246) 0x42619c WHILELO	P0.D, X6, X17

  (246) 0x4261a0 B.NE	426190

(245) 0x4261a4 CMP	W16, W30

(245) 0x4261a8 ADD	W3, W3, #1

(245) 0x4261ac CSEL	W19, W19, W16, #1

(245) 0x4261b0 ADD	X1, X1, X12

(245) 0x4261b4 CSEL	W7, W7, W5, #1

(245) 0x4261b8 CMP	W23, W3

(245) 0x4261bc B.GT	426180

0x4261c0 CBZ	W7, 4261c8

0x4261c4 STR	W19, [X27, #320]

0x4261c8 BL	401b40

0x4261cc LDP	X19, X23, [X27, #16]

0x4261d0 LDR	W9, [SP, #276]

0x4261d4 LDR	W24, [X23]

0x4261d8 LDR	W11, [X19]

0x4261dc LDR	W14, [SP, #136]

0x4261e0 ADD	W5, W24, #3

0x4261e4 SUB	W13, W11, #2

0x4261e8 SUB	W10, W5, W13

0x4261ec SDIV	W15, W10, W9

0x4261f0 MSUB	W12, W15, W9, W10

0x4261f4 CMP	W14, W12

0x4261f8 B.LT	426914

0x4261fc LDR	W18, [SP, #136]

0x426200 MADD	W28, W15, W18, W12

0x426204 ADD	W0, W15, W28

0x426208 CMP	W28, W0

0x42620c B.GE	4262c8

0x426210 LDP	X2, X4, [X27]

0x426214 ADD	W3, W13, W28

0x426218 ADD	W8, W13, W0

0x42621c SBFM	X16, X3, #0, #31

0x426220 MOVZ	W7, #0

0x426224 PTRUE	P3.B, ALL

0x426228 CNTD	X17, ALL

0x42622c MOVZ	W30, #1

0x426230 LDR	X6, [SP, #128]

0x426234 LDR	W23, [X2]

0x426238 LDR	W19, [X4]

0x42623c UBFM	X11, X6, #61, #60

0x426240 LDR	X1, [X27, #64]

0x426244 SUB	W24, W23, #2

0x426248 LDR	X5, [SP, #328]

0x42624c ADD	X13, X5, W23,SXTW

0x426250 MADD	X10, X16, X6, X13

0x426254 ADD	W15, W19, #3

0x426258 ADD	W12, W19, #5

0x42625c LDR	X16, [X27, #104]

0x426260 CMP	W24, W15

0x426264 SUB	W18, W12, W23

0x426268 UBFM	X9, X10, #61, #60

0x42626c CSEL	W28, W24, W15, #10

0x426270 SUB	X14, X9, #16

0x426274 WHILELO	P4.D, XZR, X18

0x426278 ADD	X2, X1, X14

0x42627c HINT	#0

(243) 0x426280 MOVZ	X0, #0

(243) 0x426284 ORR	P5.B, P4/Z, P4.B, P4.B

(243) 0x426288 CMP	W24, W15

(243) 0x42628c B.GE	4262a4

  (244) 0x426290 LD1RD	{Z1.D}, P3/Z, [X16]

  (244) 0x426294 ST1D	{Z1.D}, P5, [X2, X0,LSL #3]

  (244) 0x426298 ADD	X0, X0, X17

  (244) 0x42629c WHILELO	P5.D, X0, X18

  (244) 0x4262a0 B.NE	426290

(243) 0x4262a4 CMP	W15, W28

(243) 0x4262a8 ADD	W3, W3, #1

(243) 0x4262ac CSEL	W20, W20, W15, #1

(243) 0x4262b0 ADD	X2, X2, X11

(243) 0x4262b4 CSEL	W7, W7, W30, #1

(243) 0x4262b8 CMP	W8, W3

(243) 0x4262bc B.GT	426280

0x4262c0 CBZ	W7, 4262c8

0x4262c4 STR	W20, [X27, #320]

0x4262c8 BL	401b40

0x4262cc LDP	X20, X8, [X27, #16]

0x4262d0 LDR	W6, [SP, #276]

0x4262d4 LDR	W4, [X8]

0x4262d8 LDR	W19, [X20]

0x4262dc LDR	W5, [SP, #136]

0x4262e0 ADD	W1, W4, #3

0x4262e4 SUB	W23, W19, #2

0x4262e8 SUB	W24, W1, W23

0x4262ec SDIV	W11, W24, W6

0x4262f0 MSUB	W13, W11, W6, W24

0x4262f4 CMP	W5, W13

0x4262f8 B.LT	426938

0x4262fc LDR	W17, [SP, #136]

0x426300 MADD	W30, W11, W17, W13

0x426304 ADD	W10, W11, W30

0x426308 CMP	W30, W10

0x42630c B.GE	4263c8

0x426310 LDP	X9, X12, [X27]

0x426314 ADD	W3, W23, W30

0x426318 ADD	W14, W23, W10

0x42631c SBFM	X15, X3, #0, #31

0x426320 MOVZ	W7, #0

0x426324 PTRUE	P6.B, ALL

0x426328 CNTD	X18, ALL

0x42632c MOVZ	W28, #1

0x426330 LDR	X20, [SP, #104]

0x426334 LDR	W2, [X9]

0x426338 LDR	W0, [X12]

0x42633c UBFM	X19, X20, #61, #60

0x426340 LDR	X16, [X27, #80]

0x426344 SUB	W5, W2, #2

0x426348 LDR	X8, [SP, #312]

0x42634c ADD	X4, X8, W2,SXTW

0x426350 MADD	X1, X15, X20, X4

0x426354 ADD	W6, W0, #3

0x426358 ADD	W11, W0, #5

0x42635c LDR	X30, [X27, #120]

0x426360 CMP	W5, W6

0x426364 SUB	W13, W11, W2

0x426368 UBFM	X23, X1, #61, #60

0x42636c CSEL	W17, W5, W6, #10

0x426370 SUB	X24, X23, #16

0x426374 WHILELO	P7.D, XZR, X13

0x426378 ADD	X15, X16, X24

0x42637c HINT	#0

(241) 0x426380 MOVZ	X10, #0

(241) 0x426384 ORR	P1.B, P7/Z, P7.B, P7.B

(241) 0x426388 CMP	W5, W6

(241) 0x42638c B.GE	4263a4

  (242) 0x426390 LD1RD	{Z2.D}, P6/Z, [X30]

  (242) 0x426394 ST1D	{Z2.D}, P1, [X15, X10,LSL #3]

  (242) 0x426398 ADD	X10, X10, X18

  (242) 0x42639c WHILELO	P1.D, X10, X13

  (242) 0x4263a0 B.NE	426390

(241) 0x4263a4 CMP	W17, W6

(241) 0x4263a8 ADD	W3, W3, #1

(241) 0x4263ac CSEL	W21, W21, W17, #1

(241) 0x4263b0 ADD	X15, X15, X19

(241) 0x4263b4 CSEL	W7, W7, W28, #1

(241) 0x4263b8 CMP	W14, W3

(241) 0x4263bc B.GT	426380

0x4263c0 CBZ	W7, 4263c8

0x4263c4 STR	W21, [X27, #320]

0x4263c8 BL	401b40

0x4263cc LDP	X21, X14, [X27, #16]

0x4263d0 LDR	W20, [SP, #276]

0x4263d4 LDR	W18, [X14]

0x4263d8 LDR	W9, [X21]

0x4263dc LDR	W8, [SP, #136]

0x4263e0 ADD	W28, W18, #3

0x4263e4 SUB	W12, W9, #2

0x4263e8 SUB	W2, W28, W12

0x4263ec SDIV	W0, W2, W20

0x4263f0 MSUB	W19, W0, W20, W2

0x4263f4 CMP	W8, W19

0x4263f8 B.LT	42692c

0x4263fc LDR	W16, [SP, #136]

0x426400 MADD	W4, W0, W16, W19

0x426404 ADD	W1, W0, W4

0x426408 CMP	W4, W1

0x42640c B.GE	4264c8

0x426410 LDP	X6, X11, [X27]

0x426414 ADD	W3, W12, W4

0x426418 ADD	W23, W12, W1

0x42641c SBFM	X24, X3, #0, #31

0x426420 MOVZ	W7, #0

0x426424 PTRUE	P3.B, ALL

0x426428 CNTD	X5, ALL

0x42642c MOVZ	W13, #1

0x426430 LDR	X21, [SP, #96]

0x426434 LDR	W10, [X6]

0x426438 LDR	W30, [X11]

0x42643c UBFM	X18, X21, #61, #60

0x426440 LDR	X17, [X27, #88]

0x426444 SUB	W15, W10, #2

0x426448 LDR	X14, [SP, #304]

0x42644c ADD	X28, X14, W10,SXTW

0x426450 MADD	X9, X24, X21, X28

0x426454 ADD	W20, W30, #3

0x426458 ADD	W8, W30, #5

0x42645c LDR	X4, [X27, #128]

0x426460 CMP	W15, W20

0x426464 SUB	W19, W8, W10

0x426468 UBFM	X12, X9, #61, #60

0x42646c CSEL	W16, W15, W20, #10

0x426470 SUB	X2, X12, #16

0x426474 WHILELO	P8.D, XZR, X19

0x426478 ADD	X1, X17, X2

0x42647c HINT	#0

(239) 0x426480 MOVZ	X0, #0

(239) 0x426484 ORR	P2.B, P8/Z, P8.B, P8.B

(239) 0x426488 CMP	W15, W20

(239) 0x42648c B.GE	4264a4

  (240) 0x426490 LD1RD	{Z3.D}, P3/Z, [X4]

  (240) 0x426494 ST1D	{Z3.D}, P2, [X1, X0,LSL #3]

  (240) 0x426498 ADD	X0, X0, X5

  (240) 0x42649c WHILELO	P2.D, X0, X19

  (240) 0x4264a0 B.NE	426490

(239) 0x4264a4 CMP	W20, W16

(239) 0x4264a8 ADD	W3, W3, #1

(239) 0x4264ac CSEL	W22, W22, W20, #1

(239) 0x4264b0 ADD	X1, X1, X18

(239) 0x4264b4 CSEL	W7, W7, W13, #1

(239) 0x4264b8 CMP	W23, W3

(239) 0x4264bc B.GT	426480

0x4264c0 CBZ	W7, 4264c8

0x4264c4 STR	W22, [X27, #320]

0x4264c8 BL	401b40

0x4264cc LDR	X23, [X27, #96]

0x4264d0 MOVZ	X22, #1

0x4264d4 STR	W22, [SP, #272]

0x4264d8 LDR	W24, [X23]

0x4264dc SBFM	X5, X24, #0, #31

0x4264e0 STR	X5, [SP, #280]

0x4264e4 CMP	W24, #1

0x4264e8 B.LE	4268f0

0x4264ec ORR	X19, XZR, X22

0x4264f0 STP	X25, X26, [SP, #64]

0x4264f4 B	42650c

  (235) 0x4264f8 BL	401b40

  (235) 0x4264fc LDR	X11, [SP, #280]

  (235) 0x426500 ADD	X19, X19, #1

  (235) 0x426504 CMP	X19, X11

  (235) 0x426508 B.EQ	4268ec

(236) 0x42650c LDP	X26, X13, [X27, #16]

(236) 0x426510 LDR	W25, [SP, #276]

(236) 0x426514 LDR	W6, [X13]

(236) 0x426518 LDR	W17, [X26]

(236) 0x42651c LDR	X20, [X27, #136]

(236) 0x426520 ADD	W11, W6, #3

(236) 0x426524 LDR	X15, [X27, #152]

(236) 0x426528 SUB	W30, W17, #2

(236) 0x42652c SUB	W10, W11, W30

(236) 0x426530 LDR	W21, [SP, #136]

(236) 0x426534 SDIV	W14, W10, W25

(236) 0x426538 LDR	D2, [X20, X19,LSL #3]

(236) 0x42653c STR	X15, [SP, #152]

(236) 0x426540 LDR	D4, [X15, X19,LSL #3]

(236) 0x426544 STP	D4, D2, [X27, #304]

(236) 0x426548 MSUB	W18, W14, W25, W10

(236) 0x42654c CMP	W21, W18

(236) 0x426550 B.LT	426908

  (235) 0x426554 LDR	W28, [SP, #136]

  (235) 0x426558 MADD	W9, W14, W28, W18

  (235) 0x42655c ADD	W12, W14, W9

  (235) 0x426560 CMP	W9, W12

  (235) 0x426564 B.GE	4264f8

  (235) 0x426568 LDR	X2, [X27]

  (235) 0x42656c ADD	W1, W30, W12

  (235) 0x426570 ADD	W9, W30, W9

  (235) 0x426574 LDP	X16, X4, [SP, #336]

  (235) 0x426578 SBFM	X25, X9, #0, #31

  (235) 0x42657c MOVZ	W10, #0

  (235) 0x426580 UBFM	X13, X19, #61, #60

  (235) 0x426584 LDP	X5, X22, [X27, #32]

  (235) 0x426588 ADD	X23, X16, X25

  (235) 0x42658c LDP	X26, X6, [SP, #304]

  (235) 0x426590 ADD	X16, X22, X23,LSL #3

  (235) 0x426594 ADD	X14, X5, #8

  (235) 0x426598 LDR	W0, [X2]

  (235) 0x42659c LDR	X24, [SP, #352]

  (235) 0x4265a0 LDR	X7, [X27, #56]

  (235) 0x4265a4 SUB	W8, W0, #2

  (235) 0x4265a8 LDR	X28, [SP, #96]

  (235) 0x4265ac STP	W1, W8, [SP, #140]

  (235) 0x4265b0 ADD	X11, X24, X25

  (235) 0x4265b4 LDR	X1, [X27, #8]

  (235) 0x4265b8 ADD	X15, X7, X11,LSL #3

  (235) 0x4265bc LDR	X18, [SP, #104]

  (235) 0x4265c0 LDR	X17, [SP, #120]

  (235) 0x4265c4 LDR	X30, [SP, #128]

  (235) 0x4265c8 MADD	X22, X25, X18, X6

  (235) 0x4265cc LDR	X3, [SP, #320]

  (235) 0x4265d0 LDR	X21, [SP, #328]

  (235) 0x4265d4 LDR	W7, [X1]

  (235) 0x4265d8 MADD	X24, X25, X17, X3

  (235) 0x4265dc MADD	X17, X25, X28, X26

  (235) 0x4265e0 MADD	X23, X25, X30, X21

  (235) 0x4265e4 SBFM	X25, X0, #0, #31

  (235) 0x4265e8 LDR	X21, [SP, #360]

  (235) 0x4265ec ADD	X2, X4, X25

  (235) 0x4265f0 ADD	X6, X25, X6

  (235) 0x4265f4 ADD	X12, X5, X2,LSL #3

  (235) 0x4265f8 LDR	X5, [X27, #64]

  (235) 0x4265fc ADD	W3, W7, #4

  (235) 0x426600 SUB	W4, W3, W0

  (235) 0x426604 ADD	X26, X25, X26

  (235) 0x426608 ADD	X11, X4, X2

  (235) 0x42660c LDR	X30, [X27, #72]

  (235) 0x426610 UBFM	X0, X25, #61, #60

  (235) 0x426614 STR	X12, [SP, #192]

  (235) 0x426618 ADD	X12, X14, X11,LSL #3

  (235) 0x42661c ADD	X14, X21, X25

  (235) 0x426620 LDR	X25, [X27, #48]

  (235) 0x426624 UBFM	X28, X14, #61, #60

  (235) 0x426628 ADD	W18, W7, #3

  (235) 0x42662c ADD	X2, X5, X0

  (235) 0x426630 STP	X6, X26, [SP, #240]

  (235) 0x426634 SUB	X1, X28, #16

  (235) 0x426638 SUB	X3, X2, #16

  (235) 0x42663c CMP	W18, W8

  (235) 0x426640 CSEL	W8, W8, W18, #13

  (235) 0x426644 ADD	X4, X30, X0

  (235) 0x426648 LDR	X5, [X27, #80]

  (235) 0x42664c SUB	X11, X4, #16

  (235) 0x426650 ADD	X7, X25, X1

  (235) 0x426654 STR	W8, [SP, #148]

  (235) 0x426658 LDR	X6, [X27, #88]

  (235) 0x42665c STR	X3, [SP, #232]

  (235) 0x426660 STR	X5, [SP, #176]

  (235) 0x426664 ADD	X8, X5, X0

  (235) 0x426668 STR	X6, [SP, #184]

  (235) 0x42666c ADD	X0, X6, X0

  (235) 0x426670 STR	X7, [SP, #200]

  (235) 0x426674 STR	X11, [SP, #224]

  (235) 0x426678 LDR	W11, [SP, #116]

  (235) 0x42667c STR	X27, [SP, #296]

  (235) 0x426680 LDR	X1, [X27, #104]

  (235) 0x426684 LDP	X26, X25, [X27, #120]

  (235) 0x426688 LDP	X14, X21, [X27, #192]

  (235) 0x42668c STP	X8, X0, [SP, #208]

  (235) 0x426690 LDR	X7, [X27, #112]

  (235) 0x426694 STR	X1, [SP, #264]

  (235) 0x426698 LDR	X30, [X27, #144]

  (235) 0x42669c LDR	X2, [X27, #160]

  (235) 0x4266a0 STR	X7, [SP, #256]

  (235) 0x4266a4 LDR	X28, [X27, #168]

  (235) 0x4266a8 LDR	X3, [X27, #176]

  (235) 0x4266ac STR	X2, [SP, #288]

  (235) 0x4266b0 LDR	X27, [X27, #184]

  (235) 0x4266b4 STR	X3, [SP, #160]

  (235) 0x4266b8 STR	X27, [SP, #168]

  (235) 0x4266bc HINT	#0

    (237) 0x4266c0 LDR	W5, [SP, #144]

    (237) 0x4266c4 ADD	W9, W9, #1

    (237) 0x4266c8 CMP	W18, W5

    (237) 0x4266cc B.LE	42687c

    (237) 0x4266d0 LDR	X8, [SP, #104]

    (237) 0x4266d4 SBFM	X1, X9, #0, #31

    (237) 0x4266d8 LDP	X4, X5, [SP, #240]

    (237) 0x4266dc STR	W9, [SP, #116]

    (237) 0x4266e0 LDR	X7, [SP, #168]

    (237) 0x4266e4 MADD	X2, X1, X8, X4

    (237) 0x4266e8 LDR	X4, [SP, #96]

    (237) 0x4266ec LDR	X6, [SP, #160]

    (237) 0x4266f0 LDR	W27, [X7]

    (237) 0x4266f4 MADD	X1, X1, X4, X5

    (237) 0x4266f8 LDR	X4, [SP, #176]

    (237) 0x4266fc LDR	X5, [SP, #208]

    (237) 0x426700 LDR	X0, [SP, #224]

    (237) 0x426704 ADD	X2, X4, X2,LSL #3

    (237) 0x426708 LDR	X4, [SP, #184]

    (237) 0x42670c ADD	X5, X5, X22,LSL #3

    (237) 0x426710 LDR	X7, [SP, #232]

    (237) 0x426714 ADD	X8, X0, X24,LSL #3

    (237) 0x426718 LDR	W6, [X6, X19,LSL #2]

    (237) 0x42671c ADD	X1, X4, X1,LSL #3

    (237) 0x426720 LDR	X4, [SP, #216]

    (237) 0x426724 ADD	X7, X7, X23,LSL #3

    (237) 0x426728 LDR	X0, [SP, #192]

    (237) 0x42672c LDR	X3, [SP, #200]

    (237) 0x426730 ADD	X4, X4, X17,LSL #3

    (237) 0x426734 B	426778

      (238) 0x426738 LDR	W9, [X14]

      (238) 0x42673c CMP	W6, W9

      (238) 0x426740 B.EQ	42684c

      (238) 0x426744 LDR	W9, [X21]

      (238) 0x426748 CMP	W6, W9

      (238) 0x42674c B.EQ	4267d8

      (238) 0x426750 ADD	X0, X0, #8

      (238) 0x426754 ADD	X8, X8, #8

      (238) 0x426758 ADD	X7, X7, #8

      (238) 0x42675c ADD	X5, X5, #8

      (238) 0x426760 ADD	X4, X4, #8

      (238) 0x426764 ADD	X2, X2, #8

      (238) 0x426768 ADD	X1, X1, #8

      (238) 0x42676c ADD	X3, X3, #8

      (238) 0x426770 CMP	X0, X12

      (238) 0x426774 B.EQ	426878

      (238) 0x426778 CMP	W6, W27

      (238) 0x42677c B.NE	426738

      (238) 0x426780 LDUR	D24, [X0, #504]

      (238) 0x426784 LDR	D23, [X20, X19,LSL #3]

      (238) 0x426788 FCMPE	D24, D23

      (238) 0x42678c B.GE	426794

      (238) 0x426790 B	426750

      (238) 0x426794 LDUR	D26, [X0, #496]

      (238) 0x426798 LDR	D25, [X30, X19,LSL #3]

      (238) 0x42679c FCMPE	D26, D25

      (238) 0x4267a0 B.MI	4267a8

      (238) 0x4267a4 B	426750

      (238) 0x4267a8 LDR	X9, [SP, #152]

      (238) 0x4267ac LDR	D27, [X16, #8]

      (238) 0x4267b0 LDR	D28, [X9, X19,LSL #3]

      (238) 0x4267b4 FCMPE	D27, D28

      (238) 0x4267b8 B.GE	4267c0

      (238) 0x4267bc B	426750

      (238) 0x4267c0 LDR	X9, [SP, #288]

      (238) 0x4267c4 LDR	D29, [X16]

      (238) 0x4267c8 LDR	D30, [X9, X19,LSL #3]

      (238) 0x4267cc FCMPE	D29, D30

      (238) 0x4267d0 B.MI	4267f0

      (238) 0x4267d4 B	426750

      (238) 0x4267d8 LDUR	D5, [X0, #496]

      (238) 0x4267dc FCMP	D2, D5

      (238) 0x4267e0 B.NE	426750

      (238) 0x4267e4 LDR	D6, [X16]

      (238) 0x4267e8 FCMP	D4, D6

      (238) 0x4267ec B.NE	426750

      (238) 0x4267f0 LDR	X9, [SP, #256]

      (238) 0x4267f4 LDR	D31, [X9, X19,LSL #3]

      (238) 0x4267f8 LDR	X9, [SP, #264]

      (238) 0x4267fc STR	D31, [X8]

      (238) 0x426800 LDR	D0, [X9, X19,LSL #3]

      (238) 0x426804 STR	D0, [X7]

      (238) 0x426808 LDR	D1, [X26, X13]

      (238) 0x42680c STUR	D1, [X5, #496]

      (238) 0x426810 LDR	D3, [X25, X13]

      (238) 0x426814 STUR	D3, [X4, #496]

      (238) 0x426818 LDR	D5, [X26, X13]

      (238) 0x42681c STUR	D5, [X5, #504]

      (238) 0x426820 LDR	D6, [X25, X13]

      (238) 0x426824 STUR	D6, [X4, #504]

      (238) 0x426828 LDR	D7, [X26, X13]

      (238) 0x42682c STUR	D7, [X2, #496]

      (238) 0x426830 LDR	D16, [X25, X13]

      (238) 0x426834 STUR	D16, [X1, #496]

      (238) 0x426838 LDR	D17, [X26, X13]

      (238) 0x42683c STUR	D17, [X2, #504]

      (238) 0x426840 LDR	D18, [X25, X13]

      (238) 0x426844 STUR	D18, [X1, #504]

      (238) 0x426848 B	426750

      (238) 0x42684c LDR	D18, [X15]

      (238) 0x426850 LDR	D16, [X3]

      (238) 0x426854 LDR	D7, [X28, X19,LSL #3]

      (238) 0x426858 FSUB	D19, D18, S4

      (238) 0x42685c FSUB	D17, D16, S2

      (238) 0x426860 FMUL	D20, D19, D19

      (238) 0x426864 FMADD	D21, D17, D17, D20

      (238) 0x426868 FSQRT	D22, D21

      (238) 0x42686c FCMPE	D22, D7

      (238) 0x426870 B.LS	4267f0

      (238) 0x426874 B	426750

    (237) 0x426878 LDR	W9, [SP, #116]

    (237) 0x42687c ADD	X16, X16, #8

    (237) 0x426880 ADD	X15, X15, #8

    (237) 0x426884 LDR	W6, [SP, #148]

    (237) 0x426888 LDR	W4, [SP, #140]

    (237) 0x42688c LDR	X5, [SP, #96]

    (237) 0x426890 CMP	W18, W6

    (237) 0x426894 CSEL	W11, W11, W18, #1

    (237) 0x426898 LDR	X7, [SP, #104]

    (237) 0x42689c LDR	X0, [SP, #120]

    (237) 0x4268a0 ADD	X17, X17, X5

    (237) 0x4268a4 LDR	X8, [SP, #128]

    (237) 0x4268a8 ADD	X22, X22, X7

    (237) 0x4268ac LDR	W27, [SP, #272]

    (237) 0x4268b0 CSEL	W10, W10, W27, #1

    (237) 0x4268b4 ADD	X24, X24, X0

    (237) 0x4268b8 ADD	X23, X23, X8

    (237) 0x4268bc CMP	W4, W9

    (237) 0x4268c0 B.GT	4266c0

  (235) 0x4268c4 STR	W11, [SP, #116]

  (235) 0x4268c8 LDR	X27, [SP, #296]

  (235) 0x4268cc CBZ	W10, 4264f8

0x4268d0 ORR	W10, WZR, W11

0x4268d4 ADD	X19, X19, #1

0x4268d8 STR	W10, [X27, #320]

0x4268dc BL	401b40

0x4268e0 LDR	X11, [SP, #280]

0x4268e4 CMP	X19, X11

0x4268e8 B.NE	42650c

  (235) 0x4268ec LDP	X25, X26, [SP, #64]

  (235) 0x4268f0 LDP	X19, X20, [SP, #16]

  (235) 0x4268f4 LDP	X21, X22, [SP, #32]

  (235) 0x4268f8 LDP	X23, X24, [SP, #48]

  (235) 0x4268fc LDP	X27, X28, [SP, #80]

  (235) 0x426900 LDP	X29, X30, [SP], #368

  (235) 0x426904 RET

  (235) 0x426908 ADD	W14, W14, #1

  (235) 0x42690c MOVZ	W18, #0

  (235) 0x426910 B	426554

0x426914 ADD	W15, W15, #1

0x426918 MOVZ	W12, #0

0x42691c B	4261fc

0x426920 ADD	W8, W8, #1

0x426924 MOVZ	W2, #0

0x426928 B	426100

0x42692c ADD	W0, W0, #1

0x426930 MOVZ	W19, #0

0x426934 B	4263fc

0x426938 ADD	W11, W11, #1

0x42693c MOVZ	W13, #0

0x426940 B	4262fc

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk_kernel	generate_chunk_kernel.f90:174	exec
○	generate_chunk	generate_chunk.f90:75	exec
○	start	start.f90:104	exec
○	initialise	initialise.f90:141	exec
○	main	clover_leaf.f90:72	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	generate_chunk_kernel.f90:85-161
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:85-144,154-161.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 35.75 to 5.00 cycles (7.15x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 20% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 35.75 to 31.17 cycles (1.15x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 35.75 to 3.50 cycles (10.21x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 476 bytes. The binary function is storing 232 bytes.

General properties

nb instructions	257
loop length	1028
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

31.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	13.00	13.00	35.75	35.75	35.75	35.75	0.00	0.00	0.00	0.00	31.17	30.83	31.00	13.50	13.50
cycles	13.00	13.00	35.75	35.75	35.75	35.75	0.00	0.00	0.00	0.00	31.17	30.83	31.00	13.50	13.50

Cycles executing div or sqrt instructions

4.00-2.00

Cycles summary

Front-end	31.75
Overall L1	35.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 35.75 cycles. At this rate:

13% of peak load performance is reached (13.31 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.49 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 426040

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #656]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X1, [X27, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X27, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W23, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X1, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X2, [X27, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X27, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X3, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X2, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401b60 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [X27, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W0, [SP, #276]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X5, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401ad0 <@plt_start@+0x320>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X7, [X27, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W6, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W0, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X27, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X27, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X13, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X27, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X15, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X28, [X27, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W10, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W11, W10, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X27, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X18, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SDIV W8, W11, W24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
LDR X12, [X27, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X28, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X27, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X12, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X14, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MSUB W2, W8, W24, W11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W6, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 426920 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x8e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W16, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD W17, W8, W16, W2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W30, W8, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W17, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4261c8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X4, X6, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W3, W23, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X1, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X24, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P1.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W23, W23, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W10, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W13, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X12, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X27, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W9, W10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X15, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X15, W10,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
MADD X28, X1, X14, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W16, W13, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W2, W13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X4, [X27, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W9, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB W17, W2, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X0, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL W30, W9, W16, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
WHILELO P2.D, XZR, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ADD X1, X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ W7, 4261c8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR W19, [X27, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401b40 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X19, X23, [X27, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W9, [SP, #276]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W24, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W11, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W14, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W5, W24, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W13, W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W10, W5, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W15, W10, W9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W12, W15, W9, W10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W14, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 426914 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x8d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W18, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD W28, W15, W18, W12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W0, W15, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W28, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4262c8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X2, X4, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W3, W13, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W13, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X16, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CNTD X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ W30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W23, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W19, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X11, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X27, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W24, W23, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X5, W23,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
MADD X10, X16, X6, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W15, W19, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W12, W19, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X16, [X27, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W24, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB W18, W12, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X9, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL W28, W24, W15, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X14, X9, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
WHILELO P4.D, XZR, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ADD X2, X1, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
CBZ W7, 4262c8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR W20, [X27, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401b40 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X8, [X27, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W6, [SP, #276]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W4, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W19, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W5, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W1, W4, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W23, W19, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W24, W1, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W11, W24, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W13, W11, W6, W24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W5, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 426938 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x8f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W17, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD W30, W11, W17, W13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W10, W11, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W30, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4263c8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x388>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X9, X12, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W3, W23, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W14, W23, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X15, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CNTD X18, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ W28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X20, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W2, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W0, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X19, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X16, [X27, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W5, W2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X8, W2,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
MADD X1, X15, X20, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W6, W0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W11, W0, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X30, [X27, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W5, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB W13, W11, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X23, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL W17, W5, W6, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X24, X23, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
WHILELO P7.D, XZR, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ADD X15, X16, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
CBZ W7, 4263c8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x388>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR W21, [X27, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401b40 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X21, X14, [X27, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W20, [SP, #276]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W18, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W28, W18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W2, W28, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W0, W2, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W19, W0, W20, W2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W8, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42692c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x8ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W16, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD W4, W0, W16, W19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W1, W0, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W4, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4264c8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x488>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X6, X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W3, W12, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W23, W12, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X24, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CNTD X5, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W10, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W30, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X18, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X17, [X27, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W15, W10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X28, X14, W10,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
MADD X9, X24, X21, X28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W20, W30, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W30, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X4, [X27, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W15, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB W19, W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X12, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL W16, W15, W20, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X2, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
WHILELO P8.D, XZR, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ADD X1, X17, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
CBZ W7, 4264c8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x488>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR W22, [X27, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401b40 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X23, [X27, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W22, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W24, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X5, X24, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4268f0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x8b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 42650c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x4cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W10, WZR, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X19, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W10, [X27, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401b40 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X19, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 42650c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x4cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W15, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4261fc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 426100 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W0, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4263fc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x3bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W11, W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4262fc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	generate_chunk_kernel.f90:85-161
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 35.75 to 5.00 cycles (7.15x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 35.75 to 3.50 cycles (10.21x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 476 bytes. The binary function is storing 232 bytes.

General properties

nb instructions	257
loop length	1028
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

31.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	13.00	13.00	35.75	35.75	35.75	35.75	0.00	0.00	0.00	0.00	31.17	30.83	31.00	13.50	13.50
cycles	13.00	13.00	35.75	35.75	35.75	35.75	0.00	0.00	0.00	0.00	31.17	30.83	31.00	13.50	13.50

Cycles executing div or sqrt instructions

4.00-2.00

Cycles summary

Front-end	31.75
Overall L1	35.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 35.75 cycles. At this rate:

13% of peak load performance is reached (13.31 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.49 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 426040

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #656]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X27, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X1, [X27, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W8, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X3, [X27, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W23, W8, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X1, [SP, #360]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X2, [X27, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X27, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X3, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X2, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X4, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401b60 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X5, [X27, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W0, [SP, #276]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X5, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401ad0 <@plt_start@+0x320>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X7, [X27, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W6, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W0, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X13, [X27, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X15, [X27, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X13, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X18, [X27, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X15, [SP, #344]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X28, [X27, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W10, W9, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W11, W10, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X27, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X18, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SDIV W8, W11, W24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
LDR X12, [X27, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X28, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X27, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X12, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X14, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MSUB W2, W8, W24, W11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W6, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 426920 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x8e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W16, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD W17, W8, W16, W2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W30, W8, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W17, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4261c8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X4, X6, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W3, W23, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X1, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X24, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
PTRUE P1.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W23, W23, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W10, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W13, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X12, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X27, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W9, W10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X15, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X15, W10,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
MADD X28, X1, X14, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W16, W13, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W2, W13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X4, [X27, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W9, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB W17, W2, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X0, X28, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL W30, W9, W16, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X8, X0, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
WHILELO P2.D, XZR, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ADD X1, X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CBZ W7, 4261c8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x188>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR W19, [X27, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401b40 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X19, X23, [X27, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W9, [SP, #276]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W24, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W11, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W14, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W5, W24, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W13, W11, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W10, W5, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W15, W10, W9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W12, W15, W9, W10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W14, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 426914 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x8d4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W18, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD W28, W15, W18, W12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W0, W15, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W28, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4262c8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X2, X4, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W3, W13, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W13, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X16, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CNTD X17, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ W30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X6, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W23, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W19, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X11, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X27, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W24, W23, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X5, W23,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
MADD X10, X16, X6, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W15, W19, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W12, W19, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X16, [X27, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W24, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB W18, W12, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X9, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL W28, W24, W15, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X14, X9, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
WHILELO P4.D, XZR, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ADD X2, X1, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
CBZ W7, 4262c8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x288>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR W20, [X27, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401b40 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X20, X8, [X27, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W6, [SP, #276]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W4, [X8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W19, [X20]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W5, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W1, W4, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W23, W19, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W24, W1, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W11, W24, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W13, W11, W6, W24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W5, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 426938 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x8f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W17, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD W30, W11, W17, W13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W10, W11, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W30, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4263c8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x388>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X9, X12, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W3, W23, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W14, W23, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X15, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P6.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CNTD X18, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ W28, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X20, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W2, [X9]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W0, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X19, X20, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X16, [X27, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W5, W2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [SP, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X8, W2,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
MADD X1, X15, X20, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W6, W0, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W11, W0, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X30, [X27, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W5, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB W13, W11, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X23, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL W17, W5, W6, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X24, X23, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
WHILELO P7.D, XZR, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ADD X15, X16, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
CBZ W7, 4263c8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x388>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR W21, [X27, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401b40 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X21, X14, [X27, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W20, [SP, #276]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W18, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W28, W18, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W9, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W2, W28, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W0, W2, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W19, W0, W20, W2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W8, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42692c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x8ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W16, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD W4, W0, W16, W19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W1, W0, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W4, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 4264c8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x488>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X6, X11, [X27]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W3, W12, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W23, W12, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X24, X3, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W7, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CNTD X5, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X21, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W10, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W30, [X11]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X18, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X17, [X27, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W15, W10, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X28, X14, W10,SXTW	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
MADD X9, X24, X21, X28	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W20, W30, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W8, W30, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X4, [X27, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W15, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
SUB W19, W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X12, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL W16, W15, W20, #10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X2, X12, #16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
WHILELO P8.D, XZR, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
ADD X1, X17, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
CBZ W7, 4264c8 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x488>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR W22, [X27, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401b40 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X23, [X27, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W22, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W24, [X23]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X5, X24, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X5, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 4268f0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x8b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X19, XZR, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 42650c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x4cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W10, WZR, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X19, X19, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W10, [X27, #320]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401b40 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X19, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.NE 42650c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x4cc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W15, W15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W12, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4261fc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x1bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W8, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W2, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 426100 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0xc0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W0, W0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W19, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4263fc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x3bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W11, W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W13, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4262fc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼generate_chunk_kernel._omp_fn.0–	0.05	0.01
▼Loop 245 - generate_chunk_kernel.f90:90-90 - exec–	0	0
○Loop 246 - generate_chunk_kernel.f90:90-90 - exec	0	0
▼Loop 239 - generate_chunk_kernel.f90:114-114 - exec–	0	0
○Loop 240 - generate_chunk_kernel.f90:114-114 - exec	0	0
▼Loop 236 - generate_chunk_kernel.f90:85-161 - exec–	0	0
▼Loop 235 - generate_chunk_kernel.f90:85-161 - exec–	0	0
▼Loop 237 - generate_chunk_kernel.f90:129-155 - exec–	0	0
○Loop 238 - generate_chunk_kernel.f90:129-155 - exec	0.05	0.01
▼Loop 243 - generate_chunk_kernel.f90:98-98 - exec–	0	0
○Loop 244 - generate_chunk_kernel.f90:98-98 - exec	0	0
▼Loop 241 - generate_chunk_kernel.f90:106-106 - exec–	0	0
○Loop 242 - generate_chunk_kernel.f90:106-106 - exec	0	0

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Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code