OV - exec - Function flux_calc_kernel._omp

	Function: flux_calc_kernel._omp_fn.0	Module: exec	Source: flux_calc_kernel.f90:49-60	Coverage: 2.61%

/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/flux_calc_kernel.f90: 49 - 60

--------------------------------------------------------------------------------

49:     !$OMP PARALLEL

50:

51:     ! Note that the loops calculate one extra flux than required, but this

52:     ! allows loop fusion that improves performance

53:     !$OMP DO

54:     DO k=y_min,y_max+1

55:     !$OMP SIMD

56:       DO j=x_min,x_max+1

57:         vol_flux_x(j,k)=0.25_8*dt*xarea(j,k)                  &

58:           *(xvel0(j,k)+xvel0(j,k+1)+xvel1(j,k)+xvel1(j,k+1))

59:         vol_flux_y(j,k)=0.25_8*dt*yarea(j,k)                  &

60:           *(yvel0(j,k)+yvel0(j+1,k)+yvel1(j,k)+yvel1(j+1,k))

0x425960 STP	X29, X30, [SP, #880]!

0x425964 ADD	X29, SP, #0

0x425968 STP	X19, X20, [SP, #16]

0x42596c ORR	X19, XZR, X0

0x425970 LDR	X0, [X0, #16]

0x425974 STP	X21, X22, [SP, #32]

0x425978 STP	X23, X24, [SP, #48]

0x42597c STP	X25, X26, [SP, #64]

0x425980 STP	X27, X28, [SP, #80]

0x425984 LDR	W28, [X0]

0x425988 BL	401b60

0x42598c ORR	W21, WZR, W0

0x425990 BL	401ad0

0x425994 LDR	X1, [X19, #24]

0x425998 ORR	W16, WZR, W0

0x42599c LDP	X26, X27, [X19, #104]

0x4259a0 LDP	X23, X13, [X19, #120]

0x4259a4 LDP	X11, X12, [X19, #136]

0x4259a8 LDP	X9, X5, [X19, #152]

0x4259ac LDP	X8, X4, [X19, #168]

0x4259b0 LDP	X10, X2, [X19, #184]

0x4259b4 LDP	X22, X7, [X19, #200]

0x4259b8 LDR	W3, [X1]

0x4259bc LDR	X6, [X19, #224]

0x4259c0 ADD	W14, W3, #2

0x4259c4 SUB	W15, W14, W28

0x4259c8 SDIV	W18, W15, W21

0x4259cc MSUB	W24, W18, W21, W15

0x4259d0 LDR	X21, [X19, #216]

0x4259d4 CMP	W0, W24

0x4259d8 B.LT	425c00

(227) 0x4259dc MADD	W17, W18, W16, W24

(227) 0x4259e0 ADD	W30, W18, W17

(227) 0x4259e4 CMP	W17, W30

(227) 0x4259e8 B.GE	425be4

(227) 0x4259ec ADD	W16, W28, W17

(227) 0x4259f0 UBFM	X25, X9, #61, #60

(227) 0x4259f4 SUB	X14, XZR, X9,LSL #3

(227) 0x4259f8 SBFM	X0, X16, #0, #31

(227) 0x4259fc LDP	X18, X15, [X19]

(227) 0x425a00 UBFM	X24, X8, #61, #60

(227) 0x425a04 SUB	X3, XZR, X8,LSL #3

(227) 0x425a08 ADD	W28, W28, W30

(227) 0x425a0c MOVZ	W30, #0

(227) 0x425a10 MADD	X1, X0, X25, X25

(227) 0x425a14 PTRUE	P0.B, ALL

(227) 0x425a18 FDUP	Z2.D, #80

(227) 0x425a1c STR	X19, [SP, #136]

(227) 0x425a20 MADD	X1, X14, X0, X1

(227) 0x425a24 LDR	W18, [X18]

(227) 0x425a28 LDR	W17, [X15]

(227) 0x425a2c STR	X1, [SP, #112]

(227) 0x425a30 UBFM	X1, X11, #61, #60

(227) 0x425a34 LDR	X14, [X19, #40]

(227) 0x425a38 STR	X1, [SP, #104]

(227) 0x425a3c MADD	X1, X0, X24, X24

(227) 0x425a40 LDR	X15, [X19, #48]

(227) 0x425a44 ADD	W17, W17, #2

(227) 0x425a48 MADD	X3, X3, X0, X1

(227) 0x425a4c SBFM	X1, X18, #0, #31

(227) 0x425a50 ADD	X12, X12, X1

(227) 0x425a54 ADD	X5, X5, X1

(227) 0x425a58 ADD	X2, X2, X1

(227) 0x425a5c ADD	X6, X6, X1

(227) 0x425a60 MADD	X11, X0, X11, X12

(227) 0x425a64 STR	X3, [SP, #120]

(227) 0x425a68 ADD	X3, X27, X1

(227) 0x425a6c MADD	X9, X0, X9, X5

(227) 0x425a70 LDP	X12, X5, [X19, #72]

(227) 0x425a74 UBFM	X27, X26, #61, #60

(227) 0x425a78 MADD	X3, X0, X26, X3

(227) 0x425a7c UBFM	X26, X10, #61, #60

(227) 0x425a80 ADD	X4, X4, X1

(227) 0x425a84 MADD	X10, X0, X10, X2

(227) 0x425a88 ADD	X7, X7, X1

(227) 0x425a8c ADD	X13, X13, X1

(227) 0x425a90 MADD	X6, X0, X21, X6

(227) 0x425a94 UBFM	X21, X21, #61, #60

(227) 0x425a98 ADD	X11, X14, X11,LSL #3

(227) 0x425a9c LDR	X1, [X19, #88]

(227) 0x425aa0 ADD	X10, X15, X10,LSL #3

(227) 0x425aa4 LDP	X14, X15, [X19, #56]

(227) 0x425aa8 ADD	X6, X5, X6,LSL #3

(227) 0x425aac MADD	X2, X0, X23, X13

(227) 0x425ab0 MADD	X8, X0, X8, X4

(227) 0x425ab4 SUB	W4, W17, W18

(227) 0x425ab8 WHILELO	P2.D, XZR, X4

(227) 0x425abc LDR	X5, [X19, #32]

(227) 0x425ac0 MADD	X7, X0, X22, X7

(227) 0x425ac4 UBFM	X0, X23, #61, #60

(227) 0x425ac8 ADD	X9, X14, X9,LSL #3

(227) 0x425acc UBFM	X22, X22, #61, #60

(227) 0x425ad0 MOVZ	W23, #1

(227) 0x425ad4 LDR	X19, [X19, #96]

(227) 0x425ad8 ADD	X8, X12, X8,LSL #3

(227) 0x425adc STR	X0, [SP, #128]

(227) 0x425ae0 ADD	X7, X15, X7,LSL #3

(227) 0x425ae4 CNTD	X0, ALL

(227) 0x425ae8 ADD	X3, X1, X3,LSL #3

(227) 0x425aec ADD	X2, X19, X2,LSL #3

(227) 0x425af0 LDR	X19, [SP, #128]

(227) 0x425af4 HINT	#0

(227) 0x425af8 HINT	#0

(227) 0x425afc HINT	#0

  (228) 0x425b00 ADD	W16, W16, #1

  (228) 0x425b04 CMP	W18, W17

  (228) 0x425b08 B.GE	425ba0

  (228) 0x425b0c LDR	X14, [SP, #112]

  (228) 0x425b10 ADD	X13, X7, #8

  (228) 0x425b14 ADD	X12, X6, #8

  (228) 0x425b18 ORR	P1.B, P2/Z, P2.B, P2.B

  (228) 0x425b1c LDR	X1, [SP, #120]

  (228) 0x425b20 ADD	X15, X9, X14

  (228) 0x425b24 ADD	X14, X8, X1

  (228) 0x425b28 MOVZ	X1, #0

    (229) 0x425b2c LD1D	{Z3.D}, P1/Z, [X9, X1,LSL #3]

    (229) 0x425b30 LD1D	{Z0.D}, P1/Z, [X15, X1,LSL #3]

    (229) 0x425b34 LD1D	{Z1.D}, P1/Z, [X8, X1,LSL #3]

    (229) 0x425b38 LD1D	{Z5.D}, P1/Z, [X14, X1,LSL #3]

    (229) 0x425b3c LD1D	{Z18.D}, P1/Z, [X11, X1,LSL #3]

    (229) 0x425b40 LD1RD	{Z7.D}, P0/Z, [X5]

    (229) 0x425b44 FADD	Z4.D, Z0.D, Z3.D

    (229) 0x425b48 FMUL	Z17.D, Z7.D, Z2.D

    (229) 0x425b4c FADD	Z6.D, Z4.D, Z1.D

    (229) 0x425b50 FMUL	Z19.D, Z17.D, Z18.D

    (229) 0x425b54 FADD	Z16.D, Z6.D, Z5.D

    (229) 0x425b58 FMUL	Z20.D, Z16.D, Z19.D

    (229) 0x425b5c ST1D	{Z20.D}, P1, [X3, X1,LSL #3]

    (229) 0x425b60 LD1D	{Z21.D}, P1/Z, [X7, X1,LSL #3]

    (229) 0x425b64 LD1D	{Z22.D}, P1/Z, [X13, X1,LSL #3]

    (229) 0x425b68 LD1D	{Z23.D}, P1/Z, [X6, X1,LSL #3]

    (229) 0x425b6c LD1D	{Z25.D}, P1/Z, [X12, X1,LSL #3]

    (229) 0x425b70 LD1D	{Z30.D}, P1/Z, [X10, X1,LSL #3]

    (229) 0x425b74 LD1RD	{Z27.D}, P0/Z, [X5]

    (229) 0x425b78 FADD	Z24.D, Z21.D, Z22.D

    (229) 0x425b7c FMUL	Z29.D, Z27.D, Z2.D

    (229) 0x425b80 FADD	Z26.D, Z24.D, Z23.D

    (229) 0x425b84 FMUL	Z31.D, Z29.D, Z30.D

    (229) 0x425b88 FADD	Z28.D, Z26.D, Z25.D

    (229) 0x425b8c FMUL	Z3.D, Z28.D, Z31.D

    (229) 0x425b90 ST1D	{Z3.D}, P1, [X2, X1,LSL #3]

    (229) 0x425b94 ADD	X1, X1, X0

    (229) 0x425b98 WHILELO	P1.D, X1, X4

    (229) 0x425b9c B.NE	425b2c

  (228) 0x425ba0 LDR	X13, [SP, #104]

  (228) 0x425ba4 CMP	W18, W17

  (228) 0x425ba8 ADD	X9, X9, X25

  (228) 0x425bac ADD	X8, X8, X24

  (228) 0x425bb0 ADD	X3, X3, X27

  (228) 0x425bb4 CSEL	W20, W20, W17, #12

  (228) 0x425bb8 ADD	X10, X10, X26

  (228) 0x425bbc ADD	X7, X7, X22

  (228) 0x425bc0 CSEL	W30, W30, W23, #12

  (228) 0x425bc4 ADD	X6, X6, X21

  (228) 0x425bc8 ADD	X2, X2, X19

  (228) 0x425bcc ADD	X11, X11, X13

  (228) 0x425bd0 CMP	W28, W16

  (228) 0x425bd4 B.GT	425b00

(227) 0x425bd8 LDR	X25, [SP, #136]

(227) 0x425bdc CBZ	W30, 425be4

0x425be0 STR	W20, [X25, #232]

(227) 0x425be4 LDP	X19, X20, [SP, #16]

(227) 0x425be8 LDP	X21, X22, [SP, #32]

(227) 0x425bec LDP	X23, X24, [SP, #48]

(227) 0x425bf0 LDP	X25, X26, [SP, #64]

(227) 0x425bf4 LDP	X27, X28, [SP, #80]

(227) 0x425bf8 LDP	X29, X30, [SP], #144

(227) 0x425bfc RET

(227) 0x425c00 ADD	W18, W18, #1

(227) 0x425c04 MOVZ	W24, #0

(227) 0x425c08 B	4259dc

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	flux_calc_kernel	flux_calc_kernel.f90:67	exec
○	flux_calc	flux_calc.f90:41	exec
○	hydro	hydro.f90:62	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	flux_calc_kernel.f90:49-60
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/flux_calc_kernel.f90:49-60.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 6.83 to 0.85 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 6.83 to 1.00 cycles (6.83x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 152 bytes. The binary function is storing 100 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	6.83	6.50	6.67	3.50	3.50
cycles	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	6.83	6.50	6.67	3.50	3.50

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	4.00
Overall L1	6.83

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.83 cycles. At this rate:

23% of peak load performance is reached (22.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (14.63 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 425960

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #880]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W28, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 401b60 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 401ad0 <@plt_start@+0x320>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W16, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDP X26, X27, [X19, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X13, [X19, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X11, X12, [X19, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X9, X5, [X19, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X8, X4, [X19, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X10, X2, [X19, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X7, [X19, #200]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W3, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X19, #224]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W14, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W15, W14, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W18, W15, W21	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W24, W18, W21, W15	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X21, [X19, #216]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W0, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 425c00 <__flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR W20, [X25, #232]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50

Source file and lines	flux_calc_kernel.f90:49-60
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/flux_calc_kernel.f90:49-60.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 6.83 to 1.00 cycles (6.83x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 152 bytes. The binary function is storing 100 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	6.83	6.50	6.67	3.50	3.50
cycles	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	6.83	6.50	6.67	3.50	3.50

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	4.00
Overall L1	6.83

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.83 cycles. At this rate:

23% of peak load performance is reached (22.24 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (14.63 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 425960

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #880]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W28, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 401b60 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W21, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 401ad0 <@plt_start@+0x320>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W16, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDP X26, X27, [X19, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X13, [X19, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X11, X12, [X19, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X9, X5, [X19, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X8, X4, [X19, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X10, X2, [X19, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X22, X7, [X19, #200]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W3, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X6, [X19, #224]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W14, W3, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W15, W14, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W18, W15, W21	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W24, W18, W21, W15	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X21, [X19, #216]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W0, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 425c00 <__flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0+0x2a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR W20, [X25, #232]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50

Name	Coverage (%)	Time (s)
▼flux_calc_kernel._omp_fn.0–	2.61	0.55
▼Loop 227 - flux_calc_kernel.f90:49-60 - exec–	0	0
▼Loop 228 - flux_calc_kernel.f90:58-60 - exec–	0	0
○Loop 229 - flux_calc_kernel.f90:58-60 - exec	2.61	0.55

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code