OV - exec - Function field_summary_kernel._omp

	Function: field_summary_kernel._omp_fn.0	Module: exec	Source: field_summary_kernel.f90:54-71	Coverage: 0.47%

/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/field_summary_kernel.f90: 54 - 71

--------------------------------------------------------------------------------

54:     !$OMP PARALLEL

55:     !$OMP DO PRIVATE(vsqrd,cell_vol,cell_mass) REDUCTION(+ : vol,mass,press,ie,ke)

56:     DO k=y_min,y_max

57:     !$OMP SIMD

58:       DO j=x_min,x_max

59:         vsqrd=0.0

60:         DO kv=k,k+1

61:           DO jv=j,j+1

62:             vsqrd=vsqrd+0.25*(xvel0(jv,kv)**2+yvel0(jv,kv)**2)

63:           ENDDO

64:         ENDDO

65:         cell_vol=volume(j,k)

66:         cell_mass=cell_vol*density0(j,k)

67:         vol=vol+cell_vol

68:         mass=mass+cell_mass

69:         ie=ie+cell_mass*energy0(j,k)

70:         ke=ke+cell_mass*0.5*vsqrd

71:         press=press+cell_vol*pressure(j,k)

0x424f60 STP	X29, X30, [SP, #896]!

0x424f64 ADD	X29, SP, #0

0x424f68 STP	X19, X20, [SP, #16]

0x424f6c ORR	X19, XZR, X0

0x424f70 LDR	X0, [X0, #16]

0x424f74 STP	X21, X22, [SP, #32]

0x424f78 STP	D8, D9, [SP, #80]

0x424f7c LDR	W21, [X0]

0x424f80 STP	D10, D11, [SP, #96]

0x424f84 STR	D12, [SP, #112]

0x424f88 BL	401b60

0x424f8c ORR	W20, WZR, W0

0x424f90 BL	401ad0

0x424f94 LDR	X1, [X19, #24]

0x424f98 ORR	W15, WZR, W0

0x424f9c LDR	W2, [X1]

0x424fa0 ADD	W3, W2, #1

0x424fa4 SUB	W4, W3, W21

0x424fa8 SDIV	W5, W4, W20

0x424fac MSUB	W6, W5, W20, W4

0x424fb0 CMP	W0, W6

0x424fb4 B.LT	4253cc

0x424fb8 MADD	W7, W5, W15, W6

0x424fbc ADD	W8, W5, W7

0x424fc0 CMP	W7, W8

0x424fc4 B.GE	42534c

0x424fc8 LDP	X11, X9, [X19, #120]

0x424fcc ADD	W15, W21, W7

0x424fd0 ADD	W18, W21, W8

0x424fd4 SBFM	X2, X15, #0, #31

0x424fd8 MOVI	D8, #0

0x424fdc FMOV	D2, #0.2500000

0x424fe0 FMOV	D18, #0.5000000

0x424fe4 MOVZ	W1, #0

0x424fe8 LDP	X14, X6, [X19]

0x424fec MADD	X21, X2, X11, X9

0x424ff0 FMOV	D11, D8

0x424ff4 FMOV	D12, D8

0x424ff8 LDP	X13, X12, [X19, #160]

0x424ffc FMOV	D9, D8

0x425000 FMOV	D10, D8

0x425004 FMOV	D17, D8

0x425008 LDP	X16, X4, [X19, #176]

0x42500c UBFM	X20, X12, #61, #60

0x425010 STP	X23, X24, [SP, #48]

0x425014 UBFM	X23, X11, #61, #60

0x425018 MADD	X12, X12, X2, X16

0x42501c UBFM	X17, X4, #61, #60

0x425020 LDR	X30, [X19, #40]

0x425024 MADD	X8, X2, X4, X4

0x425028 LDP	X10, X24, [X19, #136]

0x42502c STP	X25, X26, [SP, #64]

0x425030 MOVZ	W25, #1

0x425034 ADD	X11, X30, X21,LSL #3

0x425038 UBFM	X22, X10, #61, #60

0x42503c MADD	X10, X2, X10, X24

0x425040 LDR	W16, [X14]

0x425044 LDR	X14, [X19, #48]

0x425048 LDR	X30, [X19, #152]

0x42504c ADD	W24, W16, W25

0x425050 LDR	X5, [X19, #192]

0x425054 ADD	X10, X14, X10,LSL #3

0x425058 LDR	X3, [X19, #200]

0x42505c MADD	X9, X2, X30, X13

0x425060 UBFM	X21, X30, #61, #60

0x425064 LDR	X14, [X19, #64]

0x425068 MADD	X4, X4, X2, X5

0x42506c ADD	X8, X8, X5

0x425070 LDR	X13, [X19, #208]

0x425074 MADD	X7, X2, X3, X3

0x425078 UBFM	X0, X3, #61, #60

0x42507c LDR	X5, [X19, #56]

0x425080 ADD	X8, X14, X8,LSL #3

0x425084 MADD	X3, X3, X2, X13

0x425088 ADD	X7, X7, X13

0x42508c LDR	W13, [X6]

0x425090 ADD	X6, X14, X4,LSL #3

0x425094 LDR	X2, [X19, #32]

0x425098 ADD	X9, X5, X9,LSL #3

0x42509c LDR	X4, [X19, #72]

0x4250a0 ADD	W30, W13, W25

0x4250a4 ADD	X12, X2, X12,LSL #3

0x4250a8 ADD	X7, X4, X7,LSL #3

0x4250ac ADD	X5, X4, X3,LSL #3

  (221) 0x4250b0 ADD	W15, W15, #1

  (221) 0x4250b4 CMP	W16, W13

  (221) 0x4250b8 B.GT	42533c

(222) 0x4250bc SBFM	X26, X16, #0, #31

(222) 0x4250c0 SBFM	X2, X24, #0, #31

(222) 0x4250c4 SUB	W14, W13, W16

(222) 0x4250c8 ADD	X1, X26, #1

(222) 0x4250cc LDR	D1, [X5, X26,LSL #3]

(222) 0x4250d0 ADD	X3, X2, #1

(222) 0x4250d4 AND	W4, W14, #0

(222) 0x4250d8 LDR	D0, [X6, X26,LSL #3]

(222) 0x4250dc LDR	D4, [X5, X2,LSL #3]

(222) 0x4250e0 FMUL	D5, D1, D1

(222) 0x4250e4 LDR	D19, [X6, X2,LSL #3]

(222) 0x4250e8 LDR	D3, [X7, X26,LSL #3]

(222) 0x4250ec FMUL	D6, D4, D4

(222) 0x4250f0 LDR	D20, [X8, X26,LSL #3]

(222) 0x4250f4 FMADD	D21, D0, D0, D5

(222) 0x4250f8 LDR	D22, [X7, X2,LSL #3]

(222) 0x4250fc FMUL	D7, D3, D3

(222) 0x425100 LDR	D16, [X12, X26,LSL #3]

(222) 0x425104 FMADD	D23, D19, D19, D6

(222) 0x425108 FMADD	D24, D21, D2, D17

(222) 0x42510c LDR	D25, [X11, X26,LSL #3]

(222) 0x425110 LDR	D26, [X8, X2,LSL #3]

(222) 0x425114 FMUL	D27, D22, D22

(222) 0x425118 FMADD	D28, D20, D20, D7

(222) 0x42511c LDR	D29, [X10, X26,LSL #3]

(222) 0x425120 FADD	D10, D10, D16

(222) 0x425124 FMADD	D30, D23, D2, D24

(222) 0x425128 FMUL	D31, D16, D25

(222) 0x42512c LDR	D1, [X9, X26,LSL #3]

(222) 0x425130 FMADD	D5, D26, D26, D27

(222) 0x425134 FMADD	D0, D28, D2, D30

(222) 0x425138 FMADD	D11, D31, D29, D11

(222) 0x42513c FMUL	D4, D31, D18

(222) 0x425140 FMADD	D12, D16, D1, D12

(222) 0x425144 FADD	D9, D9, D31

(222) 0x425148 FMADD	D19, D5, D2, D0

(222) 0x42514c FMADD	D8, D19, D4, D8

(222) 0x425150 CMP	W13, W1

(222) 0x425154 B.LT	4252f8

(222) 0x425158 CBZ	W4, 4251e8

0x42515c LDR	D3, [X5, X1,LSL #3]

0x425160 LDR	D20, [X6, X1,LSL #3]

0x425164 LDR	D6, [X5, X3,LSL #3]

0x425168 FMUL	D21, D3, D3

0x42516c LDR	D22, [X6, X3,LSL #3]

0x425170 LDR	D7, [X7, X1,LSL #3]

0x425174 FMUL	D23, D6, D6

0x425178 LDR	D24, [X8, X1,LSL #3]

0x42517c FMADD	D25, D20, D20, D21

0x425180 LDR	D26, [X7, X3,LSL #3]

0x425184 FMUL	D27, D7, D7

0x425188 LDR	D16, [X12, X1,LSL #3]

0x42518c FMADD	D28, D22, D22, D23

0x425190 FMADD	D29, D25, D2, D17

0x425194 LDR	D30, [X11, X1,LSL #3]

0x425198 LDR	D31, [X8, X3,LSL #3]

0x42519c FMUL	D5, D26, D26

0x4251a0 ADD	X3, X3, #1

0x4251a4 FMADD	D4, D24, D24, D27

0x4251a8 LDR	D19, [X10, X1,LSL #3]

0x4251ac FADD	D10, D10, D16

0x4251b0 FMADD	D0, D28, D2, D29

0x4251b4 FMUL	D1, D16, D30

0x4251b8 LDR	D20, [X9, X1,LSL #3]

0x4251bc ADD	X1, X1, #1

0x4251c0 FMADD	D3, D31, D31, D5

0x4251c4 FMADD	D6, D4, D2, D0

0x4251c8 FMADD	D11, D1, D19, D11

0x4251cc FMUL	D21, D1, D18

0x4251d0 FMADD	D12, D16, D20, D12

0x4251d4 FADD	D9, D9, D1

0x4251d8 FMADD	D22, D3, D2, D6

0x4251dc FMADD	D8, D22, D21, D8

0x4251e0 CMP	W13, W1

0x4251e4 B.LT	4252f8

  (223) 0x4251e8 LDR	D7, [X5, X1,LSL #3]

  (223) 0x4251ec ADD	X26, X1, #1

  (223) 0x4251f0 ADD	X2, X3, #1

  (223) 0x4251f4 LDR	D23, [X6, X1,LSL #3]

  (223) 0x4251f8 LDR	D24, [X5, X3,LSL #3]

  (223) 0x4251fc FMUL	D26, D7, D7

  (223) 0x425200 LDR	D25, [X5, X26,LSL #3]

  (223) 0x425204 LDR	D27, [X6, X3,LSL #3]

  (223) 0x425208 LDR	D16, [X7, X1,LSL #3]

  (223) 0x42520c FMUL	D28, D24, D24

  (223) 0x425210 FMADD	D29, D23, D23, D26

  (223) 0x425214 LDR	D30, [X6, X26,LSL #3]

  (223) 0x425218 FMUL	D31, D25, D25

  (223) 0x42521c LDR	D20, [X5, X2,LSL #3]

  (223) 0x425220 FMADD	D19, D27, D27, D28

  (223) 0x425224 LDR	D4, [X8, X1,LSL #3]

  (223) 0x425228 FMADD	D0, D29, D2, D17

  (223) 0x42522c FMUL	D21, D16, D16

  (223) 0x425230 LDR	D3, [X7, X3,LSL #3]

  (223) 0x425234 FMADD	D1, D30, D30, D31

  (223) 0x425238 LDR	D5, [X6, X2,LSL #3]

  (223) 0x42523c FMUL	D22, D20, D20

  (223) 0x425240 FMADD	D23, D19, D2, D0

  (223) 0x425244 LDR	D6, [X7, X26,LSL #3]

  (223) 0x425248 FMADD	D24, D4, D4, D21

  (223) 0x42524c FMADD	D25, D1, D2, D17

  (223) 0x425250 LDR	D26, [X12, X1,LSL #3]

  (223) 0x425254 FMUL	D27, D3, D3

  (223) 0x425258 LDR	D28, [X11, X1,LSL #3]

  (223) 0x42525c FMADD	D7, D5, D5, D22

  (223) 0x425260 FMADD	D29, D24, D2, D23

  (223) 0x425264 LDR	D30, [X8, X3,LSL #3]

  (223) 0x425268 FMUL	D16, D6, D6

  (223) 0x42526c ADD	X3, X3, #2

  (223) 0x425270 LDR	D31, [X8, X26,LSL #3]

  (223) 0x425274 FADD	D10, D10, D26

  (223) 0x425278 FMADD	D4, D7, D2, D25

  (223) 0x42527c LDR	D0, [X7, X2,LSL #3]

  (223) 0x425280 FMUL	D3, D26, D28

  (223) 0x425284 LDR	D20, [X12, X26,LSL #3]

  (223) 0x425288 FMADD	D19, D30, D30, D27

  (223) 0x42528c LDR	D5, [X11, X26,LSL #3]

  (223) 0x425290 FMADD	D1, D31, D31, D16

  (223) 0x425294 LDR	D23, [X8, X2,LSL #3]

  (223) 0x425298 FMUL	D6, D0, D0

  (223) 0x42529c FMUL	D22, D3, D18

  (223) 0x4252a0 FMADD	D24, D19, D2, D29

  (223) 0x4252a4 LDR	D21, [X10, X1,LSL #3]

  (223) 0x4252a8 FADD	D9, D9, D3

  (223) 0x4252ac FADD	D10, D10, D20

  (223) 0x4252b0 FMADD	D25, D1, D2, D4

  (223) 0x4252b4 FMUL	D27, D20, D5

  (223) 0x4252b8 LDR	D28, [X9, X1,LSL #3]

  (223) 0x4252bc ADD	X1, X1, #2

  (223) 0x4252c0 FMADD	D29, D23, D23, D6

  (223) 0x4252c4 LDR	D30, [X10, X26,LSL #3]

  (223) 0x4252c8 FMADD	D16, D24, D22, D8

  (223) 0x4252cc LDR	D7, [X9, X26,LSL #3]

  (223) 0x4252d0 FMADD	D11, D3, D21, D11

  (223) 0x4252d4 FMADD	D12, D26, D28, D12

  (223) 0x4252d8 FMADD	D31, D29, D2, D25

  (223) 0x4252dc FMUL	D8, D27, D18

  (223) 0x4252e0 FADD	D9, D9, D27

  (223) 0x4252e4 FMADD	D11, D27, D30, D11

  (223) 0x4252e8 FMADD	D12, D20, D7, D12

  (223) 0x4252ec FMADD	D8, D31, D8, D16

  (223) 0x4252f0 CMP	W13, W1

  (223) 0x4252f4 B.GE	4251e8

(222) 0x4252f8 ORR	W26, WZR, W30

(222) 0x4252fc MOVZ	W1, #1

  (221) 0x425300 ADD	X6, X6, X17

  (221) 0x425304 ADD	X5, X5, X0

  (221) 0x425308 ADD	X8, X8, X17

  (221) 0x42530c ADD	X7, X7, X0

  (221) 0x425310 ADD	X12, X12, X20

  (221) 0x425314 ADD	X11, X11, X23

  (221) 0x425318 ADD	X10, X10, X22

  (221) 0x42531c ADD	X9, X9, X21

  (221) 0x425320 CMP	W18, W15

  (221) 0x425324 B.GT	4250b0

0x425328 CBZ	W1, 4253d8

0x42532c LDP	X23, X24, [SP, #48]

0x425330 STR	W26, [X19, #216]

0x425334 LDP	X25, X26, [SP, #64]

0x425338 B	425360

  (221) 0x42533c CMP	W16, W30

  (221) 0x425340 CSEL	W26, W26, W16, #1

  (221) 0x425344 CSEL	W1, W1, W25, #1

  (221) 0x425348 B	425300

0x42534c MOVI	D8, #0

0x425350 FMOV	D11, D8

0x425354 FMOV	D12, D8

0x425358 FMOV	D9, D8

0x42535c FMOV	D10, D8

0x425360 BL	4018f0

0x425364 LDP	X14, X4, [X19, #80]

0x425368 LDP	X3, X0, [X19, #96]

0x42536c LDR	D2, [X14]

0x425370 LDR	X5, [X19, #112]

0x425374 FADD	D17, D2, D10

0x425378 STR	D17, [X14]

0x42537c LDR	D18, [X4]

0x425380 FADD	D26, D18, D9

0x425384 STR	D26, [X4]

0x425388 LDR	D10, [X5]

0x42538c FADD	D4, D10, D12

0x425390 STR	D4, [X5]

0x425394 LDR	D0, [X3]

0x425398 FADD	D3, D0, D11

0x42539c STR	D3, [X3]

0x4253a0 LDR	D20, [X0]

0x4253a4 FADD	D19, D20, D8

0x4253a8 STR	D19, [X0]

0x4253ac BL	401940

0x4253b0 LDP	X19, X20, [SP, #16]

0x4253b4 LDP	X21, X22, [SP, #32]

0x4253b8 LDP	D8, D9, [SP, #80]

0x4253bc LDP	D10, D11, [SP, #96]

0x4253c0 LDR	D12, [SP, #112]

0x4253c4 LDP	X29, X30, [SP], #128

0x4253c8 B	401b40

0x4253cc ADD	W5, W5, #1

0x4253d0 MOVZ	W6, #0

0x4253d4 B	424fb8

0x4253d8 LDP	X23, X24, [SP, #48]

0x4253dc LDP	X25, X26, [SP, #64]

0x4253e0 B	425360

Coverage (%)	Name	Source Location	Module
►80.00+	GOMP_parallel		libgomp.so.1.0.0
○	field_summary_kernel	field_summary_kernel.f90:54	exec
○	field_summary	field_summary.f90:84	exec
○	hydro	hydro.f90:74	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec
►10.00+	GOMP_parallel		libgomp.so.1.0.0
○	field_summary_kernel	field_summary_kernel.f90:54	exec
○	field_summary	field_summary.f90:84	exec
○	hydro	hydro.f90:88	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec
►10.00+	GOMP_parallel		libgomp.so.1.0.0
○	field_summary_kernel	field_summary_kernel.f90:54	exec
○	field_summary	field_summary.f90:84	exec
○	start	start.f90:145	exec
○	initialise	initialise.f90:141	exec
○	main	clover_leaf.f90:72	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	field_summary_kernel.f90:54-71
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/field_summary_kernel.f90:54-71.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 21.67 to 9.33 cycles (2.32x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 21.67 to 4.21 cycles (5.15x speedup).

Details

9% of VPU instructions are used in vector version (process two or more data elements in vector registers):

10% of VPU loads are used in vector version.
25% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 21.67 to 2.00 cycles (10.83x speedup).

FMA

Detected 11 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your function (in the source code) and the binary function

The binary function is composed of 35 FP arithmetical operations:

18: addition or subtraction (11 inside FMA instructions)
17: multiply (11 inside FMA instructions)

The binary function is loading 520 bytes. The binary function is storing 164 bytes.

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	162
loop length	648
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

20.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.00	6.00	13.25	13.25	13.25	13.25	11.25	11.25	11.25	11.25	21.67	21.67	21.67	3.00	3.00
cycles	6.00	6.00	13.25	13.25	13.25	13.25	11.25	11.25	11.25	11.25	21.67	21.67	21.67	3.00	3.00

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	20.25
Overall L1	21.67

Vectorization ratios

all	9%
load	10%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 21.67 cycles. At this rate:

25% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (7.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 424f60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #896]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP D8, D9, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR W21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP D10, D11, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR D12, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 401b60 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 401ad0 <@plt_start@+0x320>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W15, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W2, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W3, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W4, W3, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W5, W4, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W6, W5, W20, W4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4253cc <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x46c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W7, W5, W15, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W8, W5, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W7, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 42534c <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x3ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X9, [X19, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W15, W21, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W18, W21, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X2, X15, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVI D8, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D2, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D18, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X14, X6, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X21, X2, X11, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
FMOV D11, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D12, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDP X13, X12, [X19, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
FMOV D9, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D10, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D17, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDP X16, X4, [X19, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
UBFM X20, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X23, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X12, X12, X2, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X17, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X30, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X8, X2, X4, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDP X10, X24, [X19, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X30, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X22, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X10, X2, X10, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR W16, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X19, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X19, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W24, W16, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [X19, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X14, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X3, [X19, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X9, X2, X30, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X21, X30, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X19, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X4, X4, X2, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X8, X8, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [X19, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X7, X2, X3, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X0, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [X19, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X14, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X3, X3, X2, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X7, X7, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W13, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, X14, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X5, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X4, [X19, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W30, W13, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X2, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X4, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X4, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D3, [X5, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D20, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D6, [X5, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D21, D3, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
LDR D22, [X6, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D7, [X7, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D23, D6, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
LDR D24, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMADD D25, D20, D20, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
LDR D26, [X7, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D27, D7, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
LDR D16, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMADD D28, D22, D22, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMADD D29, D25, D2, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
LDR D30, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D31, [X8, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D5, D26, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMADD D4, D24, D24, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
LDR D19, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D10, D10, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMADD D0, D28, D2, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMUL D1, D16, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
LDR D20, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMADD D3, D31, D31, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMADD D6, D4, D2, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMADD D11, D1, D19, D11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMUL D21, D1, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMADD D12, D16, D20, D12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FADD D9, D9, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMADD D22, D3, D2, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMADD D8, D22, D21, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
CMP W13, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4252f8 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x398>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W1, 4253d8 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x478>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR W26, [X19, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 425360 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVI D8, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D11, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D12, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D9, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D10, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
BL 4018f0 <@plt_start@+0x140>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X14, X4, [X19, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X3, X0, [X19, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR D2, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X5, [X19, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FADD D17, D2, D10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D17, [X14]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D18, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D26, D18, D9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D26, [X4]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D10, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D4, D10, D12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D4, [X5]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D0, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D3, D0, D11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D3, [X3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D19, D20, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D19, [X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 401940 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP D8, D9, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D10, D11, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D12, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X29, X30, [SP], #128	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 401b40 <@plt_start@+0x390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W5, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 424fb8 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 425360 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	field_summary_kernel.f90:54-71
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/field_summary_kernel.f90:54-71.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 21.67 to 9.33 cycles (2.32x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

9% of VPU instructions are used in vector version (process two or more data elements in vector registers):

10% of VPU loads are used in vector version.
25% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 21.67 to 2.00 cycles (10.83x speedup).

FMA

Detected 11 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your function (in the source code) and the binary function

The binary function is composed of 35 FP arithmetical operations:

18: addition or subtraction (11 inside FMA instructions)
17: multiply (11 inside FMA instructions)

The binary function is loading 520 bytes. The binary function is storing 164 bytes.

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	162
loop length	648
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

20.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.00	6.00	13.25	13.25	13.25	13.25	11.25	11.25	11.25	11.25	21.67	21.67	21.67	3.00	3.00
cycles	6.00	6.00	13.25	13.25	13.25	13.25	11.25	11.25	11.25	11.25	21.67	21.67	21.67	3.00	3.00

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	20.25
Overall L1	21.67

Vectorization ratios

all	9%
load	10%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 21.67 cycles. At this rate:

25% of peak load performance is reached (24.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (7.57 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 424f60

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #896]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP D8, D9, [SP, #80]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR W21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP D10, D11, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
STR D12, [SP, #112]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 401b60 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 401ad0 <@plt_start@+0x320>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W15, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W2, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W3, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W4, W3, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W5, W4, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W6, W5, W20, W4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4253cc <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x46c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W7, W5, W15, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W8, W5, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W7, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 42534c <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x3ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X11, X9, [X19, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W15, W21, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W18, W21, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X2, X15, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVI D8, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D2, #0.2500000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D18, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X14, X6, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X21, X2, X11, X9	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
FMOV D11, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D12, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDP X13, X12, [X19, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
FMOV D9, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D10, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D17, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDP X16, X4, [X19, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
UBFM X20, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X23, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X12, X12, X2, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X17, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X30, [X19, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X8, X2, X4, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDP X10, X24, [X19, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X30, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X22, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X10, X2, X10, X24	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR W16, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X19, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X30, [X19, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W24, W16, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [X19, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X14, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X3, [X19, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X9, X2, X30, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X21, X30, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X19, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X4, X4, X2, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X8, X8, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X13, [X19, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X7, X2, X3, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X0, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [X19, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X14, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X3, X3, X2, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X7, X7, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W13, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, X14, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X2, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X5, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X4, [X19, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W30, W13, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X2, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X4, X7,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X4, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D3, [X5, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D20, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D6, [X5, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D21, D3, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
LDR D22, [X6, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D7, [X7, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D23, D6, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
LDR D24, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMADD D25, D20, D20, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
LDR D26, [X7, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D27, D7, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
LDR D16, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMADD D28, D22, D22, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMADD D29, D25, D2, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
LDR D30, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D31, [X8, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FMUL D5, D26, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMADD D4, D24, D24, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
LDR D19, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D10, D10, D16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMADD D0, D28, D2, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMUL D1, D16, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
LDR D20, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMADD D3, D31, D31, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMADD D6, D4, D2, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMADD D11, D1, D19, D11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMUL D21, D1, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FMADD D12, D16, D20, D12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FADD D9, D9, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMADD D22, D3, D2, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
FMADD D8, D22, D21, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25
CMP W13, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4252f8 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x398>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W1, 4253d8 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x478>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR W26, [X19, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 425360 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVI D8, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D11, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D12, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D9, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D10, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
BL 4018f0 <@plt_start@+0x140>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X14, X4, [X19, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X3, X0, [X19, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR D2, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X5, [X19, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FADD D17, D2, D10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D17, [X14]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D18, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D26, D18, D9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D26, [X4]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D10, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D4, D10, D12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D4, [X5]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D0, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D3, D0, D11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D3, [X3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR D20, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D19, D20, D8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D19, [X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
BL 401940 <@plt_start@+0x190>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP D8, D9, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP D10, D11, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D12, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDP X29, X30, [SP], #128	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 401b40 <@plt_start@+0x390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W5, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 424fb8 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 425360 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x400>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼field_summary_kernel._omp_fn.0–	0.47	0.1
▼Loop 222 - field_summary_kernel.f90:57-71 - exec–	0	0
○Loop 223 - field_summary_kernel.f90:62-71 - exec	0.47	0.1
○Loop 221 - field_summary_kernel.f90:57-71 - exec	0	0

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Expensive FP math instructions/calls

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Matching between your function (in the source code) and the binary function

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Vectorization ratios

Cycles and memory resources usage

ASM code