OV - exec - Function calc_dt_kernel._omp

	Function: calc_dt_kernel._omp_fn.0	Module: exec	Source: calc_dt_kernel.f90:89-129	Coverage: 10.19%

/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/calc_dt_kernel.f90: 89 - 129

--------------------------------------------------------------------------------

89:     !$OMP PARALLEL

90:

91:     !$OMP DO PRIVATE(dsx,dsy,cc,dv1,dv2,div,dtct,dtut,dtvt,dtdivt) REDUCTION(MIN : dt_min_val)

92:     DO k=y_min,y_max

93:     !$OMP SIMD

94:       DO j=x_min,x_max

95:

96:         dsx=celldx(j)

97:         dsy=celldy(k)

98:

99:         cc=soundspeed(j,k)*soundspeed(j,k)

100:         cc=cc+2.0_8*viscosity_a(j,k)/density0(j,k)

101:         cc=MAX(SQRT(cc),g_small)

102:

103:         dtct=dtc_safe*MIN(dsx,dsy)/cc

104:

105:         div=0.0

106:

107:         dv1=(xvel0(j  ,k)+xvel0(j  ,k+1))*xarea(j  ,k)

108:         dv2=(xvel0(j+1,k)+xvel0(j+1,k+1))*xarea(j+1,k)

109:

110:         div=div+dv2-dv1

111:

112:         dtut=dtu_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

113:

114:         dv1=(yvel0(j,k  )+yvel0(j+1,k  ))*yarea(j,k  )

115:         dv2=(yvel0(j,k+1)+yvel0(j+1,k+1))*yarea(j,k+1)

116:

117:         div=div+dv2-dv1

118:

119:         dtvt=dtv_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

120:

121:         div=div/(2.0_8*volume(j,k))

122:

123:         IF(div.LT.-g_small)THEN

124:           dtdivt=dtdiv_safe*(-1.0_8/div)

125:         ELSE

126:           dtdivt=g_big

127:         ENDIF

128:

129:         dt_min_val=MIN(dt_min_val,dtct,dtut,dtvt,dtdivt)

0x423a40 STP	X29, X30, [SP, #784]!

0x423a44 ADD	X29, SP, #0

0x423a48 STP	X19, X20, [SP, #16]

0x423a4c ORR	X19, XZR, X0

0x423a50 LDR	X0, [X0, #16]

0x423a54 STP	X21, X22, [SP, #32]

0x423a58 LDR	W21, [X0]

0x423a5c BL	401b60

0x423a60 ORR	W20, WZR, W0

0x423a64 BL	401ad0

0x423a68 LDR	X1, [X19, #24]

0x423a6c LDR	W2, [X1]

0x423a70 ADD	W3, W2, #1

0x423a74 SUB	W4, W3, W21

0x423a78 SDIV	W5, W4, W20

0x423a7c MSUB	W6, W5, W20, W4

0x423a80 CMP	W0, W6

0x423a84 B.LT	423eb4

0x423a88 MADD	W7, W5, W0, W6

0x423a8c ADD	W8, W5, W7

0x423a90 CMP	W7, W8

0x423a94 B.GE	423e58

0x423a98 LDP	X18, X13, [X19]

0x423a9c MOVZ	X10, #32752

0x423aa0 ADD	W12, W21, W8

0x423aa4 ADD	W11, W21, W7

0x423aa8 MOVI	D25, #0

0x423aac FMOV	D26, #1.0000000

0x423ab0 SBFM	X15, X11, #0, #31

0x423ab4 MOVZ	X17, #0

0x423ab8 STP	X23, X24, [SP, #48]

0x423abc MOVZ	X16, #0

0x423ac0 ADD	X0, X15, #1

0x423ac4 LDR	W24, [X18]

0x423ac8 LDP	X22, X20, [X19, #32]

0x423acc LDP	X5, X6, [X19, #48]

0x423ad0 FMOV	D19, X10

0x423ad4 SBFM	X10, X24, #0, #31

0x423ad8 LDR	X23, [X19, #184]

0x423adc STP	X25, X26, [SP, #64]

0x423ae0 MOVZ	W25, #0

0x423ae4 LDR	W13, [X13]

0x423ae8 UBFM	X7, X23, #61, #60

0x423aec STP	X27, X28, [SP, #80]

0x423af0 LDR	X9, [X19, #64]

0x423af4 CMP	W10, W13

0x423af8 CSINC	W2, W10, W13, #12

0x423afc STP	D8, D9, [SP, #96]

0x423b00 LDR	X3, [X19, #192]

0x423b04 ADD	W26, W13, #1

0x423b08 STR	W12, [SP, #124]

0x423b0c STP	W24, W2, [SP, #128]

0x423b10 STR	X22, [SP, #176]

0x423b14 STP	X5, X6, [SP, #184]

0x423b18 MADD	X8, X23, X15, X3

0x423b1c STR	X9, [SP, #200]

0x423b20 LDR	X30, [X19, #72]

0x423b24 LDP	X27, X21, [X19, #128]

0x423b28 LDR	X12, [X19, #120]

0x423b2c LDR	X14, [X19, #144]

0x423b30 LDR	X4, [X19, #200]

0x423b34 STR	X7, [SP, #136]

0x423b38 ADD	X9, X12, X8,LSL #3

0x423b3c LDP	X22, X5, [X19, #208]

0x423b40 LDP	X3, X1, [X19, #224]

0x423b44 UBFM	X11, X4, #61, #60

0x423b48 MADD	X4, X4, X15, X22

0x423b4c UBFM	X2, X5, #61, #60

0x423b50 LDP	X6, X24, [X19, #240]

0x423b54 ADD	X8, X21, X4,LSL #3

0x423b58 MADD	X21, X5, X15, X3

0x423b5c STR	X2, [SP, #144]

0x423b60 UBFM	X2, X1, #61, #60

0x423b64 LDR	X22, [X19, #256]

0x423b68 MADD	X1, X15, X1, X6

0x423b6c STR	X2, [SP, #160]

0x423b70 ADD	X7, X27, X21,LSL #3

0x423b74 LDP	X18, X12, [X19, #296]

0x423b78 MADD	X27, X24, X15, XZR

0x423b7c UBFM	X24, X24, #61, #60

0x423b80 ADD	X4, X22, X10

0x423b84 ADD	X3, X22, #1

0x423b88 STR	X1, [SP, #208]

0x423b8c ADD	X21, X4, X27

0x423b90 ADD	X3, X3, X27

0x423b94 LDR	X27, [X19, #80]

0x423b98 STR	X10, [SP, #168]

0x423b9c MADD	X5, X15, X18, XZR

0x423ba0 MADD	X4, X15, X18, X18

0x423ba4 STR	X11, [SP, #152]

0x423ba8 UBFM	X18, X18, #61, #60

0x423bac LDP	X23, X11, [X19, #280]

0x423bb0 ADD	X21, X27, X21,LSL #3

0x423bb4 LDP	X27, X1, [X19, #264]

0x423bb8 MADD	X6, X27, X15, XZR

0x423bbc UBFM	X22, X27, #61, #60

0x423bc0 MADD	X2, X15, X27, X27

0x423bc4 ADD	X27, X1, X10

0x423bc8 ADD	X1, X1, #1

0x423bcc ADD	X10, X6, X27

0x423bd0 ADD	X6, X6, X1

0x423bd4 ADD	X27, X2, X27

0x423bd8 ADD	X2, X2, X1

0x423bdc LDR	X1, [SP, #168]

0x423be0 ADD	X10, X14, X10,LSL #3

0x423be4 ADD	X6, X14, X6,LSL #3

0x423be8 ADD	X27, X14, X27,LSL #3

0x423bec ADD	X2, X14, X2,LSL #3

0x423bf0 LDR	X14, [X19, #80]

0x423bf4 ADD	X1, X12, X1

0x423bf8 ADD	X12, X12, #1

0x423bfc STR	X10, [SP, #112]

0x423c00 MADD	X10, X15, X23, X23

0x423c04 ADD	X3, X14, X3,LSL #3

0x423c08 ADD	X14, X1, X5

0x423c0c ADD	X1, X4, X1

0x423c10 ADD	X5, X12, X5

0x423c14 ADD	X4, X4, X12

0x423c18 LDR	X12, [X19, #152]

0x423c1c ADD	X10, X10, X11

0x423c20 MADD	X11, X15, X23, X11

0x423c24 UBFM	X23, X23, #61, #60

0x423c28 ADD	X12, X12, X14,LSL #3

0x423c2c LDR	X14, [X19, #176]

0x423c30 STR	X12, [SP, #216]

0x423c34 LDR	X12, [X19, #152]

0x423c38 ADD	X5, X12, X5,LSL #3

0x423c3c ADD	X12, X12, X1,LSL #3

0x423c40 LDR	X1, [SP, #208]

0x423c44 STR	X12, [SP, #224]

0x423c48 LDR	X12, [X19, #152]

0x423c4c ADD	X4, X12, X4,LSL #3

0x423c50 LDR	X12, [X19, #112]

0x423c54 ADD	X12, X12, X1,LSL #3

0x423c58 LDR	X1, [X19, #88]

0x423c5c ADD	X10, X1, X10,LSL #3

0x423c60 ADD	X11, X1, X11,LSL #3

0x423c64 LDR	X1, [X19, #104]

0x423c68 ADD	X14, X1, X14,LSL #3

0x423c6c STR	X14, [SP, #208]

0x423c70 STR	X19, [SP, #232]

0x423c74 LDR	X14, [X19, #96]

0x423c78 LDR	X19, [X19, #168]

0x423c7c ADD	X14, X14, X19,LSL #3

0x423c80 LDR	X19, [SP, #112]

(212) 0x423c84 LDR	W1, [SP, #128]

(212) 0x423c88 CMP	W1, W13

(212) 0x423c8c B.GT	423dd8

(212) 0x423c90 LDR	X1, [SP, #192]

(212) 0x423c94 LDR	D6, [X19, X16]

(212) 0x423c98 LDR	D0, [X27, X16]

(212) 0x423c9c LDR	D21, [X1]

(212) 0x423ca0 LDR	X1, [SP, #168]

(212) 0x423ca4 FADD	D6, D6, D0

(212) 0x423ca8 LDR	D17, [X21]

(212) 0x423cac FADD	D21, D21, D21

(212) 0x423cb0 STR	X1, [SP, #112]

(212) 0x423cb4 LDR	X1, [SP, #200]

(212) 0x423cb8 LDR	D20, [X1]

(212) 0x423cbc LDR	X1, [SP, #176]

(212) 0x423cc0 FADD	D20, D20, D20

(212) 0x423cc4 LDR	D18, [X1]

(212) 0x423cc8 LDR	X1, [SP, #208]

(212) 0x423ccc FNEG	D22, D18

(212) 0x423cd0 LDR	D24, [X1, X15,LSL #3]

(212) 0x423cd4 LDR	X15, [SP, #184]

(212) 0x423cd8 LDR	X1, [SP, #216]

(212) 0x423cdc LDR	D23, [X15]

(212) 0x423ce0 LDR	X15, [SP, #224]

(212) 0x423ce4 LDR	D16, [X1, X17]

(212) 0x423ce8 LDR	X1, [SP, #112]

(212) 0x423cec LDR	D7, [X15, X17]

  (213) 0x423cf0 FMUL	D8, D6, D17

  (213) 0x423cf4 FMOV	D4, D7

  (213) 0x423cf8 LDR	D1, [X6, X1,LSL #3]

  (213) 0x423cfc FMOV	D31, D16

  (213) 0x423d00 LDR	D2, [X2, X1,LSL #3]

  (213) 0x423d04 LDR	D17, [X3, X1,LSL #3]

  (213) 0x423d08 FABS	D28, D8

  (213) 0x423d0c LDR	D7, [X4, X1,LSL #3]

  (213) 0x423d10 FADD	D6, D1, D2

  (213) 0x423d14 LDR	D27, [X10, X1,LSL #3]

  (213) 0x423d18 LDR	D30, [X7, X1,LSL #3]

  (213) 0x423d1c FADD	D29, D7, D4

  (213) 0x423d20 LDR	D16, [X5, X1,LSL #3]

  (213) 0x423d24 FMUL	D3, D6, D17

  (213) 0x423d28 LDR	D5, [X9, X1,LSL #3]

  (213) 0x423d2c LDR	D9, [X11, X1,LSL #3]

  (213) 0x423d30 FMUL	D4, D29, D27

  (213) 0x423d34 FADD	D29, D30, D30

  (213) 0x423d38 LDR	D2, [X12, X1,LSL #3]

  (213) 0x423d3c FADD	D31, D16, D31

  (213) 0x423d40 FADD	D0, D3, D25

  (213) 0x423d44 FABS	D27, D3

  (213) 0x423d48 LDR	D30, [X14, X1,LSL #3]

  (213) 0x423d4c FMINNM	D3, D30, D24

  (213) 0x423d50 FMUL	D3, D3, D23

  (213) 0x423d54 LDR	D1, [X8, X1,LSL #3]

  (213) 0x423d58 FDIV	D29, D29, D5

  (213) 0x423d5c FADD	D30, D2, D2

  (213) 0x423d60 FMUL	D31, D31, D9

  (213) 0x423d64 FSUB	D0, D0, S8

  (213) 0x423d68 FMUL	D5, D2, D21

  (213) 0x423d6c FMUL	D8, D2, D20

  (213) 0x423d70 FMUL	D2, D18, D2

  (213) 0x423d74 FMAXNM	D28, D28, D2

  (213) 0x423d78 FMAXNM	D28, D28, D27

  (213) 0x423d7c FABS	D9, D4

  (213) 0x423d80 FABS	D27, D31

  (213) 0x423d84 FMAXNM	D9, D27, D9

  (213) 0x423d88 FADD	D0, D0, D4

  (213) 0x423d8c FDIV	D5, D5, D28

  (213) 0x423d90 FMAXNM	D27, D9, D2

  (213) 0x423d94 FSUB	D31, D0, S31

  (213) 0x423d98 FDIV	D4, D8, D27

  (213) 0x423d9c FMADD	D1, D1, D1, D29

  (213) 0x423da0 FDIV	D29, D31, D30

  (213) 0x423da4 FSQRT	D30, D1

  (213) 0x423da8 FMAXNM	D8, D30, D18

  (213) 0x423dac FDIV	D3, D3, D8

  (213) 0x423db0 FMINNM	D2, D5, D3

  (213) 0x423db4 FCMPE	D29, D22

  (213) 0x423db8 B.MI	423e48

  (213) 0x423dbc LDR	D27, [X20]

  (213) 0x423dc0 ADD	X1, X1, #1

  (213) 0x423dc4 FMINNM	D5, D27, D4

  (213) 0x423dc8 FMINNM	D0, D5, D2

  (213) 0x423dcc FMINNM	D19, D19, D0

  (213) 0x423dd0 CMP	W13, W1

  (213) 0x423dd4 B.GE	423cf0

(212) 0x423dd8 LDR	W1, [SP, #132]

(212) 0x423ddc ADD	X6, X6, X22

(212) 0x423de0 ADD	X2, X2, X22

(212) 0x423de4 ADD	X3, X3, X24

(212) 0x423de8 ADD	X5, X5, X18

(212) 0x423dec ADD	X11, X11, X23

(212) 0x423df0 ADD	X4, X4, X18

(212) 0x423df4 ADD	X10, X10, X23

(212) 0x423df8 ADD	X21, X21, X24

(212) 0x423dfc ADD	X16, X16, X22

(212) 0x423e00 ADD	X17, X17, X18

(212) 0x423e04 CMP	W26, W1

(212) 0x423e08 LDR	X1, [SP, #152]

(212) 0x423e0c ORR	X15, XZR, X0

(212) 0x423e10 CSEL	W28, W28, W26, #1

(212) 0x423e14 CSINC	W25, W25, WZR, #1

(212) 0x423e18 ADD	X8, X8, X1

(212) 0x423e1c LDR	X1, [SP, #144]

(212) 0x423e20 ADD	X7, X7, X1

(212) 0x423e24 LDR	X1, [SP, #136]

(212) 0x423e28 ADD	X9, X9, X1

(212) 0x423e2c LDR	X1, [SP, #160]

(212) 0x423e30 ADD	X12, X12, X1

(212) 0x423e34 LDR	W1, [SP, #124]

(212) 0x423e38 CMP	W1, W0

(212) 0x423e3c B.LE	423e94

(212) 0x423e40 ADD	X0, X0, #1

(212) 0x423e44 B	423c84

  (213) 0x423e48 FDIV	D28, D26, D29

  (213) 0x423e4c LDR	D9, [X30]

  (213) 0x423e50 FNMUL	D27, D28, D9

  (213) 0x423e54 B	423dc0

0x423e58 MOVZ	X9, #32752

0x423e5c FMOV	D19, X9

0x423e60 LDR	X2, [X19, #160]

0x423e64 LDR	X1, [X2]

(211) 0x423e68 FMOV	D17, X1

(211) 0x423e6c ORR	X4, XZR, X1

(211) 0x423e70 FMINNM	D7, D19, D17

(211) 0x423e74 FMOV	X3, D7

(211) 0x423e78 CASAL	X4, X3, [X2]

(211) 0x423e7c CMP	X1, X4

(211) 0x423e80 B.NE	423ed4

0x423e84 LDP	X19, X20, [SP, #16]

0x423e88 LDP	X21, X22, [SP, #32]

0x423e8c LDP	X29, X30, [SP], #240

0x423e90 B	401b40

0x423e94 LDR	X19, [SP, #232]

0x423e98 CBZ	W25, 423ec0

0x423e9c LDP	X23, X24, [SP, #48]

0x423ea0 LDP	X25, X26, [SP, #64]

0x423ea4 LDP	D8, D9, [SP, #96]

0x423ea8 STR	W28, [X19, #312]

0x423eac LDP	X27, X28, [SP, #80]

0x423eb0 B	423e60

0x423eb4 ADD	W5, W5, #1

0x423eb8 MOVZ	W6, #0

0x423ebc B	423a88

0x423ec0 LDP	X23, X24, [SP, #48]

0x423ec4 LDP	X25, X26, [SP, #64]

0x423ec8 LDP	X27, X28, [SP, #80]

0x423ecc LDP	D8, D9, [SP, #96]

0x423ed0 B	423e60

(211) 0x423ed4 ORR	X1, XZR, X4

(211) 0x423ed8 B	423e68

0x423edc HINT	#0

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	calc_dt_kernel	calc_dt_kernel.f90:140	exec
○	calc_dt	calc_dt.f90:81	exec
○	timestep	timestep.f90:87	exec
○	hydro	hydro.f90:54	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	calc_dt_kernel.f90:89-129
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/calc_dt_kernel.f90:89-129.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.33 to 1.17 cycles (21.71x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 25.33 to 3.75 cycles (6.76x speedup).

Details

5% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.33 to 1.00 cycles (25.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 568 bytes. The binary function is storing 248 bytes.

General properties

nb instructions	170
loop length	680
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

21.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	20.75	20.75	20.75	20.75	1.25	1.25	1.25	1.25	25.33	25.33	25.33	11.50	11.50
cycles	4.50	4.50	20.75	20.75	20.75	20.75	1.25	1.25	1.25	1.25	25.33	25.33	25.33	11.50	11.50

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	21.13
Overall L1	25.33

Vectorization ratios

all	5%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.33 cycles. At this rate:

23% of peak load performance is reached (22.42 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.79 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 423a40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #784]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 401b60 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 401ad0 <@plt_start@+0x320>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W2, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W3, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W4, W3, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W5, W4, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W6, W5, W20, W4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 423eb4 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x474>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W7, W5, W0, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W8, W5, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W7, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 423e58 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X18, X13, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MOVZ X10, #32752	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W12, W21, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W11, W21, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVI D25, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D26, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
SBFM X15, X11, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W24, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X22, X20, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X5, X6, [X19, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
FMOV D19, X10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
SBFM X10, X24, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X23, [X19, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W25, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X7, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X19, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W10, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSINC W2, W10, W13, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR X3, [X19, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W26, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W12, [SP, #124]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP W24, W2, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X22, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X5, X6, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X8, X23, X15, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X9, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X30, [X19, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X27, X21, [X19, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X12, [X19, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X19, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X19, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X7, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X9, X12, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X22, X5, [X19, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X3, X1, [X19, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
UBFM X11, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X4, X4, X15, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X2, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X6, X24, [X19, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X8, X21, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X21, X5, X15, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X2, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X2, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X22, [X19, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X1, X15, X1, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X2, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X7, X27, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X18, X12, [X19, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X27, X24, X15, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X24, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X22, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X1, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X21, X4, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X3, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X27, [X19, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X5, X15, X18, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X4, X15, X18, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X11, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X18, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X23, X11, [X19, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X21, X27, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X27, X1, [X19, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X6, X27, X15, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X22, X27, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X2, X15, X27, X27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X27, X1, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X6, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X2, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X14, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X14, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X14, X27,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X14, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X19, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X10, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X10, X15, X23, X23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X3, X14, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X1, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X4, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X12, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [X19, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X10, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X11, X15, X23, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X23, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X19, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X12, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X19, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, X12, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X12, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X19, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X12, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [X19, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X12, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X19, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X1, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X1, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X19, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X1, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X14, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X19, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X19, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X19, [X19, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X14, X19,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ X9, #32752	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D19, X9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X2, [X19, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #240	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 401b40 <@plt_start@+0x390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X19, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ W25, 423ec0 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR W28, [X19, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 423e60 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W5, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 423a88 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
B 423e60 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Source file and lines	calc_dt_kernel.f90:89-129
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/calc_dt_kernel.f90:89-129.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

5% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.33 to 1.00 cycles (25.33x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 568 bytes. The binary function is storing 248 bytes.

General properties

nb instructions	170
loop length	680
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

21.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	20.75	20.75	20.75	20.75	1.25	1.25	1.25	1.25	25.33	25.33	25.33	11.50	11.50
cycles	4.50	4.50	20.75	20.75	20.75	20.75	1.25	1.25	1.25	1.25	25.33	25.33	25.33	11.50	11.50

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	21.13
Overall L1	25.33

Vectorization ratios

all	5%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.33 cycles. At this rate:

23% of peak load performance is reached (22.42 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.79 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 423a40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #784]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 401b60 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 401ad0 <@plt_start@+0x320>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W2, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W3, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W4, W3, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W5, W4, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W6, W5, W20, W4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 423eb4 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x474>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W7, W5, W0, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W8, W5, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W7, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 423e58 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X18, X13, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MOVZ X10, #32752	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W12, W21, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W11, W21, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVI D25, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
FMOV D26, #1.0000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
SBFM X15, X11, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X17, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ X16, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X15, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W24, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X22, X20, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X5, X6, [X19, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
FMOV D19, X10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
SBFM X10, X24, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X23, [X19, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MOVZ W25, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W13, [X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X7, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X19, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W10, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
CSINC W2, W10, W13, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
LDR X3, [X19, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W26, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W12, [SP, #124]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP W24, W2, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X22, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X5, X6, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X8, X23, X15, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X9, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X30, [X19, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X27, X21, [X19, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X12, [X19, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X14, [X19, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X4, [X19, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X7, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X9, X12, X8,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X22, X5, [X19, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X3, X1, [X19, #224]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
UBFM X11, X4, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X4, X4, X15, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X2, X5, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X6, X24, [X19, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X8, X21, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X21, X5, X15, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X2, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X2, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X22, [X19, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X1, X15, X1, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X2, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X7, X27, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X18, X12, [X19, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X27, X24, X15, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X24, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X22, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X1, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X21, X4, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X3, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X27, [X19, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X5, X15, X18, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X4, X15, X18, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X11, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X18, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X23, X11, [X19, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X21, X27, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X27, X1, [X19, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
MADD X6, X27, X15, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X22, X27, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X2, X15, X27, X27	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X27, X1, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X6, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X2, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X14, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X14, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X14, X27,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X14, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X19, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X10, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X10, X15, X23, X23	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X3, X14, X3,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X1, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X4, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X12, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [X19, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X10, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X11, X15, X23, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X23, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [X19, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X12, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X19, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, X12, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X12, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X19, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X12, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X12, [X19, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X12, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X19, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X10, X1, X10,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X1, X11,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [X19, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X1, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X14, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X19, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X14, [X19, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X19, [X19, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X14, X19,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X19, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MOVZ X9, #32752	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D19, X9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR X2, [X19, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #240	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 401b40 <@plt_start@+0x390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X19, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ W25, 423ec0 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x480>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR W28, [X19, #312]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 423e60 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W5, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 423a88 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
B 423e60 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x420>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Name	Coverage (%)	Time (s)
▼calc_dt_kernel._omp_fn.0–	10.19	2.17
▼Loop 212 - calc_dt_kernel.f90:96-129 - exec–	0.02	0
○Loop 213 - calc_dt_kernel.f90:96-129 - exec	10.17	2.16
○Loop 211 - calc_dt_kernel.f90:91-91 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

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Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code