OV - exec - Function accelerate_kernel._omp

	Function: accelerate_kernel._omp_fn.0	Module: exec	Source: accelerate_kernel.f90:57-76 [...]	Coverage: 5.26%

/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/accelerate_kernel.f90: 57 - 76

--------------------------------------------------------------------------------

57:     !$OMP PARALLEL

58:

59:     !$OMP DO PRIVATE(j,k,stepbymass_s)

60:     DO k=y_min,y_max+1

61:     !$OMP SIMD

[...]

67:           *0.25_8)

68:

69:         xvel1(j,k)=xvel0(j,k)-stepbymass_s*(xarea(j  ,k  )*(pressure(j  ,k  )-pressure(j-1,k  ))    &

70:           +xarea(j  ,k-1)*(pressure(j  ,k-1)-pressure(j-1,k-1)))

71:         yvel1(j,k)=yvel0(j,k)-stepbymass_s*(yarea(j  ,k  )*(pressure(j  ,k  )-pressure(j  ,k-1))    &

72:           +yarea(j-1,k  )*(pressure(j-1,k  )-pressure(j-1,k-1)))

73:         xvel1(j,k)=xvel1(j,k)-stepbymass_s*(xarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j-1,k  )) &

74:           +xarea(j  ,k-1)*(viscosity(j  ,k-1)-viscosity(j-1,k-1)))

75:         yvel1(j,k)=yvel1(j,k)-stepbymass_s*(yarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j  ,k-1)) &

76:           +yarea(j-1,k  )*(viscosity(j-1,k  )-viscosity(j-1,k-1)))

0x41e780 STP	X29, X30, [SP, #720]!

0x41e784 ADD	X29, SP, #0

0x41e788 STP	X19, X20, [SP, #16]

0x41e78c ORR	X20, XZR, X0

0x41e790 LDR	X0, [X0, #16]

0x41e794 STP	X21, X22, [SP, #32]

0x41e798 STP	X25, X26, [SP, #64]

0x41e79c LDR	W21, [X0]

0x41e7a0 BL	401b60

0x41e7a4 ORR	W19, WZR, W0

0x41e7a8 BL	401ad0

0x41e7ac LDR	X1, [X20, #24]

0x41e7b0 ORR	W25, WZR, W0

0x41e7b4 LDR	W2, [X1]

0x41e7b8 ADD	W3, W2, #2

0x41e7bc SUB	W4, W3, W21

0x41e7c0 SDIV	W5, W4, W19

0x41e7c4 MSUB	W6, W5, W19, W4

0x41e7c8 CMP	W0, W6

0x41e7cc B.LT	41ebd0

(110) 0x41e7d0 MADD	W7, W5, W25, W6

(110) 0x41e7d4 ADD	W8, W5, W7

(110) 0x41e7d8 CMP	W7, W8

(110) 0x41e7dc B.GE	41ebbc

(110) 0x41e7e0 LDP	X15, X16, [X20]

(110) 0x41e7e4 ADD	W11, W21, W8

(110) 0x41e7e8 ADD	W25, W21, W7

(110) 0x41e7ec PTRUE	P0.B, ALL

(110) 0x41e7f0 CNTD	X26, ALL

(110) 0x41e7f4 ORR	P1.B, P0/Z, P0.B, P0.B

(110) 0x41e7f8 FDUP	Z5.D, #80

(110) 0x41e7fc STP	X23, X24, [SP, #48]

(110) 0x41e800 LDR	W21, [X15]

(110) 0x41e804 STP	X27, X28, [SP, #80]

(110) 0x41e808 LDR	W30, [X16]

(110) 0x41e80c LDP	X10, X13, [X20, #32]

(110) 0x41e810 SBFM	X3, X21, #0, #31

(110) 0x41e814 LDP	X22, X28, [X20, #48]

(110) 0x41e818 ADD	W0, W30, #2

(110) 0x41e81c SUB	W15, W0, W21

(110) 0x41e820 WHILELO	P2.D, XZR, X15

(110) 0x41e824 LDP	X27, X17, [X20, #64]

(110) 0x41e828 STP	W21, W0, [SP, #192]

(110) 0x41e82c SBFM	X0, X25, #0, #31

(110) 0x41e830 LDR	X18, [X20, #112]

(110) 0x41e834 STR	W11, [SP, #108]

(110) 0x41e838 LDR	X1, [X20, #120]

(110) 0x41e83c STP	X22, X10, [SP, #240]

(110) 0x41e840 UBFM	X19, X18, #61, #60

(110) 0x41e844 LDR	X6, [X20, #144]

(110) 0x41e848 ADD	X2, X3, X1

(110) 0x41e84c STR	X19, [SP, #112]

(110) 0x41e850 LDR	X24, [X20, #136]

(110) 0x41e854 STR	X17, [SP, #256]

(110) 0x41e858 MADD	X4, X18, X0, X2

(110) 0x41e85c LDR	X14, [X20, #152]

(110) 0x41e860 ADD	X7, X3, X6

(110) 0x41e864 STR	X2, [SP, #296]

(110) 0x41e868 LDP	X23, X9, [X20, #80]

(110) 0x41e86c ADD	X30, X28, X4,LSL #3

(110) 0x41e870 MADD	X8, X0, X24, X7

(110) 0x41e874 UBFM	X5, X24, #61, #60

(110) 0x41e878 STP	X24, X18, [SP, #224]

(110) 0x41e87c UBFM	X11, X14, #61, #60

(110) 0x41e880 ADD	X8, X27, X8,LSL #3

(110) 0x41e884 LDR	X12, [X20, #96]

(110) 0x41e888 STR	X14, [SP, #216]

(110) 0x41e88c LD1RD	{Z4.D}, P0/Z, [X20, #16]

(110) 0x41e890 LDP	X24, X18, [X20, #168]

(110) 0x41e894 STR	X7, [SP, #272]

(110) 0x41e898 LDR	X16, [X20, #184]

(110) 0x41e89c ADD	X19, X3, X18

(110) 0x41e8a0 LDP	X2, X4, [X20, #208]

(110) 0x41e8a4 UBFM	X6, X24, #61, #60

(110) 0x41e8a8 MADD	X1, X0, X24, X19

(110) 0x41e8ac STR	X6, [SP, #120]

(110) 0x41e8b0 LDR	X7, [X20, #192]

(110) 0x41e8b4 ADD	X18, X22, X1,LSL #3

(110) 0x41e8b8 STP	X16, X24, [SP, #200]

(110) 0x41e8bc ADD	X1, X3, X2

(110) 0x41e8c0 LDR	X21, [X20, #200]

(110) 0x41e8c4 ADD	X24, X3, X7

(110) 0x41e8c8 STR	X5, [SP, #144]

(110) 0x41e8cc UBFM	X7, X4, #61, #60

(110) 0x41e8d0 LDR	X22, [X20, #224]

(110) 0x41e8d4 STR	X11, [SP, #184]

(110) 0x41e8d8 MADD	X11, X0, X16, X24

(110) 0x41e8dc UBFM	X16, X16, #61, #60

(110) 0x41e8e0 LDR	X6, [X20, #240]

(110) 0x41e8e4 STR	X24, [SP, #280]

(110) 0x41e8e8 LDR	X5, [X20, #232]

(110) 0x41e8ec ADD	X11, X10, X11,LSL #3

(110) 0x41e8f0 STR	X19, [SP, #288]

(110) 0x41e8f4 UBFM	X19, X21, #61, #60

(110) 0x41e8f8 MADD	X21, X0, X21, X1

(110) 0x41e8fc LDR	X24, [X20, #256]

(110) 0x41e900 ADD	X22, X3, X22

(110) 0x41e904 ADD	X1, X3, X6

(110) 0x41e908 STR	X19, [SP, #128]

(110) 0x41e90c LDR	X10, [X20, #248]

(110) 0x41e910 ADD	X19, X23, X21,LSL #3

(110) 0x41e914 MADD	X23, X0, X4, X22

(110) 0x41e918 UBFM	X4, X5, #61, #60

(110) 0x41e91c STR	X7, [SP, #152]

(110) 0x41e920 MADD	X5, X0, X5, X1

(110) 0x41e924 STR	X16, [SP, #136]

(110) 0x41e928 ADD	X21, X3, X24

(110) 0x41e92c STR	X4, [SP, #168]

(110) 0x41e930 ADD	X2, X12, X23,LSL #3

(110) 0x41e934 LDR	X12, [X20, #264]

(110) 0x41e938 ADD	X7, X13, X5,LSL #3

(110) 0x41e93c MADD	X13, X0, X10, X21

(110) 0x41e940 LDR	X23, [X20, #272]

(110) 0x41e944 UBFM	X10, X10, #61, #60

(110) 0x41e948 STR	X10, [SP, #160]

(110) 0x41e94c ADD	X22, X9, X13,LSL #3

(110) 0x41e950 LDR	X9, [X20, #104]

(110) 0x41e954 LDR	X20, [X20, #160]

(110) 0x41e958 ADD	X4, X3, X23

(110) 0x41e95c MADD	X24, X0, X12, X4

(110) 0x41e960 UBFM	X12, X12, #61, #60

(110) 0x41e964 STR	X12, [SP, #176]

(110) 0x41e968 ADD	X3, X3, X20

(110) 0x41e96c ADD	X1, X9, X24,LSL #3

(110) 0x41e970 MADD	X14, X0, X14, X3

(110) 0x41e974 STR	X3, [SP, #264]

(110) 0x41e978 ADD	X6, X17, X14,LSL #3

(110) 0x41e97c HINT	#0

  (111) 0x41e980 LDP	W17, W0, [SP, #192]

  (111) 0x41e984 CMP	W17, W0

  (111) 0x41e988 B.GE	41eb54

  (111) 0x41e98c LDR	X21, [SP, #232]

  (111) 0x41e990 SUB	W5, W25, #1

  (111) 0x41e994 SUB	X24, X30, #8

  (111) 0x41e998 SBFM	X3, X5, #0, #31

  (111) 0x41e99c SUB	X23, X18, #8

  (111) 0x41e9a0 ORR	P3.B, P2/Z, P2.B, P2.B

  (111) 0x41e9a4 LDR	X10, [SP, #296]

  (111) 0x41e9a8 SUB	X14, X8, #8

  (111) 0x41e9ac SUB	X13, X7, #8

  (111) 0x41e9b0 SUB	X12, X6, #8

  (111) 0x41e9b4 LDR	X0, [SP, #208]

  (111) 0x41e9b8 LDR	X5, [SP, #288]

  (111) 0x41e9bc MADD	X4, X21, X3, X10

  (111) 0x41e9c0 LDR	X9, [SP, #280]

  (111) 0x41e9c4 UBFM	X16, X4, #61, #60

  (111) 0x41e9c8 LDR	X4, [SP, #272]

  (111) 0x41e9cc MADD	X10, X0, X3, X5

  (111) 0x41e9d0 SUB	X20, X16, #8

  (111) 0x41e9d4 ADD	X17, X28, X16

  (111) 0x41e9d8 LDR	X0, [SP, #224]

  (111) 0x41e9dc ADD	X21, X28, X20

  (111) 0x41e9e0 UBFM	X16, X10, #61, #60

  (111) 0x41e9e4 SUB	X20, X16, #8

  (111) 0x41e9e8 MADD	X5, X0, X3, X4

  (111) 0x41e9ec LDR	X4, [SP, #264]

  (111) 0x41e9f0 UBFM	X0, X5, #61, #60

  (111) 0x41e9f4 SUB	X10, X0, #8

  (111) 0x41e9f8 ADD	X5, X27, X0

  (111) 0x41e9fc LDR	X0, [SP, #216]

  (111) 0x41ea00 ADD	X10, X27, X10

  (111) 0x41ea04 MADD	X0, X0, X3, X4

  (111) 0x41ea08 UBFM	X4, X0, #61, #60

  (111) 0x41ea0c LDR	X0, [SP, #200]

  (111) 0x41ea10 MADD	X3, X0, X3, X9

  (111) 0x41ea14 LDR	X0, [SP, #248]

  (111) 0x41ea18 SUB	X9, X4, #8

  (111) 0x41ea1c ADD	X3, X0, X3,LSL #3

  (111) 0x41ea20 LDR	X0, [SP, #240]

  (111) 0x41ea24 ADD	X20, X0, X20

  (111) 0x41ea28 ADD	X16, X0, X16

  (111) 0x41ea2c LDR	X0, [SP, #256]

  (111) 0x41ea30 ADD	X9, X0, X9

  (111) 0x41ea34 ADD	X4, X0, X4

  (111) 0x41ea38 MOVZ	X0, #0

  (111) 0x41ea3c HINT	#0

    (112) 0x41ea40 LD1D	{Z0.D}, P3/Z, [X17, X0,LSL #3]

    (112) 0x41ea44 LD1D	{Z1.D}, P3/Z, [X16, X0,LSL #3]

    (112) 0x41ea48 LD1D	{Z3.D}, P3/Z, [X21, X0,LSL #3]

    (112) 0x41ea4c LD1D	{Z2.D}, P3/Z, [X30, X0,LSL #3]

    (112) 0x41ea50 LD1D	{Z17.D}, P3/Z, [X24, X0,LSL #3]

    (112) 0x41ea54 LD1D	{Z7.D}, P3/Z, [X20, X0,LSL #3]

    (112) 0x41ea58 LD1D	{Z16.D}, P3/Z, [X18, X0,LSL #3]

    (112) 0x41ea5c FMUL	Z6.D, Z1.D, Z0.D

    (112) 0x41ea60 FMAD	Z7.D, P1/M, Z3.D, Z6.D

    (112) 0x41ea64 FMAD	Z16.D, P1/M, Z2.D, Z7.D

    (112) 0x41ea68 LD1D	{Z19.D}, P3/Z, [X5, X0,LSL #3]

    (112) 0x41ea6c LD1D	{Z20.D}, P3/Z, [X10, X0,LSL #3]

    (112) 0x41ea70 LD1D	{Z23.D}, P3/Z, [X3, X0,LSL #3]

    (112) 0x41ea74 LD1D	{Z24.D}, P3/Z, [X8, X0,LSL #3]

    (112) 0x41ea78 LD1D	{Z29.D}, P3/Z, [X19, X0,LSL #3]

    (112) 0x41ea7c LD1D	{Z18.D}, P3/Z, [X23, X0,LSL #3]

    (112) 0x41ea80 LD1D	{Z26.D}, P3/Z, [X14, X0,LSL #3]

    (112) 0x41ea84 LD1D	{Z27.D}, P3/Z, [X11, X0,LSL #3]

    (112) 0x41ea88 FMAD	Z18.D, P1/M, Z17.D, Z16.D

    (112) 0x41ea8c FSUB	Z22.D, Z19.D, Z20.D

    (112) 0x41ea90 FSUB	Z28.D, Z24.D, Z26.D

    (112) 0x41ea94 FMUL	Z25.D, Z22.D, Z23.D

    (112) 0x41ea98 FMUL	Z21.D, Z18.D, Z5.D

    (112) 0x41ea9c FMAD	Z27.D, P1/M, Z28.D, Z25.D

    (112) 0x41eaa0 FDIVR	Z21.D, P1/M, Z21.D, Z4.D

    (112) 0x41eaa4 FMSB	Z27.D, P1/M, Z21.D, Z29.D

    (112) 0x41eaa8 ST1D	{Z27.D}, P3, [X2, X0,LSL #3]

    (112) 0x41eaac LD1D	{Z30.D}, P3/Z, [X14, X0,LSL #3]

    (112) 0x41eab0 LD1D	{Z31.D}, P3/Z, [X10, X0,LSL #3]

    (112) 0x41eab4 LD1D	{Z0.D}, P3/Z, [X13, X0,LSL #3]

    (112) 0x41eab8 LD1D	{Z3.D}, P3/Z, [X8, X0,LSL #3]

    (112) 0x41eabc LD1D	{Z6.D}, P3/Z, [X5, X0,LSL #3]

    (112) 0x41eac0 LD1D	{Z2.D}, P3/Z, [X7, X0,LSL #3]

    (112) 0x41eac4 LD1D	{Z17.D}, P3/Z, [X22, X0,LSL #3]

    (112) 0x41eac8 FSUB	Z1.D, Z30.D, Z31.D

    (112) 0x41eacc FSUB	Z16.D, Z3.D, Z6.D

    (112) 0x41ead0 FMUL	Z7.D, Z1.D, Z0.D

    (112) 0x41ead4 FMAD	Z2.D, P1/M, Z16.D, Z7.D

    (112) 0x41ead8 FMSB	Z2.D, P1/M, Z21.D, Z17.D

    (112) 0x41eadc ST1D	{Z2.D}, P3, [X1, X0,LSL #3]

    (112) 0x41eae0 LD1D	{Z18.D}, P3/Z, [X2, X0,LSL #3]

    (112) 0x41eae4 LD1D	{Z19.D}, P3/Z, [X11, X0,LSL #3]

    (112) 0x41eae8 LD1D	{Z20.D}, P3/Z, [X6, X0,LSL #3]

    (112) 0x41eaec LD1D	{Z22.D}, P3/Z, [X12, X0,LSL #3]

    (112) 0x41eaf0 LD1D	{Z23.D}, P3/Z, [X3, X0,LSL #3]

    (112) 0x41eaf4 LD1D	{Z25.D}, P3/Z, [X4, X0,LSL #3]

    (112) 0x41eaf8 FSUB	Z24.D, Z20.D, Z22.D

    (112) 0x41eafc LD1D	{Z26.D}, P3/Z, [X9, X0,LSL #3]

    (112) 0x41eb00 FSUB	Z27.D, Z25.D, Z26.D

    (112) 0x41eb04 FMUL	Z28.D, Z27.D, Z23.D

    (112) 0x41eb08 FMAD	Z19.D, P1/M, Z24.D, Z28.D

    (112) 0x41eb0c FMSB	Z19.D, P1/M, Z21.D, Z18.D

    (112) 0x41eb10 ST1D	{Z19.D}, P3, [X2, X0,LSL #3]

    (112) 0x41eb14 LD1D	{Z29.D}, P3/Z, [X12, X0,LSL #3]

    (112) 0x41eb18 LD1D	{Z30.D}, P3/Z, [X9, X0,LSL #3]

    (112) 0x41eb1c LD1D	{Z31.D}, P3/Z, [X13, X0,LSL #3]

    (112) 0x41eb20 LD1D	{Z3.D}, P3/Z, [X6, X0,LSL #3]

    (112) 0x41eb24 LD1D	{Z7.D}, P3/Z, [X4, X0,LSL #3]

    (112) 0x41eb28 LD1D	{Z2.D}, P3/Z, [X7, X0,LSL #3]

    (112) 0x41eb2c LD1D	{Z6.D}, P3/Z, [X1, X0,LSL #3]

    (112) 0x41eb30 FSUB	Z0.D, Z29.D, Z30.D

    (112) 0x41eb34 FSUB	Z16.D, Z3.D, Z7.D

    (112) 0x41eb38 FMUL	Z1.D, Z0.D, Z31.D

    (112) 0x41eb3c FMLA	Z1.D, P1/M, Z2.D, Z16.D

    (112) 0x41eb40 FMSB	Z21.D, P1/M, Z1.D, Z6.D

    (112) 0x41eb44 ST1D	{Z21.D}, P3, [X1, X0,LSL #3]

    (112) 0x41eb48 ADD	X0, X0, X26

    (112) 0x41eb4c WHILELO	P3.D, X0, X15

    (112) 0x41eb50 B.NE	41ea40

  (111) 0x41eb54 LDR	W20, [SP, #108]

  (111) 0x41eb58 ADD	W25, W25, #1

  (111) 0x41eb5c LDR	X24, [SP, #112]

  (111) 0x41eb60 LDR	X23, [SP, #120]

  (111) 0x41eb64 LDR	X14, [SP, #128]

  (111) 0x41eb68 ADD	X30, X30, X24

  (111) 0x41eb6c LDR	X13, [SP, #136]

  (111) 0x41eb70 ADD	X18, X18, X23

  (111) 0x41eb74 LDR	X12, [SP, #144]

  (111) 0x41eb78 ADD	X19, X19, X14

  (111) 0x41eb7c LDR	X21, [SP, #152]

  (111) 0x41eb80 ADD	X11, X11, X13

  (111) 0x41eb84 LDR	X17, [SP, #160]

  (111) 0x41eb88 ADD	X8, X8, X12

  (111) 0x41eb8c LDR	X10, [SP, #168]

  (111) 0x41eb90 ADD	X2, X2, X21

  (111) 0x41eb94 LDR	X5, [SP, #176]

  (111) 0x41eb98 ADD	X22, X22, X17

  (111) 0x41eb9c LDR	X3, [SP, #184]

  (111) 0x41eba0 ADD	X7, X7, X10

  (111) 0x41eba4 ADD	X1, X1, X5

  (111) 0x41eba8 ADD	X6, X6, X3

  (111) 0x41ebac CMP	W20, W25

  (111) 0x41ebb0 B.GT	41e980

(110) 0x41ebb4 LDP	X23, X24, [SP, #48]

(110) 0x41ebb8 LDP	X27, X28, [SP, #80]

(110) 0x41ebbc LDP	X19, X20, [SP, #16]

(110) 0x41ebc0 LDP	X21, X22, [SP, #32]

(110) 0x41ebc4 LDP	X25, X26, [SP, #64]

(110) 0x41ebc8 LDP	X29, X30, [SP], #304

(110) 0x41ebcc RET

(110) 0x41ebd0 ADD	W5, W5, #1

(110) 0x41ebd4 MOVZ	W6, #0

(110) 0x41ebd8 B	41e7d0

0x41ebdc HINT	#0

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	accelerate_kernel	accelerate_kernel.f90:57	exec
○	accelerate	accelerate.f90:41	exec
○	hydro	hydro.f90:58	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	accelerate_kernel.f90:57-76
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/accelerate_kernel.f90:57-61,67-76.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 3.00 to 0.41 cycles (7.38x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.00 to 1.00 cycles (3.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 64 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.67	2.67	2.67	2.00	2.00
cycles	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.67	2.67	2.67	2.00	2.00

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.50
Overall L1	3.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
44% of peak store performance is reached (21.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41e780

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #720]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 401b60 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W19, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 401ad0 <@plt_start@+0x320>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W25, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W2, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W3, W2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W4, W3, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W5, W4, W19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W6, W5, W19, W4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 41ebd0 <__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Source file and lines	accelerate_kernel.f90:57-76
Module	exec

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.00 to 1.00 cycles (3.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 24 bytes. The binary function is storing 64 bytes.

General properties

nb instructions	21
loop length	84
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.67	2.67	2.67	2.00	2.00
cycles	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	2.67	2.67	2.67	2.00	2.00

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	2.50
Overall L1	3.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
44% of peak store performance is reached (21.33 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41e780

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #720]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X20, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W21, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 401b60 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W19, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 401ad0 <@plt_start@+0x320>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W25, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W2, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W3, W2, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W4, W3, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W5, W4, W19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W6, W5, W19, W4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 41ebd0 <__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0+0x450>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
HINT #0

Name	Coverage (%)	Time (s)
▼accelerate_kernel._omp_fn.0–	5.26	1.12
▼Loop 110 - accelerate_kernel.f90:57-76 - exec–	0	0
▼Loop 111 - accelerate_kernel.f90:57-76 - exec–	0	0
○Loop 112 - accelerate_kernel.f90:67-76 - exec	5.26	1.12

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code