OV - exec - Function pdv_kernel._omp

	Function: pdv_kernel._omp_fn.0	Module: exec	Source: PdV_kernel.f90:67-135 [...]	Coverage: 10.69%

/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/PdV_kernel.f90: 67 - 135

--------------------------------------------------------------------------------

67:     !$OMP PARALLEL

68:

69:     IF(predict)THEN

70:

71:       !$OMP DO PRIVATE(right_flux,left_flux,top_flux,bottom_flux,total_flux,min_cell_volume, &

72:       !$OMP            energy_change,recip_volume,volume_change_s)

73:       DO k=y_min,y_max

74:       !$OMP SIMD

75:         DO j=x_min,x_max

76:

77:           left_flux=  (xarea(j  ,k  )*(xvel0(j  ,k  )+xvel0(j  ,k+1)                     &

78:             +xvel0(j  ,k  )+xvel0(j  ,k+1)))*0.25_8*dt*0.5

79:           right_flux= (xarea(j+1,k  )*(xvel0(j+1,k  )+xvel0(j+1,k+1)                     &

80:             +xvel0(j+1,k  )+xvel0(j+1,k+1)))*0.25_8*dt*0.5

81:           bottom_flux=(yarea(j  ,k  )*(yvel0(j  ,k  )+yvel0(j+1,k  )                     &

82:             +yvel0(j  ,k  )+yvel0(j+1,k  )))*0.25_8*dt*0.5

83:           top_flux=   (yarea(j  ,k+1)*(yvel0(j  ,k+1)+yvel0(j+1,k+1)                     &

84:             +yvel0(j  ,k+1)+yvel0(j+1,k+1)))*0.25_8*dt*0.5

85:           total_flux=right_flux-left_flux+top_flux-bottom_flux

86:

87:           volume_change_s=volume(j,k)/(volume(j,k)+total_flux)

[...]

93:           recip_volume=1.0/volume(j,k)

94:

95:           energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume

96:

97:           energy1(j,k)=energy0(j,k)-energy_change

98:

99:           density1(j,k)=density0(j,k)*volume_change_s

[...]

108:       !$OMP            energy_change,recip_volume,volume_change_s)

109:       DO k=y_min,y_max

110:       !$OMP SIMD

111:         DO j=x_min,x_max

112:

113:           left_flux=  (xarea(j  ,k  )*(xvel0(j  ,k  )+xvel0(j  ,k+1)                     &

114:             +xvel1(j  ,k  )+xvel1(j  ,k+1)))*0.25_8*dt

115:           right_flux= (xarea(j+1,k  )*(xvel0(j+1,k  )+xvel0(j+1,k+1)                     &

116:             +xvel1(j+1,k  )+xvel1(j+1,k+1)))*0.25_8*dt

117:           bottom_flux=(yarea(j  ,k  )*(yvel0(j  ,k  )+yvel0(j+1,k  )                     &

118:             +yvel1(j  ,k  )+yvel1(j+1,k  )))*0.25_8*dt

119:           top_flux=   (yarea(j  ,k+1)*(yvel0(j  ,k+1)+yvel0(j+1,k+1)                     &

120:             +yvel1(j  ,k+1)+yvel1(j+1,k+1)))*0.25_8*dt

121:           total_flux=right_flux-left_flux+top_flux-bottom_flux

122:

123:           volume_change_s=volume(j,k)/(volume(j,k)+total_flux)

[...]

129:           recip_volume=1.0/volume(j,k)

130:

131:           energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume

132:

133:           energy1(j,k)=energy0(j,k)-energy_change

134:

135:           density1(j,k)=density0(j,k)*volume_change_s

0x41d660 STP	X29, X30, [SP, #752]!

0x41d664 ADD	X29, SP, #0

0x41d668 STP	X19, X20, [SP, #16]

0x41d66c ORR	X19, XZR, X0

0x41d670 LDR	X0, [X0, #24]

0x41d674 STP	X21, X22, [SP, #32]

0x41d678 STP	X23, X24, [SP, #48]

0x41d67c LDR	W23, [X0]

0x41d680 STP	X25, X26, [SP, #64]

0x41d684 STP	X27, X28, [SP, #80]

0x41d688 BL	401b60

0x41d68c ORR	W22, WZR, W0

0x41d690 BL	401ad0

0x41d694 LDR	X1, [X19, #32]

0x41d698 LDP	X21, X20, [X19, #152]

0x41d69c LDP	X25, X30, [X19, #168]

0x41d6a0 LDP	X17, X13, [X19, #216]

0x41d6a4 LDP	X16, X12, [X19, #232]

0x41d6a8 LDP	X15, X10, [X19, #248]

0x41d6ac LDP	X14, X4, [X19, #264]

0x41d6b0 LDP	X6, X3, [X19, #280]

0x41d6b4 LDR	W2, [X1]

0x41d6b8 LDR	X18, [X19, #192]

0x41d6bc LDR	X28, [X19, #200]

0x41d6c0 ADD	W7, W2, #1

0x41d6c4 SUB	W11, W7, W23

0x41d6c8 LDR	X1, [X19, #208]

0x41d6cc STR	X18, [SP, #200]

0x41d6d0 SDIV	W27, W11, W22

0x41d6d4 LDR	X26, [X19, #184]

0x41d6d8 STR	X28, [SP, #104]

0x41d6dc LDR	X5, [X19, #296]

0x41d6e0 STR	X1, [SP, #152]

0x41d6e4 LDR	X9, [X19, #312]

0x41d6e8 LDR	X2, [X19, #320]

0x41d6ec LDR	X8, [X19, #328]

0x41d6f0 MSUB	W1, W27, W22, W11

0x41d6f4 LDR	X22, [X19, #304]

0x41d6f8 LDP	X7, X11, [X19, #336]

0x41d6fc LDR	X28, [X19]

0x41d700 LDR	X18, [X19, #352]

0x41d704 LDR	W28, [X28]

0x41d708 CBZ	W28, 41da94

0x41d70c CMP	W0, W1

0x41d710 B.LT	41ded0

0x41d714 MADD	W11, W27, W0, W1

0x41d718 ADD	W22, W27, W11

0x41d71c CMP	W11, W22

0x41d720 B.GE	41da78

0x41d724 ADD	W1, W22, W23

0x41d728 ADD	W11, W11, W23

0x41d72c LDR	X28, [X19, #8]

0x41d730 SBFM	X5, X11, #0, #31

0x41d734 UBFM	X0, X9, #61, #60

0x41d738 PTRUE	P3.B, ALL

0x41d73c STR	W1, [SP, #160]

0x41d740 UBFM	X22, X9, #61, #60

0x41d744 UBFM	X18, X14, #61, #60

0x41d748 LDR	X1, [X19, #16]

0x41d74c MADD	X23, X5, X6, X6

0x41d750 FDUP	Z3.D, #80

0x41d754 MADD	X22, X5, X22, X22

0x41d758 STR	X0, [SP, #168]

0x41d75c FDUP	Z4.D, #96

0x41d760 SUB	X0, XZR, X9,LSL #3

0x41d764 LDR	W28, [X28]

0x41d768 FDUP	Z19.D, #112

0x41d76c STR	X18, [SP, #136]

0x41d770 UBFM	X18, X15, #61, #60

0x41d774 LDR	X27, [X19, #48]

0x41d778 MADD	X0, X0, X5, X22

0x41d77c STR	X18, [SP, #176]

0x41d780 UBFM	X18, X17, #61, #60

0x41d784 LDR	W1, [X1]

0x41d788 STR	X18, [SP, #184]

0x41d78c UBFM	X18, X21, #61, #60

0x41d790 STR	X0, [SP, #192]

0x41d794 UBFM	X0, X16, #61, #60

0x41d798 LDR	X22, [X19, #56]

0x41d79c STR	X0, [SP, #120]

0x41d7a0 STR	W1, [SP, #100]

0x41d7a4 SBFM	X1, X28, #0, #31

0x41d7a8 ADD	X0, X2, X1

0x41d7ac ADD	X3, X3, X1

0x41d7b0 STR	X18, [SP, #112]

0x41d7b4 ADD	X2, X20, X1

0x41d7b8 ADD	X20, X23, X3

0x41d7bc LDR	W23, [SP, #100]

0x41d7c0 MADD	X9, X5, X9, X0

0x41d7c4 ADD	X10, X10, X1

0x41d7c8 ADD	X12, X12, X1

0x41d7cc LDR	X0, [SP, #200]

0x41d7d0 ADD	X4, X4, X1

0x41d7d4 MADD	X2, X21, X5, X2

0x41d7d8 MADD	X15, X5, X15, X10

0x41d7dc UBFM	X21, X25, #61, #60

0x41d7e0 ADD	X7, X7, X1

0x41d7e4 ADD	X9, X22, X9,LSL #3

0x41d7e8 LDR	X22, [X19, #64]

0x41d7ec ADD	X13, X13, X1

0x41d7f0 CMP	W28, W23

0x41d7f4 MADD	X16, X16, X5, X12

0x41d7f8 LDR	X23, [SP, #152]

0x41d7fc MADD	X14, X14, X5, X4

0x41d800 ADD	X10, X0, X1

0x41d804 STR	X21, [SP, #152]

0x41d808 MADD	X18, X5, X8, X8

0x41d80c LDR	X21, [X19, #80]

0x41d810 MADD	X13, X5, X17, X13

0x41d814 UBFM	X17, X26, #61, #60

0x41d818 MADD	X12, X26, X5, X10

0x41d81c MOVZ	W26, #0

0x41d820 LDR	X10, [SP, #104]

0x41d824 ADD	X15, X22, X15,LSL #3

0x41d828 ADD	X22, X23, X1

0x41d82c ADD	X1, X30, X1

0x41d830 STR	W28, [SP, #104]

0x41d834 UBFM	X30, X6, #61, #60

0x41d838 UBFM	X28, X8, #61, #60

0x41d83c MADD	X6, X5, X6, X3

0x41d840 MADD	X0, X5, X25, X1

0x41d844 STR	X17, [SP, #128]

0x41d848 ADD	X17, X18, X7

0x41d84c LDR	X3, [X19, #88]

0x41d850 CNTD	X25, ALL

0x41d854 MADD	X22, X5, X10, X22

0x41d858 UBFM	X23, X10, #61, #60

0x41d85c ADD	X10, X27, X14,LSL #3

0x41d860 LDR	X27, [X19, #104]

0x41d864 MADD	X5, X5, X8, X7

0x41d868 STR	X23, [SP, #144]

0x41d86c LDP	W8, W7, [SP, #100]

0x41d870 ADD	X1, X21, X0,LSL #3

0x41d874 ADD	X12, X3, X12,LSL #3

0x41d878 LDR	X4, [X19, #96]

0x41d87c ADD	X14, X27, X13,LSL #3

0x41d880 LDR	X13, [X19, #72]

0x41d884 LDP	X0, X18, [X19, #112]

0x41d888 ADD	W27, W8, #1

0x41d88c ADD	X3, X4, X22,LSL #3

0x41d890 CSINC	W22, W7, W8, #12

0x41d894 SUB	W4, W27, W7

0x41d898 WHILELO	P4.D, XZR, X4

0x41d89c STR	X19, [SP, #200]

0x41d8a0 LDR	X21, [X19, #136]

0x41d8a4 ADD	X2, X13, X2,LSL #3

0x41d8a8 ADD	X6, X18, X6,LSL #3

0x41d8ac LDR	X23, [X19, #40]

0x41d8b0 ADD	X13, X0, X16,LSL #3

0x41d8b4 ADD	X8, X18, X20,LSL #3

0x41d8b8 ADD	X5, X21, X5,LSL #3

0x41d8bc ADD	X7, X21, X17,LSL #3

(102) 0x41d8c0 LDP	W19, W20, [SP, #100]

(102) 0x41d8c4 ADD	W11, W11, #1

(102) 0x41d8c8 CMP	W20, W19

(102) 0x41d8cc B.GT	41d9fc

(102) 0x41d8d0 LDR	X17, [SP, #192]

(102) 0x41d8d4 ADD	X21, X10, #8

(102) 0x41d8d8 ADD	X20, X6, #8

(102) 0x41d8dc ADD	X19, X8, #8

(102) 0x41d8e0 ADD	X18, X5, #8

(102) 0x41d8e4 ORR	P5.B, P4/Z, P4.B, P4.B

(102) 0x41d8e8 ADD	X16, X7, #8

(102) 0x41d8ec MOVZ	X0, #0

(102) 0x41d8f0 ADD	X17, X17, X9

(102) 0x41d8f4 HINT	#0

(102) 0x41d8f8 HINT	#0

(102) 0x41d8fc HINT	#0

  (103) 0x41d900 LD1D	{Z20.D}, P5/Z, [X20, X0,LSL #3]

  (103) 0x41d904 LD1D	{Z21.D}, P5/Z, [X19, X0,LSL #3]

  (103) 0x41d908 LD1D	{Z26.D}, P5/Z, [X6, X0,LSL #3]

  (103) 0x41d90c LD1D	{Z22.D}, P5/Z, [X21, X0,LSL #3]

  (103) 0x41d910 FADD	Z23.D, Z21.D, Z20.D

  (103) 0x41d914 FADD	Z25.D, Z23.D, Z20.D

  (103) 0x41d918 FADD	Z27.D, Z25.D, Z21.D

  (103) 0x41d91c LD1D	{Z28.D}, P5/Z, [X8, X0,LSL #3]

  (103) 0x41d920 LD1D	{Z18.D}, P5/Z, [X7, X0,LSL #3]

  (103) 0x41d924 LD1D	{Z7.D}, P5/Z, [X16, X0,LSL #3]

  (103) 0x41d928 LD1D	{Z25.D}, P5/Z, [X5, X0,LSL #3]

  (103) 0x41d92c LD1RD	{Z24.D}, P3/Z, [X23]

  (103) 0x41d930 LD1D	{Z2.D}, P5/Z, [X10, X0,LSL #3]

  (103) 0x41d934 LD1D	{Z23.D}, P5/Z, [X17, X0,LSL #3]

  (103) 0x41d938 FMUL	Z29.D, Z27.D, Z22.D

  (103) 0x41d93c FADD	Z30.D, Z28.D, Z26.D

  (103) 0x41d940 LD1D	{Z27.D}, P5/Z, [X18, X0,LSL #3]

  (103) 0x41d944 FADD	Z1.D, Z30.D, Z26.D

  (103) 0x41d948 FADD	Z17.D, Z7.D, Z18.D

  (103) 0x41d94c FADD	Z0.D, Z1.D, Z28.D

  (103) 0x41d950 FADD	Z21.D, Z17.D, Z18.D

  (103) 0x41d954 FMUL	Z16.D, Z0.D, Z2.D

  (103) 0x41d958 FADD	Z22.D, Z21.D, Z7.D

  (103) 0x41d95c FMUL	Z31.D, Z29.D, Z3.D

  (103) 0x41d960 FMUL	Z26.D, Z22.D, Z23.D

  (103) 0x41d964 FMUL	Z5.D, Z31.D, Z24.D

  (103) 0x41d968 FMUL	Z6.D, Z16.D, Z3.D

  (103) 0x41d96c FMUL	Z5.D, P3/M, Z5.D, #0

  (103) 0x41d970 FMUL	Z20.D, Z6.D, Z24.D

  (103) 0x41d974 FMSB	Z20.D, P3/M, Z4.D, Z5.D

  (103) 0x41d978 LD1D	{Z17.D}, P5/Z, [X15, X0,LSL #3]

  (103) 0x41d97c LD1D	{Z16.D}, P5/Z, [X2, X0,LSL #3]

  (103) 0x41d980 LD1D	{Z5.D}, P5/Z, [X9, X0,LSL #3]

  (103) 0x41d984 LD1D	{Z18.D}, P5/Z, [X14, X0,LSL #3]

  (103) 0x41d988 LD1D	{Z7.D}, P5/Z, [X13, X0,LSL #3]

  (103) 0x41d98c FADD	Z29.D, Z27.D, Z25.D

  (103) 0x41d990 FMUL	Z28.D, Z26.D, Z3.D

  (103) 0x41d994 FADD	Z31.D, Z29.D, Z25.D

  (103) 0x41d998 FMUL	Z30.D, Z28.D, Z24.D

  (103) 0x41d99c LD1D	{Z25.D}, P5/Z, [X12, X0,LSL #3]

  (103) 0x41d9a0 FMAD	Z30.D, P3/M, Z4.D, Z20.D

  (103) 0x41d9a4 FADD	Z1.D, Z31.D, Z27.D

  (103) 0x41d9a8 FDIV	Z18.D, P3/M, Z18.D, Z16.D

  (103) 0x41d9ac FMUL	Z0.D, Z1.D, Z5.D

  (103) 0x41d9b0 MOVPRFX	Z6, Z7

  (103) 0x41d9b4 FDIV	Z6.D, P3/M, Z6.D, Z16.D

  (103) 0x41d9b8 FMUL	Z2.D, Z0.D, Z3.D

  (103) 0x41d9bc FADD	Z20.D, Z6.D, Z18.D

  (103) 0x41d9c0 FMUL	Z24.D, Z2.D, Z24.D

  (103) 0x41d9c4 FMSB	Z24.D, P3/M, Z4.D, Z30.D

  (103) 0x41d9c8 FADD	Z21.D, Z17.D, Z24.D

  (103) 0x41d9cc FMUL	Z22.D, Z20.D, Z24.D

  (103) 0x41d9d0 MOVPRFX	Z23, Z17

  (103) 0x41d9d4 FDIV	Z23.D, P3/M, Z23.D, Z21.D

  (103) 0x41d9d8 FDIVR	Z17.D, P3/M, Z17.D, Z19.D

  (103) 0x41d9dc FMSB	Z22.D, P3/M, Z17.D, Z25.D

  (103) 0x41d9e0 ST1D	{Z22.D}, P5, [X3, X0,LSL #3]

  (103) 0x41d9e4 LD1D	{Z26.D}, P5/Z, [X2, X0,LSL #3]

  (103) 0x41d9e8 FMUL	Z27.D, Z26.D, Z23.D

  (103) 0x41d9ec ST1D	{Z27.D}, P5, [X1, X0,LSL #3]

  (103) 0x41d9f0 ADD	X0, X0, X25

  (103) 0x41d9f4 WHILELO	P5.D, X0, X4

  (103) 0x41d9f8 B.NE	41d900

(102) 0x41d9fc LDR	X21, [SP, #136]

(102) 0x41da00 CMP	W27, W22

(102) 0x41da04 ADD	X6, X6, X30

(102) 0x41da08 ADD	X8, X8, X30

(102) 0x41da0c ADD	X5, X5, X28

(102) 0x41da10 CSEL	W24, W24, W27, #1

(102) 0x41da14 LDR	X20, [SP, #168]

(102) 0x41da18 ADD	X7, X7, X28

(102) 0x41da1c CSINC	W26, W26, WZR, #1

(102) 0x41da20 LDR	X19, [SP, #176]

(102) 0x41da24 ADD	X10, X10, X21

(102) 0x41da28 LDR	X16, [SP, #112]

(102) 0x41da2c ADD	X9, X9, X20

(102) 0x41da30 LDR	X17, [SP, #120]

(102) 0x41da34 ADD	X15, X15, X19

(102) 0x41da38 LDR	W19, [SP, #160]

(102) 0x41da3c ADD	X2, X2, X16

(102) 0x41da40 LDR	X0, [SP, #128]

(102) 0x41da44 ADD	X13, X13, X17

(102) 0x41da48 LDR	X21, [SP, #144]

(102) 0x41da4c LDR	X20, [SP, #152]

(102) 0x41da50 ADD	X12, X12, X0

(102) 0x41da54 LDR	X18, [SP, #184]

(102) 0x41da58 ADD	X3, X3, X21

(102) 0x41da5c ADD	X1, X1, X20

(102) 0x41da60 ADD	X14, X14, X18

(102) 0x41da64 CMP	W19, W11

(102) 0x41da68 B.GT	41d8c0

0x41da6c LDR	X30, [SP, #200]

0x41da70 CBZ	W26, 41da78

0x41da74 STR	W24, [X30, #360]

(99) 0x41da78 LDP	X19, X20, [SP, #16]

(99) 0x41da7c LDP	X21, X22, [SP, #32]

(99) 0x41da80 LDP	X23, X24, [SP, #48]

(99) 0x41da84 LDP	X25, X26, [SP, #64]

(99) 0x41da88 LDP	X27, X28, [SP, #80]

(99) 0x41da8c LDP	X29, X30, [SP], #272

(99) 0x41da90 RET

(99) 0x41da94 CMP	W0, W1

(99) 0x41da98 B.LT	41deec

(99) 0x41da9c MADD	W24, W27, W0, W1

(99) 0x41daa0 ADD	W27, W27, W24

(99) 0x41daa4 CMP	W24, W27

(99) 0x41daa8 B.GE	41da78

(99) 0x41daac ADD	W1, W27, W23

(99) 0x41dab0 LDR	X28, [X19, #8]

(99) 0x41dab4 ADD	W0, W24, W23

(99) 0x41dab8 UBFM	X24, X21, #61, #60

(99) 0x41dabc UBFM	X23, X15, #61, #60

(99) 0x41dac0 PTRUE	P0.B, ALL

(99) 0x41dac4 STR	W1, [SP, #144]

(99) 0x41dac8 UBFM	X1, X14, #61, #60

(99) 0x41dacc UBFM	X27, X26, #61, #60

(99) 0x41dad0 STR	W0, [SP, #100]

(99) 0x41dad4 SBFM	X0, X0, #0, #31

(99) 0x41dad8 FDUP	Z3.D, #80

(99) 0x41dadc STR	X1, [SP, #160]

(99) 0x41dae0 FDUP	Z4.D, #112

(99) 0x41dae4 LDR	X1, [X19, #16]

(99) 0x41dae8 STR	X24, [SP, #224]

(99) 0x41daec UBFM	X24, X16, #61, #60

(99) 0x41daf0 LDR	W28, [X28]

(99) 0x41daf4 STR	X23, [SP, #208]

(99) 0x41daf8 UBFM	X23, X17, #61, #60

(99) 0x41dafc STR	X24, [SP, #232]

(99) 0x41db00 MADD	X24, X0, X5, X5

(99) 0x41db04 STR	X1, [SP, #128]

(99) 0x41db08 LDR	W1, [X1]

(99) 0x41db0c STR	W28, [SP, #120]

(99) 0x41db10 MADD	X28, X0, X8, X8

(99) 0x41db14 STR	X23, [SP, #216]

(99) 0x41db18 MADD	X23, X0, X6, X6

(99) 0x41db1c STR	X27, [SP, #240]

(99) 0x41db20 MADD	X27, X0, X9, X9

(99) 0x41db24 STR	W1, [SP, #128]

(99) 0x41db28 LDR	X1, [SP, #104]

(99) 0x41db2c UBFM	X1, X1, #61, #60

(99) 0x41db30 STR	X1, [SP, #248]

(99) 0x41db34 LDRSW	X1, [SP, #120]

(99) 0x41db38 ADD	X4, X4, X1

(99) 0x41db3c ADD	X12, X12, X1

(99) 0x41db40 ADD	X13, X13, X1

(99) 0x41db44 ADD	X18, X18, X1

(99) 0x41db48 MADD	X14, X14, X0, X4

(99) 0x41db4c LDR	X4, [SP, #200]

(99) 0x41db50 ADD	X30, X30, X1

(99) 0x41db54 MADD	X16, X0, X16, X12

(99) 0x41db58 ADD	X3, X3, X1

(99) 0x41db5c ADD	X2, X2, X1

(99) 0x41db60 MADD	X17, X0, X17, X13

(99) 0x41db64 LDR	X13, [SP, #104]

(99) 0x41db68 ADD	X7, X7, X1

(99) 0x41db6c ADD	X22, X22, X1

(99) 0x41db70 ADD	X20, X20, X1

(99) 0x41db74 ADD	X10, X10, X1

(99) 0x41db78 ADD	X12, X4, X1

(99) 0x41db7c LDR	X4, [SP, #152]

(99) 0x41db80 MADD	X21, X0, X21, X20

(99) 0x41db84 MADD	X10, X0, X15, X10

(99) 0x41db88 ADD	X20, X23, X3

(99) 0x41db8c ADD	X23, X24, X22

(99) 0x41db90 STR	X12, [SP, #136]

(99) 0x41db94 MADD	X22, X0, X5, X22

(99) 0x41db98 ADD	X15, X27, X2

(99) 0x41db9c LDR	X12, [SP, #136]

(99) 0x41dba0 ADD	X24, X28, X7

(99) 0x41dba4 LDP	X27, X28, [X19, #72]

(99) 0x41dba8 ADD	X4, X4, X1

(99) 0x41dbac MADD	X1, X0, X25, X30

(99) 0x41dbb0 MADD	X4, X0, X13, X4

(99) 0x41dbb4 UBFM	X13, X25, #61, #60

(99) 0x41dbb8 MADD	X12, X0, X26, X12

(99) 0x41dbbc MADD	X26, X0, X11, X11

(99) 0x41dbc0 STR	X13, [SP, #256]

(99) 0x41dbc4 UBFM	X13, X5, #61, #60

(99) 0x41dbc8 MADD	X25, X0, X11, X18

(99) 0x41dbcc UBFM	X5, X9, #61, #60

(99) 0x41dbd0 UBFM	X11, X11, #61, #60

(99) 0x41dbd4 ADD	X26, X26, X18

(99) 0x41dbd8 LDR	X18, [X19, #64]

(99) 0x41dbdc STP	X13, X5, [SP, #176]

(99) 0x41dbe0 MADD	X13, X0, X6, X3

(99) 0x41dbe4 MADD	X5, X0, X9, X2

(99) 0x41dbe8 MADD	X9, X0, X8, X7

(99) 0x41dbec LDR	W3, [SP, #120]

(99) 0x41dbf0 ADD	X30, X18, X10,LSL #3

(99) 0x41dbf4 UBFM	X10, X6, #61, #60

(99) 0x41dbf8 UBFM	X18, X8, #61, #60

(99) 0x41dbfc LDR	W6, [SP, #128]

(99) 0x41dc00 STR	X10, [SP, #168]

(99) 0x41dc04 STR	X18, [SP, #192]

(99) 0x41dc08 LDR	W7, [SP, #128]

(99) 0x41dc0c LDP	X2, X10, [X19, #88]

(99) 0x41dc10 CMP	W3, W6

(99) 0x41dc14 LDP	X6, X8, [X19, #104]

(99) 0x41dc18 ADD	X18, X2, X12,LSL #3

(99) 0x41dc1c ADD	X2, X28, X1,LSL #3

(99) 0x41dc20 STR	X11, [SP, #200]

(99) 0x41dc24 LDR	X0, [X19, #48]

(99) 0x41dc28 ADD	X3, X10, X4,LSL #3

(99) 0x41dc2c ADD	X17, X6, X17,LSL #3

(99) 0x41dc30 STR	X19, [SP, #264]

(99) 0x41dc34 LDR	X12, [X19, #56]

(99) 0x41dc38 ADD	X16, X8, X16,LSL #3

(99) 0x41dc3c STR	WZR, [SP, #104]

(99) 0x41dc40 LDR	X28, [X19, #40]

(99) 0x41dc44 ADD	X14, X0, X14,LSL #3

(99) 0x41dc48 ADD	X0, X27, X21,LSL #3

(99) 0x41dc4c ADD	W21, W7, #1

(99) 0x41dc50 LDR	W27, [SP, #120]

(99) 0x41dc54 CSINC	W1, W27, W7, #12

(99) 0x41dc58 ADD	X15, X12, X15,LSL #3

(99) 0x41dc5c STR	W1, [SP, #152]

(99) 0x41dc60 LDR	X7, [X19, #128]

(99) 0x41dc64 STR	W21, [SP, #136]

(99) 0x41dc68 LDR	X11, [X19, #120]

(99) 0x41dc6c SUB	W4, W21, W27

(99) 0x41dc70 WHILELO	P2.D, XZR, X4

(99) 0x41dc74 ADD	X12, X7, X22,LSL #3

(99) 0x41dc78 LDR	X22, [X19, #56]

(99) 0x41dc7c ADD	X6, X7, X23,LSL #3

(99) 0x41dc80 LDR	X23, [X19, #144]

(99) 0x41dc84 ADD	X13, X11, X13,LSL #3

(99) 0x41dc88 ADD	X7, X11, X20,LSL #3

(99) 0x41dc8c LDR	X19, [X19, #136]

(99) 0x41dc90 ADD	X5, X22, X5,LSL #3

(99) 0x41dc94 ADD	X8, X23, X26,LSL #3

(99) 0x41dc98 ADD	X11, X19, X9,LSL #3

(99) 0x41dc9c ADD	X10, X19, X24,LSL #3

(99) 0x41dca0 ADD	X9, X23, X25,LSL #3

  (100) 0x41dca4 LDR	W20, [SP, #100]

  (100) 0x41dca8 LDR	W24, [SP, #128]

  (100) 0x41dcac LDR	W25, [SP, #120]

  (100) 0x41dcb0 ADD	W26, W20, #1

  (100) 0x41dcb4 STR	W26, [SP, #100]

  (100) 0x41dcb8 CMP	W25, W24

  (100) 0x41dcbc B.GT	41ddf0

  (100) 0x41dcc0 ADD	X27, X14, #8

  (100) 0x41dcc4 ADD	X26, X13, #8

  (100) 0x41dcc8 ORR	P1.B, P2/Z, P2.B, P2.B

  (100) 0x41dccc ADD	X25, X7, #8

  (100) 0x41dcd0 ADD	X24, X12, #8

  (100) 0x41dcd4 ADD	X23, X6, #8

  (100) 0x41dcd8 ADD	X22, X11, #8

  (100) 0x41dcdc ADD	X21, X9, #8

  (100) 0x41dce0 ADD	X20, X10, #8

  (100) 0x41dce4 ADD	X19, X8, #8

  (100) 0x41dce8 MOVZ	X1, #0

    (101) 0x41dcec LD1D	{Z2.D}, P1/Z, [X26, X1,LSL #3]

    (101) 0x41dcf0 LD1D	{Z1.D}, P1/Z, [X25, X1,LSL #3]

    (101) 0x41dcf4 LD1D	{Z0.D}, P1/Z, [X24, X1,LSL #3]

    (101) 0x41dcf8 LD1D	{Z6.D}, P1/Z, [X23, X1,LSL #3]

    (101) 0x41dcfc LD1D	{Z16.D}, P1/Z, [X27, X1,LSL #3]

    (101) 0x41dd00 FADD	Z5.D, Z1.D, Z2.D

    (101) 0x41dd04 FADD	Z7.D, Z5.D, Z0.D

    (101) 0x41dd08 FADD	Z17.D, Z7.D, Z6.D

    (101) 0x41dd0c LD1RD	{Z18.D}, P0/Z, [X28]

    (101) 0x41dd10 LD1D	{Z20.D}, P1/Z, [X13, X1,LSL #3]

    (101) 0x41dd14 LD1D	{Z22.D}, P1/Z, [X7, X1,LSL #3]

    (101) 0x41dd18 LD1D	{Z25.D}, P1/Z, [X12, X1,LSL #3]

    (101) 0x41dd1c LD1D	{Z26.D}, P1/Z, [X6, X1,LSL #3]

    (101) 0x41dd20 LD1D	{Z28.D}, P1/Z, [X14, X1,LSL #3]

    (101) 0x41dd24 LD1D	{Z30.D}, P1/Z, [X10, X1,LSL #3]

    (101) 0x41dd28 LD1D	{Z1.D}, P1/Z, [X20, X1,LSL #3]

    (101) 0x41dd2c LD1D	{Z5.D}, P1/Z, [X8, X1,LSL #3]

    (101) 0x41dd30 LD1D	{Z7.D}, P1/Z, [X19, X1,LSL #3]

    (101) 0x41dd34 LD1D	{Z6.D}, P1/Z, [X15, X1,LSL #3]

    (101) 0x41dd38 FMUL	Z19.D, Z17.D, Z16.D

    (101) 0x41dd3c FADD	Z24.D, Z22.D, Z20.D

    (101) 0x41dd40 FADD	Z0.D, Z30.D, Z1.D

    (101) 0x41dd44 FADD	Z27.D, Z25.D, Z24.D

    (101) 0x41dd48 FADD	Z16.D, Z0.D, Z5.D

    (101) 0x41dd4c FADD	Z29.D, Z27.D, Z26.D

    (101) 0x41dd50 FADD	Z17.D, Z16.D, Z7.D

    (101) 0x41dd54 FMUL	Z31.D, Z29.D, Z28.D

    (101) 0x41dd58 FMUL	Z21.D, Z19.D, Z3.D

    (101) 0x41dd5c FMUL	Z2.D, Z31.D, Z3.D

    (101) 0x41dd60 FMUL	Z23.D, Z21.D, Z18.D

    (101) 0x41dd64 FMSB	Z2.D, P0/M, Z18.D, Z23.D

    (101) 0x41dd68 LD1D	{Z0.D}, P1/Z, [X30, X1,LSL #3]

    (101) 0x41dd6c LD1D	{Z31.D}, P1/Z, [X0, X1,LSL #3]

    (101) 0x41dd70 LD1D	{Z19.D}, P1/Z, [X11, X1,LSL #3]

    (101) 0x41dd74 LD1D	{Z21.D}, P1/Z, [X22, X1,LSL #3]

    (101) 0x41dd78 LD1D	{Z24.D}, P1/Z, [X9, X1,LSL #3]

    (101) 0x41dd7c LD1D	{Z25.D}, P1/Z, [X21, X1,LSL #3]

    (101) 0x41dd80 LD1D	{Z27.D}, P1/Z, [X5, X1,LSL #3]

    (101) 0x41dd84 LD1D	{Z29.D}, P1/Z, [X17, X1,LSL #3]

    (101) 0x41dd88 LD1D	{Z5.D}, P1/Z, [X16, X1,LSL #3]

    (101) 0x41dd8c LD1D	{Z16.D}, P1/Z, [X18, X1,LSL #3]

    (101) 0x41dd90 FMUL	Z20.D, Z17.D, Z6.D

    (101) 0x41dd94 FADD	Z23.D, Z19.D, Z21.D

    (101) 0x41dd98 FMUL	Z22.D, Z20.D, Z3.D

    (101) 0x41dd9c FADD	Z26.D, Z23.D, Z24.D

    (101) 0x41dda0 FMAD	Z22.D, P0/M, Z18.D, Z2.D

    (101) 0x41dda4 FADD	Z28.D, Z26.D, Z25.D

    (101) 0x41dda8 FDIV	Z29.D, P0/M, Z29.D, Z31.D

    (101) 0x41ddac FMUL	Z30.D, Z28.D, Z27.D

    (101) 0x41ddb0 FDIV	Z5.D, P0/M, Z5.D, Z31.D

    (101) 0x41ddb4 FMUL	Z1.D, Z30.D, Z3.D

    (101) 0x41ddb8 FADD	Z7.D, Z5.D, Z29.D

    (101) 0x41ddbc FMSB	Z18.D, P0/M, Z1.D, Z22.D

    (101) 0x41ddc0 FADD	Z2.D, Z18.D, Z0.D

    (101) 0x41ddc4 FMUL	Z18.D, Z7.D, Z18.D

    (101) 0x41ddc8 FDIVR	Z2.D, P0/M, Z2.D, Z0.D

    (101) 0x41ddcc FDIVR	Z0.D, P0/M, Z0.D, Z4.D

    (101) 0x41ddd0 FMSB	Z0.D, P0/M, Z18.D, Z16.D

    (101) 0x41ddd4 ST1D	{Z0.D}, P1, [X3, X1,LSL #3]

    (101) 0x41ddd8 LD1D	{Z6.D}, P1/Z, [X0, X1,LSL #3]

    (101) 0x41dddc FMUL	Z17.D, Z2.D, Z6.D

    (101) 0x41dde0 ST1D	{Z17.D}, P1, [X2, X1,LSL #3]

    (101) 0x41dde4 INCD	X1, ALL

    (101) 0x41dde8 WHILELO	P1.D, X1, X4

    (101) 0x41ddec B.NE	41dcec

  (100) 0x41ddf0 LDR	W27, [SP, #136]

  (100) 0x41ddf4 LDR	W26, [SP, #152]

  (100) 0x41ddf8 LDR	W23, [SP, #112]

  (100) 0x41ddfc LDR	X25, [SP, #160]

  (100) 0x41de00 CMP	W27, W26

  (100) 0x41de04 CSEL	W22, W23, W27, #1

  (100) 0x41de08 STR	W22, [SP, #112]

  (100) 0x41de0c LDR	X27, [SP, #168]

  (100) 0x41de10 LDR	X26, [SP, #176]

  (100) 0x41de14 ADD	X14, X14, X25

  (100) 0x41de18 LDR	X21, [SP, #192]

  (100) 0x41de1c ADD	X13, X13, X27

  (100) 0x41de20 ADD	X7, X7, X27

  (100) 0x41de24 LDR	X24, [SP, #200]

  (100) 0x41de28 ADD	X12, X12, X26

  (100) 0x41de2c ADD	X6, X6, X26

  (100) 0x41de30 LDR	W19, [SP, #104]

  (100) 0x41de34 CSINC	W1, W19, WZR, #1

  (100) 0x41de38 ADD	X11, X11, X21

  (100) 0x41de3c ADD	X10, X10, X21

  (100) 0x41de40 STR	W1, [SP, #104]

  (100) 0x41de44 LDR	W20, [SP, #100]

  (100) 0x41de48 ADD	X9, X9, X24

  (100) 0x41de4c ADD	X8, X8, X24

  (100) 0x41de50 LDR	W26, [SP, #144]

  (100) 0x41de54 LDR	X25, [SP, #184]

  (100) 0x41de58 LDR	X24, [SP, #208]

  (100) 0x41de5c LDR	X23, [SP, #216]

  (100) 0x41de60 ADD	X5, X5, X25

  (100) 0x41de64 ADD	X15, X15, X25

  (100) 0x41de68 LDR	X22, [SP, #224]

  (100) 0x41de6c ADD	X30, X30, X24

  (100) 0x41de70 LDR	X21, [SP, #232]

  (100) 0x41de74 ADD	X17, X17, X23

  (100) 0x41de78 LDR	X19, [SP, #240]

  (100) 0x41de7c ADD	X0, X0, X22

  (100) 0x41de80 LDR	X1, [SP, #248]

  (100) 0x41de84 ADD	X16, X16, X21

  (100) 0x41de88 LDR	X27, [SP, #256]

  (100) 0x41de8c ADD	X18, X18, X19

  (100) 0x41de90 ADD	X3, X3, X1

  (100) 0x41de94 ADD	X2, X2, X27

  (100) 0x41de98 CMP	W26, W20

  (100) 0x41de9c B.GT	41dca4

(99) 0x41dea0 LDR	W4, [SP, #104]

(99) 0x41dea4 LDR	X28, [SP, #264]

(99) 0x41dea8 CBZ	W4, 41da78

0x41deac LDP	X19, X20, [SP, #16]

0x41deb0 LDP	X21, X22, [SP, #32]

0x41deb4 LDP	X23, X24, [SP, #48]

0x41deb8 LDP	X25, X26, [SP, #64]

0x41debc LDR	W14, [SP, #112]

0x41dec0 STR	W14, [X28, #360]

0x41dec4 LDP	X27, X28, [SP, #80]

0x41dec8 LDP	X29, X30, [SP], #272

0x41decc RET

0x41ded0 ADD	W27, W27, #1

0x41ded4 MOVZ	W1, #0

0x41ded8 MADD	W11, W27, W0, W1

0x41dedc ADD	W22, W27, W11

0x41dee0 CMP	W11, W22

0x41dee4 B.GE	41da78

0x41dee8 B	41d724

(99) 0x41deec ADD	W27, W27, #1

(99) 0x41def0 MOVZ	W1, #0

(99) 0x41def4 MADD	W24, W27, W0, W1

(99) 0x41def8 ADD	W27, W27, W24

(99) 0x41defc CMP	W24, W27

(99) 0x41df00 B.GE	41da78

(99) 0x41df04 B	41daac

Coverage (%)	Name	Source Location	Module
►50.33+	GOMP_parallel		libgomp.so.1.0.0
○	pdv_kernel	PdV_kernel.f90:145	exec
○	pdv	PdV.f90:58	exec
○	hydro	hydro.f90:56	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec
►49.67+	GOMP_parallel		libgomp.so.1.0.0
○	pdv_kernel	PdV_kernel.f90:145	exec
○	pdv	PdV.f90:58	exec
○	hydro	hydro.f90:60	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	PdV_kernel.f90:67-135
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/PdV_kernel.f90:67-87,93-99,108-123,129-135.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.83 to 3.00 cycles (8.61x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 22% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.83 to 1.00 cycles (25.83x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 508 bytes. The binary function is storing 228 bytes.

General properties

nb instructions	171
loop length	684
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

21.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	21.00	21.00	22.00	21.00	1.50	1.50	0.00	0.00	25.83	25.50	25.67	12.50	12.50
cycles	4.50	4.50	21.00	21.00	22.00	21.00	1.50	1.50	0.00	0.00	25.83	25.50	25.67	12.50	12.50

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	21.38
Overall L1	25.83

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.83 cycles. At this rate:

20% of peak load performance is reached (19.66 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (8.83 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41d660

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #752]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W23, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401b60 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR W22, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 401ad0 <@plt_start@+0x320>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X21, X20, [X19, #152]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X30, [X19, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X17, X13, [X19, #216]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X16, X12, [X19, #232]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X15, X10, [X19, #248]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X14, X4, [X19, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X6, X3, [X19, #280]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W2, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X19, #192]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X19, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W7, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB W11, W7, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X1, [X19, #208]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X18, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SDIV W27, W11, W22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	5-12	1-0.50
LDR X26, [X19, #184]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X28, [SP, #104]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X5, [X19, #296]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X1, [SP, #152]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X19, #312]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X19, #320]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X19, #328]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MSUB W1, W27, W22, W11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR X22, [X19, #304]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X7, X11, [X19, #336]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X28, [X19]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X19, #352]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W28, [X28]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ W28, 41da94 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x434>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W0, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LT 41ded0 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x870>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W11, W27, W0, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD W22, W27, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W11, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 41da78 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W1, W22, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W11, W11, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X28, [X19, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X5, X11, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X0, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
STR W1, [SP, #160]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X22, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X18, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X1, [X19, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X23, X5, X6, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FDUP Z3.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MADD X22, X5, X22, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
STR X0, [SP, #168]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
FDUP Z4.D, #96	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SUB X0, XZR, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR W28, [X28]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FDUP Z19.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
STR X18, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X18, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X27, [X19, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X0, X0, X5, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
STR X18, [SP, #176]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X18, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR W1, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X18, [SP, #184]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X18, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X0, [SP, #192]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X0, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X22, [X19, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [SP, #120]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W1, [SP, #100]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SBFM X1, X28, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X0, X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X3, X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X18, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X2, X20, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X20, X23, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR W23, [SP, #100]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X9, X5, X9, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X10, X10, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X0, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X4, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X2, X21, X5, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X15, X5, X15, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
UBFM X21, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X7, X7, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X9, X22, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X22, [X19, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X13, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W28, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
MADD X16, X16, X5, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR X23, [SP, #152]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X14, X14, X5, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X10, X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X21, [SP, #152]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X18, X5, X8, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR X21, [X19, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X13, X5, X17, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
UBFM X17, X26, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X12, X26, X5, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MOVZ W26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X10, [SP, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X22, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X22, X23, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X1, X30, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR W28, [SP, #104]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X30, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X28, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X6, X5, X6, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X0, X5, X25, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
STR X17, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X17, X18, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X3, [X19, #88]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CNTD X25, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X22, X5, X10, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
UBFM X23, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X10, X27, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X27, [X19, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X5, X5, X8, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
STR X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W8, W7, [SP, #100]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X21, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X12, X3, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X4, [X19, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X27, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X13, [X19, #72]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X0, X18, [X19, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W27, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X3, X4, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CSINC W22, W7, W8, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB W4, W27, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
WHILELO P4.D, XZR, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2
STR X19, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X19, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X13, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X6, X18, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X23, [X19, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X0, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X8, X18, X20,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X5, X21, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X7, X21, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X30, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ W26, 41da78 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR W24, [X30, #360]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W14, [SP, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W14, [X28, #360]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #272	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W27, W27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD W11, W27, W0, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD W22, W27, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W11, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 41da78 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 41d724 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	PdV_kernel.f90:67-135
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 25.83 to 3.00 cycles (8.61x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 22% of vector register length is used (average across all VPU instructions).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers).

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 25.83 to 1.00 cycles (25.83x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 508 bytes. The binary function is storing 228 bytes.

General properties

nb instructions	171
loop length	684
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

21.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.50	4.50	21.00	21.00	22.00	21.00	1.50	1.50	0.00	0.00	25.83	25.50	25.67	12.50	12.50
cycles	4.50	4.50	21.00	21.00	22.00	21.00	1.50	1.50	0.00	0.00	25.83	25.50	25.67	12.50	12.50

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	21.38
Overall L1	25.83

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 25.83 cycles. At this rate:

20% of peak load performance is reached (19.66 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (8.83 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 41d660

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #752]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #24]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W23, [X0]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401b60 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR W22, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
BL 401ad0 <@plt_start@+0x320>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X21, X20, [X19, #152]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X30, [X19, #168]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X17, X13, [X19, #216]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X16, X12, [X19, #232]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X15, X10, [X19, #248]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X14, X4, [X19, #264]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X6, X3, [X19, #280]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W2, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X19, #192]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X28, [X19, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W7, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB W11, W7, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X1, [X19, #208]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X18, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SDIV W27, W11, W22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	5-12	1-0.50
LDR X26, [X19, #184]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X28, [SP, #104]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X5, [X19, #296]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X1, [SP, #152]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X19, #312]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X19, #320]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [X19, #328]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MSUB W1, W27, W22, W11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR X22, [X19, #304]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X7, X11, [X19, #336]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X28, [X19]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X18, [X19, #352]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W28, [X28]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ W28, 41da94 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x434>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W0, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LT 41ded0 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x870>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W11, W27, W0, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD W22, W27, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W11, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 41da78 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W1, W22, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W11, W11, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X28, [X19, #8]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X5, X11, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X0, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
PTRUE P3.B, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
STR W1, [SP, #160]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X22, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X18, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X1, [X19, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X23, X5, X6, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FDUP Z3.D, #80	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
MADD X22, X5, X22, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
STR X0, [SP, #168]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
FDUP Z4.D, #96	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
SUB X0, XZR, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR W28, [X28]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FDUP Z19.D, #112	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
STR X18, [SP, #136]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X18, X15, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X27, [X19, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X0, X0, X5, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
STR X18, [SP, #176]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X18, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR W1, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X18, [SP, #184]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X18, X21, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X0, [SP, #192]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X0, X16, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X22, [X19, #56]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X0, [SP, #120]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W1, [SP, #100]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SBFM X1, X28, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X0, X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X3, X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X18, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X2, X20, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X20, X23, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR W23, [SP, #100]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X9, X5, X9, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X10, X10, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X0, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X4, X4, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X2, X21, X5, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X15, X5, X15, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
UBFM X21, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X7, X7, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X9, X22, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X22, [X19, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X13, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W28, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
MADD X16, X16, X5, X12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR X23, [SP, #152]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X14, X14, X5, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X10, X0, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR X21, [SP, #152]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X18, X5, X8, X8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR X21, [X19, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X13, X5, X17, X13	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
UBFM X17, X26, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X12, X26, X5, X10	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MOVZ W26, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X10, [SP, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X22, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X22, X23, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X1, X30, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR W28, [SP, #104]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X30, X6, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X28, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X6, X5, X6, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X0, X5, X25, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
STR X17, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X17, X18, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X3, [X19, #88]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CNTD X25, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X22, X5, X10, X22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
UBFM X23, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X10, X27, X14,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X27, [X19, #104]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X5, X5, X8, X7	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
STR X23, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP W8, W7, [SP, #100]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X21, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X12, X3, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X4, [X19, #96]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X14, X27, X13,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X13, [X19, #72]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X0, X18, [X19, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W27, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X3, X4, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CSINC W22, W7, W8, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB W4, W27, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
WHILELO P4.D, XZR, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	3	2
STR X19, [SP, #200]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X21, [X19, #136]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X13, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X6, X18, X6,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X23, [X19, #40]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X13, X0, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X8, X18, X20,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X5, X21, X5,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X7, X21, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X30, [SP, #200]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ W26, 41da78 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR W24, [X30, #360]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W14, [SP, #112]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W14, [X28, #360]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #272	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W27, W27, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ W1, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD W11, W27, W0, W1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD W22, W27, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W11, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 41da78 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0x418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 41d724 <__pdv_kernel_module_MOD_pdv_kernel._omp_fn.0+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼pdv_kernel._omp_fn.0–	10.69	2.27
▼Loop 102 - PdV_kernel.f90:78-99 - exec–	0.02	0
○Loop 103 - PdV_kernel.f90:78-99 - exec	5.36	1.14
▼Loop 99 - PdV_kernel.f90:67-135 - exec–	0	0
▼Loop 100 - PdV_kernel.f90:114-135 - exec–	0.02	0
○Loop 101 - PdV_kernel.f90:114-135 - exec	5.29	1.12

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ASM code

Code clean check

Workaround

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code