OV - exec - Function viscosity_kernel._omp

	Function: viscosity_kernel._omp_fn.0	Module: exec	Source: viscosity_kernel.f90:50-89	Coverage: 9.75%

/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/viscosity_kernel.f90: 50 - 89

--------------------------------------------------------------------------------

50:     !$OMP PARALLEL

51:

52:     !$OMP DO PRIVATE(ugrad,vgrad,div,strain2,pgradx,pgrady,pgradx2,pgrady2,limiter,pgrad,xgrad,ygrad,grad,grad2,dirx,diry)

53:     DO k=y_min,y_max

54:     !$OMP SIMD

55:       DO j=x_min,x_max

56:         ugrad=(xvel0(j+1,k  )+xvel0(j+1,k+1))-(xvel0(j  ,k  )+xvel0(j  ,k+1))

57:

58:         vgrad=(yvel0(j  ,k+1)+yvel0(j+1,k+1))-(yvel0(j  ,k  )+yvel0(j+1,k  ))

59:

60:         div = (celldx(j)*(ugrad)+  celldy(k)*(vgrad))

61:

62:         strain2 = 0.5_8*(xvel0(j,  k+1) + xvel0(j+1,k+1)-xvel0(j  ,k  )-xvel0(j+1,k  ))/celldy(k) &

63:           + 0.5_8*(yvel0(j+1,k  ) + yvel0(j+1,k+1)-yvel0(j  ,k  )-yvel0(j  ,k+1))/celldx(j)

64:

65:         pgradx=(pressure(j+1,k)-pressure(j-1,k))/(celldx(j)+celldx(j+1))

66:         pgrady=(pressure(j,k+1)-pressure(j,k-1))/(celldy(k)+celldy(k+1))

67:

68:         pgradx2 = pgradx*pgradx

69:         pgrady2 = pgrady*pgrady

70:

71:         limiter = ((0.5_8*(ugrad)/celldx(j))*pgradx2+(0.5_8*(vgrad)/celldy(k))*pgrady2+strain2*pgradx*pgrady)  &

72:           /MAX(pgradx2+pgrady2,1.0e-16_8)

73:

74:         IF ((limiter.GT.0.0).OR.(div.GE.0.0))THEN

75:           viscosity(j,k) = 0.0

76:         ELSE

77:           dirx=1.0_8

78:           IF(pgradx.LT.0.0) dirx=-1.0_8

79:           pgradx = dirx*MAX(1.0e-16_8,ABS(pgradx))

80:           diry=1.0_8

81:           IF(pgradx.LT.0.0) diry=-1.0_8

82:           pgrady = diry*MAX(1.0e-16_8,ABS(pgrady))

83:           pgrad = SQRT(pgradx**2+pgrady**2)

84:           xgrad = ABS(celldx(j)*pgrad/pgradx)

85:           ygrad = ABS(celldy(k)*pgrad/pgrady)

86:           grad  = MIN(xgrad,ygrad)

87:           grad2 = grad*grad

88:

89:           viscosity(j,k)=2.0_8*density0(j,k)*grad2*limiter*limiter

0x448020 STP	X29, X30, [SP, #816]!

0x448024 ADD	X29, SP, #0

0x448028 STP	X19, X20, [SP, #16]

0x44802c ORR	X19, XZR, X0

0x448030 LDR	X0, [X0, #16]

0x448034 STP	X21, X22, [SP, #32]

0x448038 STP	X23, X24, [SP, #48]

0x44803c LDR	W23, [X0]

0x448040 STP	X25, X26, [SP, #64]

0x448044 BL	401b60

0x448048 LDR	X1, [X19, #104]

0x44804c ORR	W22, WZR, W0

0x448050 LDP	X20, X21, [X19, #88]

0x448054 STR	X1, [SP, #112]

0x448058 BL	401ad0

0x44805c LDR	X3, [X19, #24]

0x448060 LDP	X30, X17, [X19, #112]

0x448064 LDP	X18, X25, [X19, #144]

0x448068 LDP	X26, X16, [X19, #168]

0x44806c LDR	W4, [X3]

0x448070 LDR	X2, [X19, #128]

0x448074 LDR	X7, [X19, #136]

0x448078 ADD	W5, W4, #1

0x44807c SUB	W6, W5, W23

0x448080 LDR	X11, [X19, #160]

0x448084 STR	X2, [SP, #120]

0x448088 SDIV	W8, W6, W22

0x44808c STR	X7, [SP, #104]

0x448090 MSUB	W9, W8, W22, W6

0x448094 CMP	W0, W9

0x448098 B.LT	448404

(852) 0x44809c MADD	W10, W8, W0, W9

(852) 0x4480a0 ADD	W12, W8, W10

(852) 0x4480a4 CMP	W10, W12

(852) 0x4480a8 B.GE	4483ec

0x4480ac LDP	X1, X3, [X19]

0x4480b0 ADD	W13, W23, W10

0x4480b4 ADD	W24, W23, W12

0x4480b8 SBFM	X8, X13, #0, #31

0x4480bc ADRP	X14,

0x4480c0 FMOV	D6, #0.5000000

0x4480c4 STP	X27, X28, [SP, #80]

0x4480c8 UBFM	X28, X25, #61, #60

0x4480cc MADD	X15, X8, X25, X25

0x4480d0 MADD	X0, X8, X26, X26

0x4480d4 MOVZ	W27, #0

0x4480d8 LDR	W10, [X1]

0x4480dc ADD	X23, X15, X11

0x4480e0 LDP	X7, X2, [X19, #32]

0x4480e4 ADD	X22, X0, X16

0x4480e8 MADD	X16, X26, X8, X16

0x4480ec STR	X28, [SP, #144]

0x4480f0 MADD	X28, X25, X8, XZR

0x4480f4 LDR	W12, [X3]

0x4480f8 SBFM	X1, X10, #0, #31

0x4480fc ADD	X20, X20, X1

0x448100 ADD	X3, X1, X11

0x448104 STP	W24, W10, [SP, #132]

0x448108 ADD	X7, X7, X20,LSL #3

0x44810c ADD	X24, X11, X28

0x448110 STR	X19, [SP, #192]

0x448114 LDR	X9, [X19, #48]

0x448118 UBFM	X1, X1, #61, #60

0x44811c ADD	X13, X2, X21,LSL #3

0x448120 MADD	X21, X8, X17, X17

0x448124 SUB	W5, W12, W10

0x448128 LDR	X6, [X19, #72]

0x44812c CMP	W10, W12

0x448130 ADD	X11, X5, X28

0x448134 ADD	W28, W12, #1

0x448138 CSINC	W10, W10, W12, #12

0x44813c LDR	X5, [X19, #56]

0x448140 ADD	X9, X9, X1

0x448144 STR	W12, [SP, #140]

0x448148 LDR	X20, [X19, #80]

0x44814c ADD	X2, X6, #8

0x448150 ADD	X6, X1, X6

0x448154 STR	X9, [SP, #160]

0x448158 LDR	X19, [X19, #64]

0x44815c STR	X6, [SP, #168]

0x448160 LDR	X4, [SP, #112]

0x448164 ADD	X20, X20, X1

0x448168 STR	X7, [SP, #176]

0x44816c LDR	X15, [SP, #104]

0x448170 STR	W10, [SP, #200]

0x448174 LDR	X0, [SP, #120]

0x448178 MADD	X30, X4, X8, X30

0x44817c ADD	X4, X11, X3

0x448180 ADD	X3, X5, X1

0x448184 ADD	X1, X19, X1

0x448188 LDR	W19, [SP, #204]

0x44818c ADD	X11, X2, X4,LSL #3

0x448190 MADD	X18, X15, X8, X18

0x448194 STR	X3, [SP, #184]

0x448198 LDR	D7, [X14, #4048]

0x44819c ADD	X14, X13, #8

0x4481a0 MADD	X15, X17, X8, X0

0x4481a4 ADD	X21, X21, X0

0x4481a8 ADD	X0, X8, #1

0x4481ac STR	X1, [SP, #152]

(853) 0x4481b0 LDP	W12, W4, [SP, #136]

(853) 0x4481b4 CMP	W12, W4

(853) 0x4481b8 B.GT	448368

(853) 0x4481bc LDR	X1, [SP, #120]

(853) 0x4481c0 SUB	W2, W8, #1

(853) 0x4481c4 ADD	X4, X20, X22,LSL #3

(853) 0x4481c8 LDP	X7, X5, [SP, #160]

(853) 0x4481cc SBFM	X10, X2, #0, #31

(853) 0x4481d0 ADD	X3, X20, X16,LSL #3

(853) 0x4481d4 SUB	X12, X21, X15

(853) 0x4481d8 MADD	X10, X10, X17, X1

(853) 0x4481dc LDR	X1, [SP, #184]

(853) 0x4481e0 ADD	X9, X7, X30,LSL #3

(853) 0x4481e4 LDR	X7, [SP, #152]

(853) 0x4481e8 ADD	X2, X5, X24,LSL #3

(853) 0x4481ec ADD	X5, X5, X23,LSL #3

(853) 0x4481f0 SUB	X10, X10, X15

(853) 0x4481f4 LDR	X6, [SP, #176]

(853) 0x4481f8 ADD	X1, X1, X15,LSL #3

(853) 0x4481fc ADD	X7, X7, X18,LSL #3

  (854) 0x448200 LDP	D19, D4, [X3]

  (854) 0x448204 LDP	D17, D5, [X4]

  (854) 0x448208 LDP	D28, D29, [X5]

  (854) 0x44820c LDP	D1, D18, [X2]

  (854) 0x448210 FADD	D0, D19, D4

  (854) 0x448214 FADD	D2, D5, D4

  (854) 0x448218 LDR	D20, [X1, X12,LSL #3]

  (854) 0x44821c FADD	D16, D17, D5

  (854) 0x448220 FADD	D30, D29, D28

  (854) 0x448224 LDR	D23, [X1, X10,LSL #3]

  (854) 0x448228 LDR	D21, [X14, X8,LSL #3]

  (854) 0x44822c FSUB	D3, D2, S19

  (854) 0x448230 FSUB	D25, D16, S0

  (854) 0x448234 LDUR	D22, [X1, #504]

  (854) 0x448238 FSUB	D31, D30, S1

  (854) 0x44823c FSUB	D26, D20, S23

  (854) 0x448240 LDR	D23, [X13, X8,LSL #3]

  (854) 0x448244 FADD	D20, D1, D28

  (854) 0x448248 FADD	D1, D18, D29

  (854) 0x44824c LDP	D28, D2, [X6]

  (854) 0x448250 FSUB	D24, D3, S17

  (854) 0x448254 LDR	D5, [X1, #8]

  (854) 0x448258 FMUL	D17, D25, D6

  (854) 0x44825c FSUB	D18, D31, S18

  (854) 0x448260 FADD	D21, D23, D21

  (854) 0x448264 FSUB	D19, D1, S20

  (854) 0x448268 FADD	D3, D28, D2

  (854) 0x44826c FMUL	D27, D24, D6

  (854) 0x448270 FSUB	D22, D5, S22

  (854) 0x448274 FMUL	D4, D18, D6

  (854) 0x448278 FDIV	D24, D26, D21

  (854) 0x44827c FMUL	D16, D19, D6

  (854) 0x448280 FDIV	D0, D4, D23

  (854) 0x448284 FDIV	D27, D27, D28

  (854) 0x448288 FMUL	D30, D24, D24

  (854) 0x44828c FDIV	D26, D17, D23

  (854) 0x448290 FDIV	D29, D22, D3

  (854) 0x448294 FADD	D31, D0, D27

  (854) 0x448298 FDIV	D18, D16, D28

  (854) 0x44829c FMUL	D1, D26, D30

  (854) 0x4482a0 FMUL	D20, D29, D29

  (854) 0x4482a4 FMUL	D21, D31, D29

  (854) 0x4482a8 FMADD	D0, D20, D18, D1

  (854) 0x4482ac FADD	D4, D20, D30

  (854) 0x4482b0 FMAXNM	D17, D4, D7

  (854) 0x4482b4 FMADD	D16, D24, D21, D0

  (854) 0x4482b8 FDIV	D26, D16, D17

  (854) 0x4482bc FCMPE	D26, #0

  (854) 0x4482c0 B.GT	4483d4

  (854) 0x4482c4 FMUL	D19, D28, D19

  (854) 0x4482c8 FMADD	D25, D23, D25, D19

  (854) 0x4482cc FCMPE	D25, #0

  (854) 0x4482d0 B.GE	4483d4

  (854) 0x4482d4 FCMPE	D29, #0

  (854) 0x4482d8 FABS	D5, D29

  (854) 0x4482dc FMAXNM	D22, D5, D7

  (854) 0x4482e0 B.MI	4483c0

  (854) 0x4482e4 FMOV	D2, #1.0000000

  (854) 0x4482e8 FABS	D24, D24

  (854) 0x4482ec FMAXNM	D3, D24, D7

  (854) 0x4482f0 FMUL	D27, D2, D3

  (854) 0x4482f4 LDR	D21, [X9]

  (854) 0x4482f8 FMUL	D29, D27, D27

  (854) 0x4482fc FADD	D4, D21, D21

  (854) 0x448300 FMADD	D30, D22, D22, D29

  (854) 0x448304 FSQRT	D31, D30

  (854) 0x448308 FMUL	D23, D23, D31

  (854) 0x44830c FMUL	D28, D28, D31

  (854) 0x448310 FDIV	D18, D23, D27

  (854) 0x448314 FDIV	D1, D28, D22

  (854) 0x448318 FABS	D20, D18

  (854) 0x44831c FABS	D17, D1

  (854) 0x448320 FMINNM	D0, D17, D20

  (854) 0x448324 FMUL	D16, D0, D0

  (854) 0x448328 FMUL	D19, D4, D16

  (854) 0x44832c FMUL	D25, D19, D26

  (854) 0x448330 FMUL	D26, D25, D26

  (854) 0x448334 STR	D26, [X7]

  (854) 0x448338 HINT	#0

  (854) 0x44833c HINT	#0

  (854) 0x448340 ADD	X2, X2, #8

  (854) 0x448344 ADD	X5, X5, #8

  (854) 0x448348 ADD	X4, X4, #8

  (854) 0x44834c ADD	X3, X3, #8

  (854) 0x448350 ADD	X6, X6, #8

  (854) 0x448354 ADD	X1, X1, #8

  (854) 0x448358 ADD	X9, X9, #8

  (854) 0x44835c ADD	X7, X7, #8

  (854) 0x448360 CMP	X11, X2

  (854) 0x448364 B.NE	448200

(853) 0x448368 LDR	W12, [SP, #200]

(853) 0x44836c ADD	X24, X24, X25

(853) 0x448370 ADD	X23, X23, X25

(853) 0x448374 ADD	X22, X22, X26

(853) 0x448378 ADD	X16, X16, X26

(853) 0x44837c LDR	W2, [SP, #132]

(853) 0x448380 ADD	X15, X15, X17

(853) 0x448384 ADD	X21, X21, X17

(853) 0x448388 ORR	X8, XZR, X0

(853) 0x44838c LDR	X6, [SP, #104]

(853) 0x448390 CMP	W28, W12

(853) 0x448394 CSEL	W19, W19, W28, #1

(853) 0x448398 CSINC	W27, W27, WZR, #1

(853) 0x44839c LDR	X3, [SP, #112]

(853) 0x4483a0 LDR	X4, [SP, #144]

(853) 0x4483a4 ADD	X18, X18, X6

(853) 0x4483a8 ADD	X30, X30, X3

(853) 0x4483ac ADD	X11, X11, X4

(853) 0x4483b0 CMP	W2, W0

(853) 0x4483b4 B.LE	4483dc

(853) 0x4483b8 ADD	X0, X0, #1

(853) 0x4483bc B	4481b0

  (854) 0x4483c0 FCMPE	D22, #0

  (854) 0x4483c4 FMOV	D2, #-1.0000000

  (854) 0x4483c8 FNEG	D22, D22

  (854) 0x4483cc B.GT	4482e8

  (854) 0x4483d0 B	4482e4

  (854) 0x4483d4 STR	XZR, [X7]

  (854) 0x4483d8 B	448340

0x4483dc LDR	X5, [SP, #192]

0x4483e0 CBZ	W27, 448410

0x4483e4 LDP	X27, X28, [SP, #80]

0x4483e8 STR	W19, [X5, #184]

(852) 0x4483ec LDP	X19, X20, [SP, #16]

(852) 0x4483f0 LDP	X21, X22, [SP, #32]

(852) 0x4483f4 LDP	X23, X24, [SP, #48]

(852) 0x4483f8 LDP	X25, X26, [SP, #64]

(852) 0x4483fc LDP	X29, X30, [SP], #208

(852) 0x448400 RET

(852) 0x448404 ADD	W8, W8, #1

(852) 0x448408 MOVZ	W9, #0

(852) 0x44840c B	44809c

0x448410 LDP	X19, X20, [SP, #16]

0x448414 LDP	X21, X22, [SP, #32]

0x448418 LDP	X23, X24, [SP, #48]

0x44841c LDP	X25, X26, [SP, #64]

0x448420 LDP	X27, X28, [SP, #80]

0x448424 LDP	X29, X30, [SP], #208

0x448428 RET

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	viscosity_kernel	viscosity_kernel.f90:50	exec
○	viscosity	viscosity.f90:38	exec
○	timestep	timestep.f90:76	exec
○	hydro	hydro.f90:54	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	viscosity_kernel.f90:50-89
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/viscosity_kernel.f90:50-89.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.00 to 1.00 cycles (18.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 21% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 18.00 to 2.29 cycles (7.85x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 18.00 to 1.00 cycles (18.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 356 bytes. The binary function is storing 196 bytes.

General properties

nb instructions	107
loop length	428
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	12.50	12.50	12.50	12.50	0.25	0.25	0.25	0.25	18.00	18.00	18.00	10.00	10.00
cycles	2.50	2.50	12.50	12.50	12.50	12.50	0.25	0.25	0.25	0.25	18.00	18.00	18.00	10.00	10.00

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	13.38
Overall L1	18.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.00 cycles. At this rate:

20% of peak load performance is reached (19.78 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.89 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 448020

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #816]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W23, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401b60 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W22, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X21, [X19, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X1, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401ad0 <@plt_start@+0x320>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X3, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X30, X17, [X19, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X18, X25, [X19, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X16, [X19, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W4, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X19, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X19, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W5, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W6, W5, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X19, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X2, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SDIV W8, W6, W22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
STR X7, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MSUB W9, W8, W22, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 448404 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x3e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X1, X3, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W13, W23, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W24, W23, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X8, X13, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X14, <4550bc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D6, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X28, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X15, X8, X25, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X0, X8, X26, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ W27, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W10, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X23, X15, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X7, X2, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X22, X0, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X16, X26, X8, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X28, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X28, X25, X8, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR W12, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X1, X10, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X20, X20, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X1, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W24, W10, [SP, #132]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X7, X7, X20,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X11, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X19, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X1, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X2, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X21, X8, X17, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB W5, W12, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X6, [X19, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W10, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X11, X5, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W28, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W10, W10, W12, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [X19, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X9, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W12, [SP, #140]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X20, [X19, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X6, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X1, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X9, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X19, [X19, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X20, X20, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X7, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W10, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X30, X4, X8, X30	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X4, X11, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X5, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X19, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W19, [SP, #204]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X2, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X18, X15, X8, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X3, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR D7, [X14, #4048]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X14, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X15, X17, X8, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X21, X21, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X1, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X5, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ W27, 448410 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x3f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR W19, [X5, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #208	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	viscosity_kernel.f90:50-89
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/viscosity_kernel.f90:50-89.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 18.00 to 1.00 cycles (18.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 356 bytes. The binary function is storing 196 bytes.

General properties

nb instructions	107
loop length	428
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

13.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	12.50	12.50	12.50	12.50	0.25	0.25	0.25	0.25	18.00	18.00	18.00	10.00	10.00
cycles	2.50	2.50	12.50	12.50	12.50	12.50	0.25	0.25	0.25	0.25	18.00	18.00	18.00	10.00	10.00

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	13.38
Overall L1	18.00

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.00 cycles. At this rate:

20% of peak load performance is reached (19.78 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.89 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 448020

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #816]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X19, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W23, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401b60 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [X19, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W22, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X21, [X19, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X1, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401ad0 <@plt_start@+0x320>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X3, [X19, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X30, X17, [X19, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X18, X25, [X19, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X16, [X19, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W4, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X2, [X19, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X7, [X19, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W5, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W6, W5, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X11, [X19, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X2, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
SDIV W8, W6, W22	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
STR X7, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MSUB W9, W8, W22, W6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W0, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 448404 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x3e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X1, X3, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W13, W23, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W24, W23, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SBFM X8, X13, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADRP X14, <4550bc>	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FMOV D6, #0.5000000	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X28, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X15, X8, X25, X25	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X0, X8, X26, X26	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MOVZ W27, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W10, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X23, X15, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X7, X2, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X22, X0, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X16, X26, X8, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X28, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MADD X28, X25, X8, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR W12, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X1, X10, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X20, X20, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X1, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP W24, W10, [SP, #132]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X7, X7, X20,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X11, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X9, [X19, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
UBFM X1, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X2, X21,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X21, X8, X17, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB W5, W12, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X6, [X19, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W10, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X11, X5, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W28, W12, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W10, W10, W12, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X5, [X19, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X9, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W12, [SP, #140]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X20, [X19, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X6, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X1, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X9, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X19, [X19, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X6, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X4, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X20, X20, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X7, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X15, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR W10, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X0, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X30, X4, X8, X30	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X4, X11, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X5, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X19, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W19, [SP, #204]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X2, X4,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X18, X15, X8, X18	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
STR X3, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR D7, [X14, #4048]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X14, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X15, X17, X8, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X21, X21, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X1, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X5, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ W27, 448410 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x3f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR W19, [X5, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X29, X30, [SP], #208	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼viscosity_kernel._omp_fn.0–	9.75	2.08
▼Loop 853 - viscosity_kernel.f90:56-89 - exec–	0	0
○Loop 854 - viscosity_kernel.f90:56-89 - exec	9.75	2.08
○Loop 852 - viscosity_kernel.f90:50-52 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code