OV - exec - Function revert_kernel._omp

	Function: revert_kernel._omp_fn.0	Module: exec	Source: revert_kernel.f90:41-48	Coverage: 1.06%

/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/revert_kernel.f90: 41 - 48

--------------------------------------------------------------------------------

41:     !$OMP PARALLEL

42:

43:     !$OMP DO

44:     DO k=y_min,y_max

45:     !$OMP SIMD

46:       DO j=x_min,x_max

47:         density1(j,k)=density0(j,k)

48:         energy1(j,k)=energy0(j,k)

0x42e080 STP	X29, X30, [SP, #944]!

0x42e084 ADD	X29, SP, #0

0x42e088 STP	X21, X22, [SP, #32]

0x42e08c ORR	X22, XZR, X0

0x42e090 LDR	X0, [X0, #16]

0x42e094 STP	X19, X20, [SP, #16]

0x42e098 STP	X23, X24, [SP, #48]

0x42e09c LDP	X21, X19, [X22, #64]

0x42e0a0 STR	X25, [SP, #64]

0x42e0a4 LDR	W25, [X0]

0x42e0a8 BL	401b60

0x42e0ac ORR	W24, WZR, W0

0x42e0b0 BL	401ad0

0x42e0b4 LDR	X1, [X22, #24]

0x42e0b8 ORR	W8, WZR, W0

0x42e0bc LDP	X20, X2, [X22, #80]

0x42e0c0 LDP	X18, X4, [X22, #96]

0x42e0c4 LDP	X17, X30, [X22, #112]

0x42e0c8 LDR	W3, [X1]

0x42e0cc ADD	W5, W3, #1

0x42e0d0 SUB	W6, W5, W25

0x42e0d4 SDIV	W7, W6, W24

0x42e0d8 MSUB	W9, W7, W24, W6

0x42e0dc CMP	W0, W9

0x42e0e0 B.LT	42e1f4

(399) 0x42e0e4 MADD	W10, W7, W8, W9

(399) 0x42e0e8 ADD	W11, W7, W10

(399) 0x42e0ec CMP	W10, W11

(399) 0x42e0f0 B.GE	42e1dc

(399) 0x42e0f4 ADD	W8, W25, W10

(399) 0x42e0f8 ADD	W9, W25, W11

(399) 0x42e0fc LDP	X25, X3, [X22]

(399) 0x42e100 SBFM	X1, X8, #0, #31

(399) 0x42e104 UBFM	X16, X21, #61, #60

(399) 0x42e108 UBFM	X15, X20, #61, #60

(399) 0x42e10c MOVZ	W12, #1

(399) 0x42e110 MOVZ	W0, #0

(399) 0x42e114 CNTD	X7, ALL

(399) 0x42e118 LDR	X24, [X22, #32]

(399) 0x42e11c UBFM	X13, X17, #61, #60

(399) 0x42e120 UBFM	X14, X18, #61, #60

(399) 0x42e124 LDR	W10, [X25]

(399) 0x42e128 LDR	W11, [X3]

(399) 0x42e12c SBFM	X25, X10, #0, #31

(399) 0x42e130 ADD	X2, X2, X25

(399) 0x42e134 ADD	X19, X19, X25

(399) 0x42e138 ADD	X30, X30, X25

(399) 0x42e13c ADD	X4, X4, X25

(399) 0x42e140 MADD	X21, X1, X21, X19

(399) 0x42e144 LDP	X25, X19, [X22, #40]

(399) 0x42e148 CMP	W10, W11

(399) 0x42e14c MADD	X3, X1, X20, X2

(399) 0x42e150 MADD	X5, X1, X18, X4

(399) 0x42e154 CSINC	W18, W10, W11, #12

(399) 0x42e158 MADD	X1, X1, X17, X30

(399) 0x42e15c ADD	W17, W11, W12

(399) 0x42e160 LDR	X20, [X22, #56]

(399) 0x42e164 ADD	X6, X24, X21,LSL #3

(399) 0x42e168 SUB	W24, W17, W10

(399) 0x42e16c ADD	X30, X25, X3,LSL #3

(399) 0x42e170 WHILELO	P1.D, XZR, X24

(399) 0x42e174 ADD	X21, X19, X5,LSL #3

(399) 0x42e178 ADD	X2, X20, X1,LSL #3

(399) 0x42e17c HINT	#0

  (400) 0x42e180 MOVZ	X4, #0

  (400) 0x42e184 ORR	P0.B, P1/Z, P1.B, P1.B

  (400) 0x42e188 CMP	W10, W11

  (400) 0x42e18c B.GT	42e1ac

    (401) 0x42e190 LD1D	{Z0.D}, P0/Z, [X6, X4,LSL #3]

    (401) 0x42e194 ST1D	{Z0.D}, P0, [X30, X4,LSL #3]

    (401) 0x42e198 LD1D	{Z1.D}, P0/Z, [X21, X4,LSL #3]

    (401) 0x42e19c ST1D	{Z1.D}, P0, [X2, X4,LSL #3]

    (401) 0x42e1a0 ADD	X4, X4, X7

    (401) 0x42e1a4 WHILELO	P0.D, X4, X24

    (401) 0x42e1a8 B.NE	42e190

  (400) 0x42e1ac CMP	W17, W18

  (400) 0x42e1b0 ADD	W8, W8, #1

  (400) 0x42e1b4 CSEL	W23, W23, W17, #1

  (400) 0x42e1b8 ADD	X6, X6, X16

  (400) 0x42e1bc ADD	X30, X30, X15

  (400) 0x42e1c0 CSEL	W0, W0, W12, #1

  (400) 0x42e1c4 ADD	X21, X21, X14

  (400) 0x42e1c8 ADD	X2, X2, X13

  (400) 0x42e1cc CMP	W9, W8

  (400) 0x42e1d0 B.GT	42e180

(399) 0x42e1d4 CBZ	W0, 42e1dc

0x42e1d8 STR	W23, [X22, #128]

(399) 0x42e1dc LDP	X19, X20, [SP, #16]

(399) 0x42e1e0 LDP	X21, X22, [SP, #32]

(399) 0x42e1e4 LDP	X23, X24, [SP, #48]

(399) 0x42e1e8 LDR	X25, [SP, #64]

(399) 0x42e1ec LDP	X29, X30, [SP], #80

(399) 0x42e1f0 RET

(399) 0x42e1f4 ADD	W7, W7, #1

(399) 0x42e1f8 MOVZ	W9, #0

(399) 0x42e1fc B	42e0e4

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	revert_kernel	revert_kernel.f90:55	exec
○	revert	revert.f90:37	exec
○	pdv	PdV.f90:137	exec
○	hydro	hydro.f90:56	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	revert_kernel.f90:41-48
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/revert_kernel.f90:41-48.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 14% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 4.67 to 0.58 cycles (8.00x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.67 to 1.00 cycles (4.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 88 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	26
loop length	104
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	4.67	4.67	4.67	3.00	3.00
cycles	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	4.67	4.67	4.67	3.00	3.00

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.25
Overall L1	4.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.67 cycles. At this rate:

19% of peak load performance is reached (18.86 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.29 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42e080

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X21, X19, [X22, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X25, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W25, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 401b60 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 401ad0 <@plt_start@+0x320>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X1, [X22, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W8, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDP X20, X2, [X22, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X18, X4, [X22, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X17, X30, [X22, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W3, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W5, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W6, W5, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W7, W6, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W9, W7, W24, W6	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 42e1f4 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR W23, [X22, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50

Source file and lines	revert_kernel.f90:41-48
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/revert_kernel.f90:41-48.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.67 to 1.00 cycles (4.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 88 bytes. The binary function is storing 76 bytes.

General properties

nb instructions	26
loop length	104
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	4.67	4.67	4.67	3.00	3.00
cycles	1.50	1.50	3.00	3.00	3.00	3.00	0.00	0.00	0.00	0.00	4.67	4.67	4.67	3.00	3.00

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	3.25
Overall L1	4.67

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.67 cycles. At this rate:

19% of peak load performance is reached (18.86 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (16.29 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42e080

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #944]!	1	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X22, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X21, X19, [X22, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X25, [SP, #64]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W25, [X0]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
BL 401b60 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
ORR W24, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
BL 401ad0 <@plt_start@+0x320>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X1, [X22, #24]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR W8, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDP X20, X2, [X22, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X18, X4, [X22, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X17, X30, [X22, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W3, [X1]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W5, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W6, W5, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SDIV W7, W6, W24	1	0	0	0	0	1	0	0	0	0	0	0	5-12	1-0.50
MSUB W9, W7, W24, W6	1	0	0	0	0	1	0	0	0	0	0	0	2	1
CMP W0, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 42e1f4 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x174>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
STR W23, [X22, #128]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50

Name	Coverage (%)	Time (s)
▼revert_kernel._omp_fn.0–	1.06	0.22
▼Loop 399 - revert_kernel.f90:41-48 - exec–	0	0
▼Loop 400 - revert_kernel.f90:45-48 - exec–	0	0
○Loop 401 - revert_kernel.f90:47-48 - exec	1.06	0.22

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code