OV - exec - Function reset_field_kernel._omp

	Function: reset_field_kernel._omp_fn.0	Module: exec	Source: reset_field_kernel.f90:47-63	Coverage: 2.04%

/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/reset_field_kernel.f90: 47 - 63

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47:     !$OMP PARALLEL

48:     !$OMP DO

49:     DO k=y_min,y_max

50:     !$OMP SIMD

51:       DO j=x_min,x_max

52:         density0(j,k)=density1(j,k)

53:         energy0(j,k)=energy1(j,k)

54:       ENDDO

55:     ENDDO

56:     !$OMP END DO

57:

58:     !$OMP DO

59:     DO k=y_min,y_max+1

60:     !$OMP SIMD

61:       DO j=x_min,x_max+1

62:         xvel0(j,k)=xvel1(j,k)

63:         yvel0(j,k)=yvel1(j,k)

0x42d960 STP	X29, X30, [SP, #880]!

0x42d964 ADD	X29, SP, #0

0x42d968 STP	X25, X26, [SP, #64]

0x42d96c ORR	X26, XZR, X0

0x42d970 LDR	X0, [X0, #16]

0x42d974 LDP	X25, X1, [X26, #96]

0x42d978 STP	X19, X20, [SP, #16]

0x42d97c LDR	W19, [X0]

0x42d980 STP	X21, X22, [SP, #32]

0x42d984 STP	X23, X24, [SP, #48]

0x42d988 STP	X27, X28, [SP, #80]

0x42d98c STR	X1, [SP, #96]

0x42d990 BL	401b60

0x42d994 ORR	W20, WZR, W0

0x42d998 BL	401ad0

0x42d99c LDR	X4, [X26, #24]

0x42d9a0 LDP	X23, X5, [X26, #160]

0x42d9a4 LDP	X24, X3, [X26, #112]

0x42d9a8 STR	X5, [SP, #136]

0x42d9ac LDR	W6, [X4]

0x42d9b0 LDP	X18, X30, [X26, #128]

0x42d9b4 LDP	X17, X2, [X26, #144]

0x42d9b8 ADD	W7, W6, #1

0x42d9bc SUB	W8, W7, W19

0x42d9c0 SDIV	W13, W8, W20

0x42d9c4 LDR	X9, [X26, #184]

0x42d9c8 LDR	X10, [X26, #200]

0x42d9cc LDR	X11, [X26, #208]

0x42d9d0 STR	X9, [SP, #128]

0x42d9d4 LDR	X12, [X26, #216]

0x42d9d8 STR	X10, [SP, #120]

0x42d9dc LDR	X22, [X26, #176]

0x42d9e0 STR	X11, [SP, #112]

0x42d9e4 MSUB	W14, W13, W20, W8

0x42d9e8 LDR	X21, [X26, #192]

0x42d9ec STR	X12, [SP, #104]

0x42d9f0 CMP	W0, W14

0x42d9f4 B.LT	42dc54

0x42d9f8 MADD	W15, W13, W0, W14

0x42d9fc ADD	W16, W13, W15

0x42da00 CMP	W15, W16

0x42da04 B.GE	42dafc

0x42da08 ADD	W4, W19, W15

0x42da0c ADD	W7, W19, W16

0x42da10 LDP	X19, X1, [X26]

0x42da14 SBFM	X16, X4, #0, #31

0x42da18 UBFM	X13, X17, #61, #60

0x42da1c UBFM	X15, X24, #61, #60

0x42da20 UBFM	X14, X25, #61, #60

0x42da24 MOVZ	W11, #1

0x42da28 MOVZ	W6, #0

0x42da2c CNTD	X5, ALL

0x42da30 UBFM	X12, X18, #61, #60

0x42da34 LDR	W8, [X19]

0x42da38 LDR	W10, [X1]

0x42da3c SBFM	X1, X8, #0, #31

0x42da40 ADD	X2, X2, X1

0x42da44 ADD	X3, X3, X1

0x42da48 ADD	X30, X30, X1

0x42da4c CMP	W8, W10

0x42da50 MADD	X2, X16, X17, X2

0x42da54 LDR	X17, [SP, #96]

0x42da58 MADD	X9, X24, X16, X3

0x42da5c LDR	X24, [X26, #40]

0x42da60 ADD	X19, X17, X1

0x42da64 MADD	X1, X16, X18, X30

0x42da68 LDR	X30, [X26, #56]

0x42da6c ADD	W18, W10, W11

0x42da70 ADD	X3, X24, X9,LSL #3

0x42da74 SUB	W17, W18, W8

0x42da78 MADD	X9, X16, X25, X19

0x42da7c LDR	X16, [X26, #32]

0x42da80 CSINC	W19, W8, W10, #12

0x42da84 WHILELO	P1.D, XZR, X17

0x42da88 LDR	X25, [X26, #48]

0x42da8c ADD	X2, X30, X2,LSL #3

0x42da90 ADD	X16, X16, X9,LSL #3

0x42da94 ADD	X24, X25, X1,LSL #3

0x42da98 HINT	#0

0x42da9c HINT	#0

(389) 0x42daa0 MOVZ	X9, #0

(389) 0x42daa4 ORR	P0.B, P1/Z, P1.B, P1.B

(389) 0x42daa8 CMP	W8, W10

(389) 0x42daac B.GT	42dacc

  (390) 0x42dab0 LD1D	{Z0.D}, P0/Z, [X3, X9,LSL #3]

  (390) 0x42dab4 ST1D	{Z0.D}, P0, [X16, X9,LSL #3]

  (390) 0x42dab8 LD1D	{Z1.D}, P0/Z, [X2, X9,LSL #3]

  (390) 0x42dabc ST1D	{Z1.D}, P0, [X24, X9,LSL #3]

  (390) 0x42dac0 ADD	X9, X9, X5

  (390) 0x42dac4 WHILELO	P0.D, X9, X17

  (390) 0x42dac8 B.NE	42dab0

(389) 0x42dacc CMP	W18, W19

(389) 0x42dad0 ADD	W4, W4, #1

(389) 0x42dad4 CSEL	W27, W27, W18, #1

(389) 0x42dad8 ADD	X3, X3, X15

(389) 0x42dadc ADD	X16, X16, X14

(389) 0x42dae0 CSEL	W6, W6, W11, #1

(389) 0x42dae4 ADD	X2, X2, X13

(389) 0x42dae8 ADD	X24, X24, X12

(389) 0x42daec CMP	W7, W4

(389) 0x42daf0 B.GT	42daa0

0x42daf4 CBZ	W6, 42dafc

0x42daf8 STR	W27, [X26, #224]

0x42dafc STR	W0, [SP, #96]

0x42db00 BL	401b40

0x42db04 LDP	X0, X7, [X26, #16]

0x42db08 LDR	W27, [SP, #96]

0x42db0c LDR	W14, [X7]

0x42db10 LDR	W15, [X0]

0x42db14 ADD	W13, W14, #2

0x42db18 SUB	W12, W13, W15

0x42db1c SDIV	W11, W12, W20

0x42db20 MSUB	W20, W11, W20, W12

0x42db24 CMP	W27, W20

0x42db28 B.LT	42dc48

(386) 0x42db2c MADD	W10, W11, W27, W20

(386) 0x42db30 ADD	W8, W11, W10

(386) 0x42db34 CMP	W10, W8

(386) 0x42db38 B.GE	42dc2c

(386) 0x42db3c LDP	X18, X17, [X26]

(386) 0x42db40 ADD	W5, W15, W10

(386) 0x42db44 ADD	W25, W15, W8

(386) 0x42db48 SBFM	X30, X5, #0, #31

(386) 0x42db4c UBFM	X9, X22, #61, #60

(386) 0x42db50 UBFM	X24, X23, #61, #60

(386) 0x42db54 UBFM	X27, X21, #61, #60

(386) 0x42db58 LDP	X11, X2, [SP, #120]

(386) 0x42db5c MOVZ	W8, #0

(386) 0x42db60 CNTD	X6, ALL

(386) 0x42db64 MOVZ	W14, #1

(386) 0x42db68 LDP	X1, X19, [X26, #64]

(386) 0x42db6c LDP	X0, X13, [SP, #104]

(386) 0x42db70 LDR	W7, [X18]

(386) 0x42db74 UBFM	X12, X13, #61, #60

(386) 0x42db78 LDR	W4, [X17]

(386) 0x42db7c LDR	X18, [X26, #80]

(386) 0x42db80 SBFM	X3, X7, #0, #31

(386) 0x42db84 ADD	X15, X2, X3

(386) 0x42db88 ADD	X20, X0, X3

(386) 0x42db8c LDR	X0, [X26, #88]

(386) 0x42db90 ADD	W16, W4, #2

(386) 0x42db94 MADD	X22, X30, X22, X15

(386) 0x42db98 CMP	W16, W7

(386) 0x42db9c CSEL	W17, W16, W7, #10

(386) 0x42dba0 MADD	X10, X30, X13, X20

(386) 0x42dba4 ADD	X15, X19, X22,LSL #3

(386) 0x42dba8 LDR	X19, [SP, #136]

(386) 0x42dbac ADD	X2, X0, X10,LSL #3

(386) 0x42dbb0 ADD	X4, X19, X3

(386) 0x42dbb4 ADD	X3, X11, X3

(386) 0x42dbb8 MADD	X23, X30, X23, X4

(386) 0x42dbbc MADD	X21, X30, X21, X3

(386) 0x42dbc0 SUB	W30, W16, W7

(386) 0x42dbc4 WHILELO	P2.D, XZR, X30

(386) 0x42dbc8 ADD	X11, X1, X23,LSL #3

(386) 0x42dbcc ADD	X1, X18, X21,LSL #3

  (387) 0x42dbd0 MOVZ	X13, #0

  (387) 0x42dbd4 ORR	P3.B, P2/Z, P2.B, P2.B

  (387) 0x42dbd8 CMP	W16, W7

  (387) 0x42dbdc B.LE	42dbfc

    (388) 0x42dbe0 LD1D	{Z2.D}, P3/Z, [X15, X13,LSL #3]

    (388) 0x42dbe4 ST1D	{Z2.D}, P3, [X11, X13,LSL #3]

    (388) 0x42dbe8 LD1D	{Z3.D}, P3/Z, [X2, X13,LSL #3]

    (388) 0x42dbec ST1D	{Z3.D}, P3, [X1, X13,LSL #3]

    (388) 0x42dbf0 ADD	X13, X13, X6

    (388) 0x42dbf4 WHILELO	P3.D, X13, X30

    (388) 0x42dbf8 B.NE	42dbe0

  (387) 0x42dbfc CMP	W16, W7

  (387) 0x42dc00 ADD	W5, W5, #1

  (387) 0x42dc04 CSEL	W28, W28, W17, #11

  (387) 0x42dc08 ADD	X15, X15, X9

  (387) 0x42dc0c ADD	X11, X11, X24

  (387) 0x42dc10 CSEL	W8, W8, W14, #11

  (387) 0x42dc14 ADD	X2, X2, X12

  (387) 0x42dc18 ADD	X1, X1, X27

  (387) 0x42dc1c CMP	W25, W5

  (387) 0x42dc20 B.GT	42dbd0

(386) 0x42dc24 CBZ	W8, 42dc2c

0x42dc28 STR	W28, [X26, #224]

(386) 0x42dc2c LDP	X19, X20, [SP, #16]

(386) 0x42dc30 LDP	X21, X22, [SP, #32]

(386) 0x42dc34 LDP	X23, X24, [SP, #48]

(386) 0x42dc38 LDP	X25, X26, [SP, #64]

(386) 0x42dc3c LDP	X27, X28, [SP, #80]

(386) 0x42dc40 LDP	X29, X30, [SP], #144

(386) 0x42dc44 RET

(386) 0x42dc48 ADD	W11, W11, #1

(386) 0x42dc4c MOVZ	W20, #0

(386) 0x42dc50 B	42db2c

0x42dc54 ADD	W13, W13, #1

0x42dc58 MOVZ	W14, #0

0x42dc5c B	42d9f8

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	reset_field_kernel	reset_field_kernel.f90:47	exec
○	reset_field	reset_field.f90:41	exec
○	hydro	hydro.f90:68	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	reset_field_kernel.f90:47-63
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/reset_field_kernel.f90:47-63.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 17% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 14.17 to 1.94 cycles (7.31x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.17 to 1.50 cycles (9.44x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 244 bytes. The binary function is storing 156 bytes.

General properties

nb instructions	98
loop length	392
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

12.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	12.50	12.50	12.50	12.50	0.00	0.00	0.00	0.00	14.17	13.83	14.00	7.50	7.50
cycles	4.00	4.00	12.50	12.50	12.50	12.50	0.00	0.00	0.00	0.00	14.17	13.83	14.00	7.50	7.50

Cycles executing div or sqrt instructions

2.00-1.00

Cycles summary

Front-end	12.00
Overall L1	14.17

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.17 cycles. At this rate:

17% of peak load performance is reached (17.22 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (11.01 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42d960

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #880]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X25, X1, [X26, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X1, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401b60 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 401ad0 <@plt_start@+0x320>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X4, [X26, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X23, X5, [X26, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X3, [X26, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X5, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W6, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X18, X30, [X26, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X17, X2, [X26, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W7, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W7, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W13, W8, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
LDR X9, [X26, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X26, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X26, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X26, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X22, [X26, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X11, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MSUB W14, W13, W20, W8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X21, [X26, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X12, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W0, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42dc54 <__reset_field_kernel_module_MOD_reset_field_kernel._omp_fn.0+0x2f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W15, W13, W0, W14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W16, W13, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W15, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 42dafc <__reset_field_kernel_module_MOD_reset_field_kernel._omp_fn.0+0x19c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W4, W19, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W7, W19, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X19, X1, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SBFM X16, X4, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X13, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X15, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X14, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X5, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X12, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W10, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X1, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X30, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X2, X16, X17, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X17, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X9, X24, X16, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X24, [X26, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X19, X17, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X1, X16, X18, X30	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X30, [X26, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W18, W10, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X24, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W17, W18, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X9, X16, X25, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X16, [X26, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CSINC W19, W8, W10, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
WHILELO P1.D, XZR, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
LDR X25, [X26, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X30, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X16, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X25, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
CBZ W6, 42dafc <__reset_field_kernel_module_MOD_reset_field_kernel._omp_fn.0+0x19c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR W27, [X26, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401b40 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X0, X7, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W27, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W14, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W15, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W13, W14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W13, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W11, W12, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W20, W11, W20, W12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W27, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42dc48 <__reset_field_kernel_module_MOD_reset_field_kernel._omp_fn.0+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR W28, [X26, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W13, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42d9f8 <__reset_field_kernel_module_MOD_reset_field_kernel._omp_fn.0+0x98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines	reset_field_kernel.f90:47-63
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/reset_field_kernel.f90:47-63.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 14.17 to 1.50 cycles (9.44x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 244 bytes. The binary function is storing 156 bytes.

General properties

nb instructions	98
loop length	392
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

12.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	12.50	12.50	12.50	12.50	0.00	0.00	0.00	0.00	14.17	13.83	14.00	7.50	7.50
cycles	4.00	4.00	12.50	12.50	12.50	12.50	0.00	0.00	0.00	0.00	14.17	13.83	14.00	7.50	7.50

Cycles executing div or sqrt instructions

2.00-1.00

Cycles summary

Front-end	12.00
Overall L1	14.17

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 14.17 cycles. At this rate:

17% of peak load performance is reached (17.22 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (11.01 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 42d960

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
STP X29, X30, [SP, #880]!	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X29, SP, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X26, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X0, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X25, X1, [X26, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W19, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X1, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401b60 <@plt_start@+0x3b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W20, WZR, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
BL 401ad0 <@plt_start@+0x320>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X4, [X26, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X23, X5, [X26, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X24, X3, [X26, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
STR X5, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR W6, [X4]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X18, X30, [X26, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X17, X2, [X26, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD W7, W6, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W8, W7, W19	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W13, W8, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
LDR X9, [X26, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X10, [X26, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [X26, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X12, [X26, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X10, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X22, [X26, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X11, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
MSUB W14, W13, W20, W8	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X21, [X26, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X12, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
CMP W0, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42dc54 <__reset_field_kernel_module_MOD_reset_field_kernel._omp_fn.0+0x2f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MADD W15, W13, W0, W14	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W16, W13, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W15, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GE 42dafc <__reset_field_kernel_module_MOD_reset_field_kernel._omp_fn.0+0x19c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W4, W19, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W7, W19, W16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X19, X1, [X26]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SBFM X16, X4, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X13, X17, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X15, X24, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X14, X25, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W6, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CNTD X5, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
UBFM X12, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W10, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SBFM X1, X8, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X30, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W8, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
MADD X2, X16, X17, X2	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X17, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X9, X24, X16, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X24, [X26, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X19, X17, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X1, X16, X18, X30	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X30, [X26, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W18, W10, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X24, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W17, W18, W8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MADD X9, X16, X25, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDR X16, [X26, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CSINC W19, W8, W10, #12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
WHILELO P1.D, XZR, X17	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	2
LDR X25, [X26, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X30, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X16, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X25, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
CBZ W6, 42dafc <__reset_field_kernel_module_MOD_reset_field_kernel._omp_fn.0+0x19c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR W27, [X26, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR W0, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
BL 401b40 <@plt_start@+0x390>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X0, X7, [X26, #16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR W27, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W14, [X7]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W15, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W13, W14, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W13, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SDIV W11, W12, W20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-12	1-0.50
MSUB W20, W11, W20, W12	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
CMP W27, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 42dc48 <__reset_field_kernel_module_MOD_reset_field_kernel._omp_fn.0+0x2e8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
STR W28, [X26, #224]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W13, W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 42d9f8 <__reset_field_kernel_module_MOD_reset_field_kernel._omp_fn.0+0x98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Name	Coverage (%)	Time (s)
▼reset_field_kernel._omp_fn.0–	2.04	0.43
▼Loop 386 - reset_field_kernel.f90:47-63 - exec–	0	0
▼Loop 387 - reset_field_kernel.f90:60-63 - exec–	0	0
○Loop 388 - reset_field_kernel.f90:62-63 - exec	0.99	0.21
▼Loop 389 - reset_field_kernel.f90:50-53 - exec–	0	0
○Loop 390 - reset_field_kernel.f90:52-53 - exec	1.06	0.22

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Vectorization

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

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Cycles summary

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Cycles and memory resources usage

ASM code