OV - exec - Loop 912

	Loop Id: 912	Module: exec	Source: viscosity_kernel.f90:54-89	Coverage: 0.01%

0x44ab20 LDR	W12, [SP, #128]

0x44ab24 CMP	W12, W27

0x44ab28 B.GT	44acd0

0x44ab2c LDR	X1, [SP, #120]

0x44ab30 SUB	W5, W8, #1

0x44ab34 ADD	X2, X28, X24,LSL #3

0x44ab38 SBFM	X9, X5, #0, #31

0x44ab3c ADD	X4, X20, X22,LSL #3

0x44ab40 SUB	X12, X21, X15

0x44ab44 LDR	X7, [SP, #152]

0x44ab48 ADD	X5, X28, X23,LSL #3

0x44ab4c ADD	X3, X20, X16,LSL #3

0x44ab50 LDR	X6, [SP, #168]

0x44ab54 MADD	X10, X9, X17, X1

0x44ab58 LDR	X1, [SP, #160]

0x44ab5c ADD	X9, X7, X30,LSL #3

0x44ab60 LDR	X7, [SP, #144]

0x44ab64 SUB	X10, X10, X15

0x44ab68 ADD	X1, X1, X15,LSL #3

0x44ab6c ADD	X7, X7, X18,LSL #3

  (913) 0x44ab70 LDP	D19, D4, [X3]

  (913) 0x44ab74 LDP	D17, D5, [X4]

  (913) 0x44ab78 LDP	D28, D29, [X5]

  (913) 0x44ab7c LDP	D1, D18, [X2]

  (913) 0x44ab80 FADD	D0, D19, D4

  (913) 0x44ab84 FADD	D2, D5, D4

  (913) 0x44ab88 LDR	D20, [X1, X12,LSL #3]

  (913) 0x44ab8c FADD	D16, D17, D5

  (913) 0x44ab90 FADD	D30, D29, D28

  (913) 0x44ab94 LDR	D23, [X1, X10,LSL #3]

  (913) 0x44ab98 LDR	D21, [X14, X8,LSL #3]

  (913) 0x44ab9c FSUB	D3, D2, S19

  (913) 0x44aba0 FSUB	D25, D16, S0

  (913) 0x44aba4 LDUR	D22, [X1, #504]

  (913) 0x44aba8 FSUB	D31, D30, S1

  (913) 0x44abac FSUB	D26, D20, S23

  (913) 0x44abb0 LDR	D23, [X13, X8,LSL #3]

  (913) 0x44abb4 FADD	D20, D1, D28

  (913) 0x44abb8 FADD	D1, D18, D29

  (913) 0x44abbc LDP	D28, D2, [X6]

  (913) 0x44abc0 FSUB	D24, D3, S17

  (913) 0x44abc4 LDR	D5, [X1, #8]

  (913) 0x44abc8 FMUL	D17, D25, D6

  (913) 0x44abcc FSUB	D18, D31, S18

  (913) 0x44abd0 FADD	D21, D23, D21

  (913) 0x44abd4 FSUB	D19, D1, S20

  (913) 0x44abd8 FADD	D3, D28, D2

  (913) 0x44abdc FMUL	D27, D24, D6

  (913) 0x44abe0 FSUB	D22, D5, S22

  (913) 0x44abe4 FMUL	D4, D18, D6

  (913) 0x44abe8 FDIV	D24, D26, D21

  (913) 0x44abec FMUL	D16, D19, D6

  (913) 0x44abf0 FDIV	D0, D4, D23

  (913) 0x44abf4 FDIV	D27, D27, D28

  (913) 0x44abf8 FMUL	D30, D24, D24

  (913) 0x44abfc FDIV	D26, D17, D23

  (913) 0x44ac00 FDIV	D29, D22, D3

  (913) 0x44ac04 FADD	D31, D0, D27

  (913) 0x44ac08 FDIV	D18, D16, D28

  (913) 0x44ac0c FMUL	D1, D26, D30

  (913) 0x44ac10 FMUL	D20, D29, D29

  (913) 0x44ac14 FMUL	D21, D31, D29

  (913) 0x44ac18 FMADD	D0, D20, D18, D1

  (913) 0x44ac1c FADD	D4, D20, D30

  (913) 0x44ac20 FMAXNM	D17, D4, D7

  (913) 0x44ac24 FMADD	D16, D24, D21, D0

  (913) 0x44ac28 FDIV	D26, D16, D17

  (913) 0x44ac2c FCMPE	D26, #0

  (913) 0x44ac30 B.GT	44ad38

  (913) 0x44ac34 FMUL	D19, D28, D19

  (913) 0x44ac38 FMADD	D25, D23, D25, D19

  (913) 0x44ac3c FCMPE	D25, #0

  (913) 0x44ac40 B.GE	44ad38

  (913) 0x44ac44 FCMPE	D29, #0

  (913) 0x44ac48 FABS	D5, D29

  (913) 0x44ac4c FMAXNM	D22, D5, D7

  (913) 0x44ac50 B.MI	44ad24

  (913) 0x44ac54 FMOV	D2, #1.0000000

  (913) 0x44ac58 FABS	D24, D24

  (913) 0x44ac5c FMAXNM	D3, D24, D7

  (913) 0x44ac60 FMUL	D27, D2, D3

  (913) 0x44ac64 LDR	D21, [X9]

  (913) 0x44ac68 FMUL	D29, D27, D27

  (913) 0x44ac6c FADD	D4, D21, D21

  (913) 0x44ac70 FMADD	D30, D22, D22, D29

  (913) 0x44ac74 FSQRT	D31, D30

  (913) 0x44ac78 FMUL	D23, D23, D31

  (913) 0x44ac7c FMUL	D28, D28, D31

  (913) 0x44ac80 FDIV	D18, D23, D27

  (913) 0x44ac84 FDIV	D1, D28, D22

  (913) 0x44ac88 FABS	D20, D18

  (913) 0x44ac8c FABS	D17, D1

  (913) 0x44ac90 FMINNM	D0, D17, D20

  (913) 0x44ac94 FMUL	D16, D0, D0

  (913) 0x44ac98 FMUL	D19, D4, D16

  (913) 0x44ac9c FMUL	D25, D19, D26

  (913) 0x44aca0 FMUL	D26, D25, D26

  (913) 0x44aca4 STR	D26, [X7]

  (913) 0x44aca8 ADD	X2, X2, #8

  (913) 0x44acac ADD	X5, X5, #8

  (913) 0x44acb0 ADD	X4, X4, #8

  (913) 0x44acb4 ADD	X3, X3, #8

  (913) 0x44acb8 ADD	X6, X6, #8

  (913) 0x44acbc ADD	X1, X1, #8

  (913) 0x44acc0 ADD	X9, X9, #8

  (913) 0x44acc4 ADD	X7, X7, #8

  (913) 0x44acc8 CMP	X11, X2

  (913) 0x44accc B.NE	44ab70

0x44acd0 LDR	W2, [SP, #116]

0x44acd4 ADD	X24, X24, X25

0x44acd8 ADD	X23, X23, X25

0x44acdc ADD	X22, X22, X26

0x44ace0 ADD	X16, X16, X26

0x44ace4 LDR	X4, [SP, #96]

0x44ace8 ADD	X15, X15, X17

0x44acec ADD	X21, X21, X17

0x44acf0 ORR	X8, XZR, X0

0x44acf4 LDR	X12, [SP, #104]

0x44acf8 CMP	W19, W2

0x44acfc LDR	X5, [SP, #136]

0x44ad00 ADD	X18, X18, X4

0x44ad04 LDR	W3, [SP, #132]

0x44ad08 ADD	X30, X30, X12

0x44ad0c ADD	X11, X11, X5

0x44ad10 B.EQ	44ad40

0x44ad14 CMP	W3, W0

0x44ad18 B.LE	44ad58

0x44ad1c ADD	X0, X0, #1

0x44ad20 B	44ab20

  (913) 0x44ad24 FCMPE	D22, #0

  (913) 0x44ad28 FMOV	D2, #-1.0000000

  (913) 0x44ad2c FNEG	D22, D22

  (913) 0x44ad30 B.GT	44ac58

  (913) 0x44ad34 B	44ac54

  (913) 0x44ad38 STR	XZR, [X7]

  (913) 0x44ad3c B	44aca8

0x44ad40 CMP	W3, W0

0x44ad44 B.LE	44adb8

0x44ad48 MOVZ	W1, #1

0x44ad4c ADD	X0, X0, #1

0x44ad50 STP	W1, W19, [SP, #176]

0x44ad54 B	44ab20

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/viscosity_kernel.f90: 54 - 89

--------------------------------------------------------------------------------

54:     !$OMP SIMD

55:       DO j=x_min,x_max

56:         ugrad=(xvel0(j+1,k  )+xvel0(j+1,k+1))-(xvel0(j  ,k  )+xvel0(j  ,k+1))

57:

58:         vgrad=(yvel0(j  ,k+1)+yvel0(j+1,k+1))-(yvel0(j  ,k  )+yvel0(j+1,k  ))

59:

60:         div = (celldx(j)*(ugrad)+  celldy(k)*(vgrad))

61:

62:         strain2 = 0.5_8*(xvel0(j,  k+1) + xvel0(j+1,k+1)-xvel0(j  ,k  )-xvel0(j+1,k  ))/celldy(k) &

63:           + 0.5_8*(yvel0(j+1,k  ) + yvel0(j+1,k+1)-yvel0(j  ,k  )-yvel0(j  ,k+1))/celldx(j)

64:

65:         pgradx=(pressure(j+1,k)-pressure(j-1,k))/(celldx(j)+celldx(j+1))

66:         pgrady=(pressure(j,k+1)-pressure(j,k-1))/(celldy(k)+celldy(k+1))

67:

68:         pgradx2 = pgradx*pgradx

69:         pgrady2 = pgrady*pgrady

70:

71:         limiter = ((0.5_8*(ugrad)/celldx(j))*pgradx2+(0.5_8*(vgrad)/celldy(k))*pgrady2+strain2*pgradx*pgrady)  &

72:           /MAX(pgradx2+pgrady2,1.0e-16_8)

73:

74:         IF ((limiter.GT.0.0).OR.(div.GE.0.0))THEN

75:           viscosity(j,k) = 0.0

76:         ELSE

77:           dirx=1.0_8

78:           IF(pgradx.LT.0.0) dirx=-1.0_8

79:           pgradx = dirx*MAX(1.0e-16_8,ABS(pgradx))

80:           diry=1.0_8

81:           IF(pgradx.LT.0.0) diry=-1.0_8

82:           pgrady = diry*MAX(1.0e-16_8,ABS(pgrady))

83:           pgrad = SQRT(pgradx**2+pgrady**2)

84:           xgrad = ABS(celldx(j)*pgrad/pgradx)

85:           ygrad = ABS(celldy(k)*pgrad/pgrady)

86:           grad  = MIN(xgrad,ygrad)

87:           grad2 = grad*grad

88:

89:           viscosity(j,k)=2.0_8*density0(j,k)*grad2*limiter*limiter

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.73
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.23
Bottlenecks	P2, P3, P4, P5,
Function	viscosity_kernel._omp_fn.0
Source	viscosity_kernel.f90:54-54,viscosity_kernel.f90:66-66,viscosity_kernel.f90:75-75,viscosity_kernel.f90:89-89
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.25
CQA cycles if no scalar integer	7.25
CQA cycles if FP arith vectorized	7.25
CQA cycles if fully vectorized	1.53
Front-end cycles	5.88
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	7.25
P2 cycles	7.25
P3 cycles	7.25
P4 cycles	7.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.17
P10 cycles	3.83
P11 cycles	4.00
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.00
Nb uops	47.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.59
Bytes prefetched	0.00
Bytes loaded	76.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	22.12
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	24.34
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.58

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.73
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.23
Bottlenecks	P2, P3, P4, P5,
Function	viscosity_kernel._omp_fn.0
Source	viscosity_kernel.f90:54-54,viscosity_kernel.f90:66-66,viscosity_kernel.f90:75-75,viscosity_kernel.f90:89-89
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.25
CQA cycles if no scalar integer	7.25
CQA cycles if FP arith vectorized	7.25
CQA cycles if fully vectorized	1.53
Front-end cycles	5.88
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	7.25
P2 cycles	7.25
P3 cycles	7.25
P4 cycles	7.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	4.17
P10 cycles	3.83
P11 cycles	4.00
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	47.00
Nb uops	47.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.59
Bytes prefetched	0.00
Bytes loaded	76.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	22.12
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	24.34
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.58

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	viscosity_kernel._omp_fn.0
Source file and lines	viscosity_kernel.f90:54-89
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/viscosity_kernel.f90:54-89.

Analyzed code is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/viscosity_kernel.f90:54,66,75,89.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=12
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 12 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 7.25 to 1.53 cycles (4.73x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 76 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	47
loop length	188
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	4.17	3.83	4.00	0.50	0.50
cycles	3.00	3.00	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	4.17	3.83	4.00	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.88
Overall L1	7.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.25 cycles. At this rate:

10% of peak load performance is reached (10.48 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.10 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44ab20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR W12, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W12, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 44acd0 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W5, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X2, X28, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SBFM X9, X5, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X20, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X12, X21, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X7, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, X28, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X3, X20, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X6, [SP, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X10, X9, X17, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X1, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X7, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X7, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X10, X10, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X7, X7, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W2, [SP, #116]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X24, X24, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X23, X23, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X22, X22, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X16, X16, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X4, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X15, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X21, X21, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X8, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X12, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W19, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
LDR X5, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X18, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W3, [SP, #132]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X30, X30, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X11, X11, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B.EQ 44ad40 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 44ad58 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x3b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 44ab20 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 44adb8 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP W1, W19, [SP, #176]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 44ab20 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	viscosity_kernel._omp_fn.0
Source file and lines	viscosity_kernel.f90:54-89
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=12
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 76 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	47
loop length	188
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	4.17	3.83	4.00	0.50	0.50
cycles	3.00	3.00	7.25	7.25	7.25	7.25	0.00	0.00	0.00	0.00	4.17	3.83	4.00	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.88
Overall L1	7.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.25 cycles. At this rate:

10% of peak load performance is reached (10.48 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.10 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 44ab20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR W12, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W12, W27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 44acd0 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W5, W8, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X2, X28, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SBFM X9, X5, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X20, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X12, X21, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X7, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X5, X28, X23,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X3, X20, X16,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X6, [SP, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
MADD X10, X9, X17, X1	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X1, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X9, X7, X30,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X7, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB X10, X10, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X7, X7, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W2, [SP, #116]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X24, X24, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X23, X23, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X22, X22, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X16, X16, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X4, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X15, X15, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X21, X21, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X8, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X12, [SP, #104]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W19, W2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
LDR X5, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X18, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W3, [SP, #132]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X30, X30, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X11, X11, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B.EQ 44ad40 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x3a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 44ad58 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x3b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 44ab20 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W3, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LE 44adb8 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x418>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP W1, W19, [SP, #176]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B 44ab20 <__viscosity_kernel_module_MOD_viscosity_kernel._omp_fn.0+0x180>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code