OV - exec - Loop 595

	Loop Id: 595	Module: exec	Source: update_halo_kernel.f90:539-539	Coverage: 0.05%

0x438640 CMP	W22, #1

0x438644 B.EQ	439e74

0x438648 ANDS	W26, W14, #64

0x43864c ORR	X2, XZR, X12

0x438650 ORR	X3, XZR, X13

0x438654 MOVZ	W5, #0

0x438658 B.EQ	4386ec

0x43865c CMP	W26, #1

0x438660 B.EQ	4386bc

0x438664 CMP	W26, #2

0x438668 B.EQ	438694

0x43866c LDR	D28, [X12, X6]

0x438670 ADD	X27, X13, X7

0x438674 MOVZ	W5, #1

0x438678 SUB	X3, X13, X0

0x43867c ADD	X2, X12, X0

0x438680 LDR	D29, [X12]

0x438684 MOV	V29.D[1], V28.D[0]

0x438688 FNEG	V30.2D, V29.2D

0x43868c STR	D30, [X13]

0x438690 ST1	{V30.D[1]}, [X27]

0x438694 LDR	D31, [X2, X6]

0x438698 ADD	X28, X3, X7

0x43869c ADD	W5, W5, #1

0x4386a0 LDR	D2, [X2]

0x4386a4 ADD	X2, X2, X0

0x4386a8 MOV	V2.D[1], V31.D[0]

0x4386ac FNEG	V3.2D, V2.2D

0x4386b0 STR	D3, [X3]

0x4386b4 SUB	X3, X3, X0

0x4386b8 ST1	{V3.D[1]}, [X28]

0x4386bc LDR	D4, [X2, X6]

0x4386c0 ADD	X30, X3, X7

0x4386c4 ADD	W5, W5, #1

0x4386c8 LDR	D5, [X2]

0x4386cc ADD	X2, X2, X0

0x4386d0 MOV	V5.D[1], V4.D[0]

0x4386d4 FNEG	V6.2D, V5.2D

0x4386d8 STR	D6, [X3]

0x4386dc SUB	X3, X3, X0

0x4386e0 ST1	{V6.D[1]}, [X30]

0x4386e4 CMP	W5, W14

0x4386e8 B.EQ	438788

  (596) 0x4386ec LDR	D7, [X2, X6]

  (596) 0x4386f0 ADD	X11, X2, X0

  (596) 0x4386f4 ADD	X25, X3, X7

  (596) 0x4386f8 SUB	X18, X3, X0

  (596) 0x4386fc ADD	X16, X11, X0

  (596) 0x438700 LDR	D16, [X2]

  (596) 0x438704 ADD	X27, X18, X7

  (596) 0x438708 SUB	X28, X18, X0

  (596) 0x43870c ADD	X30, X16, X0

  (596) 0x438710 ADD	X26, X28, X7

  (596) 0x438714 ADD	W5, W5, #4

  (596) 0x438718 MOV	V16.D[1], V7.D[0]

  (596) 0x43871c FNEG	V1.2D, V16.2D

  (596) 0x438720 STR	D1, [X3]

  (596) 0x438724 ST1	{V1.D[1]}, [X25]

  (596) 0x438728 LDR	D17, [X2, X0]

  (596) 0x43872c SUB	X25, X28, X0

  (596) 0x438730 ADD	X2, X30, X0

  (596) 0x438734 SUB	X3, X25, X0

  (596) 0x438738 LDR	D18, [X11, X6]

  (596) 0x43873c MOV	V17.D[1], V18.D[0]

  (596) 0x438740 FNEG	V19.2D, V17.2D

  (596) 0x438744 STR	D19, [X18]

  (596) 0x438748 ST1	{V19.D[1]}, [X27]

  (596) 0x43874c LDR	D20, [X11, X0]

  (596) 0x438750 ADD	X11, X25, X7

  (596) 0x438754 LDR	D21, [X16, X6]

  (596) 0x438758 MOV	V20.D[1], V21.D[0]

  (596) 0x43875c FNEG	V22.2D, V20.2D

  (596) 0x438760 STR	D22, [X28]

  (596) 0x438764 ST1	{V22.D[1]}, [X26]

  (596) 0x438768 LDR	D23, [X16, X0]

  (596) 0x43876c LDR	D24, [X30, X6]

  (596) 0x438770 MOV	V23.D[1], V24.D[0]

  (596) 0x438774 FNEG	V25.2D, V23.2D

  (596) 0x438778 STR	D25, [X25]

  (596) 0x43877c ST1	{V25.D[1]}, [X11]

  (596) 0x438780 CMP	W5, W14

  (596) 0x438784 B.NE	4386ec

0x438788 ORR	W25, WZR, W24

0x43878c CMP	W23, W22

0x438790 B.EQ	4387bc

0x438794 ADD	W2, W25, #1

0x438798 ADD	X5, X10, X4

0x43879c SBFM	X3, X2, #0, #31

0x4387a0 SUB	W18, W8, W25

0x4387a4 SBFM	X16, X18, #0, #31

0x4387a8 MADD	X27, X3, X9, X5

0x4387ac MADD	X28, X16, X9, X5

0x4387b0 LDR	D0, [X1, X27,LSL #3]

0x4387b4 FNEG	D26, D0

0x4387b8 STR	D26, [X1, X28,LSL #3]

0x4387bc ADD	X4, X4, #1

0x4387c0 ADD	X12, X12, #8

0x4387c4 ADD	W30, W15, W4

0x4387c8 ADD	X13, X13, #8

0x4387cc CMP	W17, W30

0x4387d0 B.GT	438640

0x439e74 ORR	W25, WZR, W22

0x439e78 B	438794

/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90: 539 - 539

--------------------------------------------------------------------------------

539:             yvel1(j,1-k)=-yvel1(j,1+k)

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	update_halo_kernel	update_halo_kernel.f90:754	exec
○	update_halo	update_halo.f90:78	exec
○	advection	advection.f90:72	exec
○	hydro	hydro.f90:64	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.81
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.29
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P2, P3, P4, P5,
Function	update_halo_kernel._omp_fn.0
Source	update_halo_kernel.f90:539-539
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.75
CQA cycles if no scalar integer	4.83
CQA cycles if FP arith vectorized	8.75
CQA cycles if fully vectorized	1.39
Front-end cycles	8.00
DIV/SQRT cycles	4.00
P0 cycles	4.00
P1 cycles	8.75
P2 cycles	8.75
P3 cycles	8.75
P4 cycles	8.75
P5 cycles	3.50
P6 cycles	3.50
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	4.83
P10 cycles	4.50
P11 cycles	4.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	64.00
Nb uops	64.00
Nb loads	NA
Nb stores	7.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.54
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	80.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	8.57
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	18.75
Vector-efficiency ratio all	22.50
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	17.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	21.88

Metric	Value
CQA speedup if no scalar integer	1.81
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.29
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P2, P3, P4, P5,
Function	update_halo_kernel._omp_fn.0
Source	update_halo_kernel.f90:539-539
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	8.75
CQA cycles if no scalar integer	4.83
CQA cycles if FP arith vectorized	8.75
CQA cycles if fully vectorized	1.39
Front-end cycles	8.00
DIV/SQRT cycles	4.00
P0 cycles	4.00
P1 cycles	8.75
P2 cycles	8.75
P3 cycles	8.75
P4 cycles	8.75
P5 cycles	3.50
P6 cycles	3.50
P7 cycles	3.50
P8 cycles	3.50
P9 cycles	4.83
P10 cycles	4.50
P11 cycles	4.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	64.00
Nb uops	64.00
Nb loads	NA
Nb stores	7.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.54
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	80.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	8.57
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	18.75
Vector-efficiency ratio all	22.50
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	17.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	21.88

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	update_halo_kernel._omp_fn.0
Source file and lines	update_halo_kernel.f90:539-539
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90:539.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=15
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 15 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.75 to 4.83 cycles (1.81x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is probably not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 8.75 to 1.39 cycles (6.29x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 56 bytes. The binary loop is storing 80 bytes.

General properties

nb instructions	64
loop length	256
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	8.75	8.75	8.75	8.75	3.50	3.50	3.50	3.50	4.83	4.50	4.67	0.00	0.00
cycles	4.00	4.00	8.75	8.75	8.75	8.75	3.50	3.50	3.50	3.50	4.83	4.50	4.67	0.00	0.00

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.00
Overall L1	8.75

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	8%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.75 cycles. At this rate:

6% of peak load performance is reached (6.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
19% of peak store performance is reached (9.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 438640

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
CMP W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 439e74 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0xa674>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ANDS W26, W14, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
ORR X2, XZR, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X3, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ W5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.EQ 4386ec <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x8eec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4386bc <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x8ebc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W26, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 438694 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x8e94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D28, [X12, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X27, X13, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X3, X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X2, X12, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D29, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MOV V29.D[1], V28.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FNEG V30.2D, V29.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D30, [X13]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ST1 {V30.D[1]}, [X27]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	0.50
LDR D31, [X2, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X28, X3, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W5, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOV V2.D[1], V31.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FNEG V3.2D, V2.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D3, [X3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
SUB X3, X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ST1 {V3.D[1]}, [X28]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	0.50
LDR D4, [X2, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X30, X3, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W5, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D5, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOV V5.D[1], V4.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FNEG V6.2D, V5.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D6, [X3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
SUB X3, X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ST1 {V6.D[1]}, [X30]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	0.50
CMP W5, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 438788 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x8f88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W25, WZR, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W23, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4387bc <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x8fbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W2, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X5, X10, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X3, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB W18, W8, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X16, X18, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X27, X3, X9, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X28, X16, X9, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR D0, [X1, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D26, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D26, [X1, X28,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W30, W15, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X13, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W17, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GT 438640 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x8e40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W25, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B 438794 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x8f94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	update_halo_kernel._omp_fn.0
Source file and lines	update_halo_kernel.f90:539-539
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90:539.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=15
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 8.75 to 4.83 cycles (1.81x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 56 bytes. The binary loop is storing 80 bytes.

General properties

nb instructions	64
loop length	256
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	4.00	4.00	8.75	8.75	8.75	8.75	3.50	3.50	3.50	3.50	4.83	4.50	4.67	0.00	0.00
cycles	4.00	4.00	8.75	8.75	8.75	8.75	3.50	3.50	3.50	3.50	4.83	4.50	4.67	0.00	0.00

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.00
Overall L1	8.75

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	8%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	18%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.75 cycles. At this rate:

6% of peak load performance is reached (6.40 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
19% of peak store performance is reached (9.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 438640

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
CMP W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 439e74 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0xa674>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ANDS W26, W14, #64	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
ORR X2, XZR, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X3, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ W5, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.EQ 4386ec <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x8eec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4386bc <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x8ebc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W26, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 438694 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x8e94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D28, [X12, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X27, X13, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOVZ W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X3, X13, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X2, X12, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D29, [X12]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MOV V29.D[1], V28.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FNEG V30.2D, V29.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D30, [X13]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ST1 {V30.D[1]}, [X27]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	0.50
LDR D31, [X2, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X28, X3, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W5, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D2, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOV V2.D[1], V31.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FNEG V3.2D, V2.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D3, [X3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
SUB X3, X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ST1 {V3.D[1]}, [X28]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	0.50
LDR D4, [X2, X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X30, X3, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W5, W5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D5, [X2]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MOV V5.D[1], V4.D[0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FNEG V6.2D, V5.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D6, [X3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
SUB X3, X3, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ST1 {V6.D[1]}, [X30]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	0.50
CMP W5, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 438788 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x8f88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W25, WZR, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W23, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 4387bc <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x8fbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W2, W25, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X5, X10, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X3, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB W18, W8, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X16, X18, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X27, X3, X9, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X28, X16, X9, X5	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR D0, [X1, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FNEG D26, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D26, [X1, X28,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X4, X4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X12, X12, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD W30, W15, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X13, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W17, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GT 438640 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x8e40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR W25, WZR, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B 438794 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x8f94>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code