OV - exec - Loop 591

	Loop Id: 591	Module: exec	Source: generate_chunk_kernel.f90-pp.f90:130-166 [...]	Coverage: 0.02%

0x4262c4 SUB	W16, W16, #1

0x4262c8 ADD	X17, X17, #1

0x4262cc ADD	X15, X15, #8

0x4262d0 CMP	W16, #1

0x4262d4 B.LE	4262a0

0x4262d8 LDR	D1, [X15]    [15]

0x4262dc FCMP	D1, D0

0x4262e0 B.LT	4262c4

0x4262e4 LDR	X18, [X19, #296]    [22]

0x4262e8 LDUR	D1, [X15, #504]    [15]

0x4262ec ADD	X18, X18, X22,LSL #3

0x4262f0 LDUR	D2, [X18, #504]    [1]

0x4262f4 FCMP	D1, D2

0x4262f8 B.PL	4262c4

0x4262fc LDP	X18, X0, [X19, #304]    [22]

0x426300 LDR	X0, [X0]    [17]

0x426304 SUB	X0, X8, X0

0x426308 ADD	X1, X18, X0,LSL #3

0x42630c LDR	D1, [X1, #8]    [7]

0x426310 LDR	X1, [X19, #248]    [22]

0x426314 ADD	X1, X1, X22,LSL #3

0x426318 LDUR	D2, [X1, #504]    [11]

0x42631c FCMP	D1, D2

0x426320 B.LT	4262c4

0x426324 LDR	D1, [X18, X0,LSL #3]    [20]

0x426328 LDR	X18, [X19, #320]    [22]

0x42632c ADD	X18, X18, X22,LSL #3

0x426330 LDUR	D2, [X18, #504]    [4]

0x426334 FCMP	D1, D2

0x426338 B.PL	4262c4

0x42633c LDP	X1, X0, [X19, #96]    [22]

0x426340 LDR	X18, [X19, #56]    [22]

0x426344 LDP	X4, X3, [X19, #120]    [22]

0x426348 ADD	X0, X0, X24

0x42634c LDR	X1, [X1]    [3]

0x426350 LDR	X18, [X18]    [21]

0x426354 LDR	X2, [X19, #32]    [22]

0x426358 ADD	X3, X3, X24

0x42635c LDR	X5, [X19, #152]    [22]

0x426360 LDUR	D1, [X0, #504]    [12]

0x426364 LDUR	D2, [X3, #504]    [13]

0x426368 LDP	X3, X0, [X19, #184]    [22]

0x42636c SUB	X1, XZR, X1

0x426370 MADD	X18, X8, X18, X1

0x426374 ADD	X0, X0, X24

0x426378 LDR	X3, [X3]    [14]

0x42637c ADD	X18, X17, X18

0x426380 SUB	X0, X0, #8

0x426384 STR	D1, [X2, X18,LSL #3]    [5]

0x426388 LDP	X2, X1, [X19, #200]    [22]

0x42638c STR	D2, [X4, X18,LSL #3]    [10]

0x426390 LDR	X18, [X5]    [16]

0x426394 LD1R	{V1.2D}, [X0]    [19]

0x426398 SUB	X0, XZR, X3

0x42639c ADD	X1, X1, X24

0x4263a0 MADD	X3, X8, X18, X0

0x4263a4 MADD	X18, X13, X18, X0

0x4263a8 SUB	X1, X1, #8

0x4263ac ADD	X3, X17, X3

0x4263b0 ADD	X18, X17, X18

0x4263b4 LD1R	{V2.2D}, [X1]    [8]

0x4263b8 LDR	X1, [X19, #136]    [22]

0x4263bc UBFM	X3, X3, #61, #60

0x4263c0 UBFM	X18, X18, #61, #60

0x4263c4 STR	Q1, [X1, X3]    [2]

0x4263c8 STR	Q1, [X1, X18]    [18]

0x4263cc STR	Q2, [X2, X3]    [6]

0x4263d0 STR	Q2, [X2, X18]    [9]

0x4263d4 B	4262c4

/home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/generate_chunk_kernel.f90-pp.f90: 130 - 166

--------------------------------------------------------------------------------

130:           IF(state_geometry(state).EQ.g_rect ) THEN

131:             IF(vertexx(j+1).GE.state_xmin(state).AND.vertexx(j).LT.state_xmax(state)) THEN

132:               IF(vertexy(k+1).GE.state_ymin(state).AND.vertexy(k).LT.state_ymax(state)) THEN

133:                 energy0(j,k)=state_energy(state)

134:                 density0(j,k)=state_density(state)

135:                 DO kt=k,k+1

136:                   DO jt=j,j+1

137:                     xvel0(jt,kt)=state_xvel(state)

[...]

166:           ENDIF

Path /

Metric	Value
CQA speedup if no scalar integer	1.48
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.61
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.31
Bottlenecks	P10, P11, P12,
Function	__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_
Source	generate_chunk_kernel.f90-pp.f90:130-137,generate_chunk_kernel.f90-pp.f90:166-166
Source loop unroll info	unrolled by 33
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	33
CQA cycles	11.33
CQA cycles if no scalar integer	7.67
CQA cycles if FP arith vectorized	11.33
CQA cycles if fully vectorized	2.46
Front-end cycles	8.63
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	6.25
P2 cycles	6.25
P3 cycles	6.25
P4 cycles	6.25
P5 cycles	5.00
P6 cycles	5.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	11.33
P10 cycles	11.33
P11 cycles	11.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	69.00
Nb uops	69.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.35
Bytes prefetched	0.00
Bytes loaded	264.00
Bytes stored	80.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	21.05
Vectorization ratio load	0.00
Vectorization ratio store	66.67
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	28.95
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	41.67
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.48
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.61
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.31
Bottlenecks	P10, P11, P12,
Function	__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_
Source	generate_chunk_kernel.f90-pp.f90:130-137,generate_chunk_kernel.f90-pp.f90:166-166
Source loop unroll info	unrolled by 33
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	33
CQA cycles	11.33
CQA cycles if no scalar integer	7.67
CQA cycles if FP arith vectorized	11.33
CQA cycles if fully vectorized	2.46
Front-end cycles	8.63
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	6.25
P2 cycles	6.25
P3 cycles	6.25
P4 cycles	6.25
P5 cycles	5.00
P6 cycles	5.00
P7 cycles	1.00
P8 cycles	1.00
P9 cycles	11.33
P10 cycles	11.33
P11 cycles	11.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	69.00
Nb uops	69.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.35
Bytes prefetched	0.00
Bytes loaded	264.00
Bytes stored	80.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	21.05
Vectorization ratio load	0.00
Vectorization ratio store	66.67
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	28.95
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	41.67
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_
Source file and lines	generate_chunk_kernel.f90-pp.f90:130-166
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/generate_chunk_kernel.f90-pp.f90:130-137,166.

The related source loop is unrolled by 33 (including vectorization).
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 5 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.33 to 7.67 cycles (1.48x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is poorly vectorized. Only 28% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 11.33 to 2.46 cycles (4.61x speedup).

Details

21% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
66% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 264 bytes. The binary loop is storing 80 bytes.

General properties

nb instructions	69
loop length	276
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	6.25	6.25	6.25	6.25	5.00	5.00	1.00	1.00	11.33	11.33	11.33	0.00	0.00
cycles	3.00	3.00	6.25	6.25	6.25	6.25	5.00	5.00	1.00	1.00	11.33	11.33	11.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.63
Overall L1	11.33

Vectorization ratios

all	21%
load	0%
store	66%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.33 cycles. At this rate:

24% of peak load performance is reached (23.29 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (7.06 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4262d8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
SUB W16, W16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X17, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 4262a0 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x710>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D1, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMP D1, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LT 4262c4 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x734>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X19, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR D1, [X15, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X18, X18, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDUR D2, [X18, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMP D1, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.PL 4262c4 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x734>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X18, X0, [X19, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDR X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB X0, X8, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X1, X18, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D1, [X1, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X1, [X19, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X1, X1, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDUR D2, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMP D1, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LT 4262c4 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x734>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D1, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X18, [X19, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X18, X18, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDUR D2, [X18, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMP D1, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.PL 4262c4 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x734>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X1, X0, [X19, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDR X18, [X19, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDP X4, X3, [X19, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
ADD X0, X0, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X18, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X2, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X3, X3, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X5, [X19, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR D1, [X0, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDUR D2, [X3, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDP X3, X0, [X19, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
SUB X1, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X18, X8, X18, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X0, X0, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X3, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X18, X17, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR D1, [X2, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDP X2, X1, [X19, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
STR D2, [X4, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR X18, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LD1R {V1.2D}, [X0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33
SUB X0, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X3, X8, X18, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X18, X13, X18, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
SUB X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X3, X17, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X18, X17, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LD1R {V2.2D}, [X1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33
LDR X1, [X19, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
UBFM X3, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X18, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR Q1, [X1, X3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
STR Q1, [X1, X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
STR Q2, [X2, X3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
STR Q2, [X2, X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 4262c4 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x734>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_
Source file and lines	generate_chunk_kernel.f90-pp.f90:130-166
Module	exec

Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.33 to 7.67 cycles (1.48x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

21% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
66% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 264 bytes. The binary loop is storing 80 bytes.

General properties

nb instructions	69
loop length	276
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	6.25	6.25	6.25	6.25	5.00	5.00	1.00	1.00	11.33	11.33	11.33	0.00	0.00
cycles	3.00	3.00	6.25	6.25	6.25	6.25	5.00	5.00	1.00	1.00	11.33	11.33	11.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.63
Overall L1	11.33

Vectorization ratios

all	21%
load	0%
store	66%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.33 cycles. At this rate:

24% of peak load performance is reached (23.29 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (7.06 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4262d8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
SUB W16, W16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X17, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.LE 4262a0 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x710>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D1, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMP D1, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LT 4262c4 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x734>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X18, [X19, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR D1, [X15, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X18, X18, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDUR D2, [X18, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMP D1, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.PL 4262c4 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x734>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X18, X0, [X19, #304]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDR X0, [X0]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB X0, X8, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X1, X18, X0,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D1, [X1, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X1, [X19, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X1, X1, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDUR D2, [X1, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMP D1, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LT 4262c4 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x734>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D1, [X18, X0,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X18, [X19, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X18, X18, X22,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDUR D2, [X18, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMP D1, D2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.PL 4262c4 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x734>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X1, X0, [X19, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
LDR X18, [X19, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDP X4, X3, [X19, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
ADD X0, X0, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X18, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR X2, [X19, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X3, X3, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X5, [X19, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDUR D1, [X0, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDUR D2, [X3, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDP X3, X0, [X19, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
SUB X1, XZR, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X18, X8, X18, X1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X0, X0, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X3, [X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X18, X17, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR D1, [X2, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDP X2, X1, [X19, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
STR D2, [X4, X18,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR X18, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LD1R {V1.2D}, [X0]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33
SUB X0, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X3, X8, X18, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X18, X13, X18, X0	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
SUB X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X3, X17, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X18, X17, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LD1R {V2.2D}, [X1]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33
LDR X1, [X19, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
UBFM X3, X3, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
UBFM X18, X18, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
STR Q1, [X1, X3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
STR Q1, [X1, X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
STR Q2, [X2, X3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
STR Q2, [X2, X18]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 4262c4 <__nv_generate_chunk_kernel_module_generate_chunk_kernel__F1L85_1_+0x734>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code