OV - exec - Loop 555

	Loop Id: 555	Module: exec	Source: update_halo_kernel.f90:148-148	Coverage: 0.02%

0x4360c0 CMP	W26, #1

0x4360c4 B.EQ	439f10

0x4360c8 ANDS	W13, W11, #128

0x4360cc ORR	X2, XZR, X10

0x4360d0 ORR	X1, XZR, X9

0x4360d4 MOVZ	W4, #0

0x4360d8 B.EQ	4361d8

0x4360dc CMP	W13, #1

0x4360e0 B.EQ	4361b4

0x4360e4 CMP	W13, #2

0x4360e8 B.EQ	436198

0x4360ec CMP	W13, #3

0x4360f0 B.EQ	43617c

0x4360f4 CMP	W13, #4

0x4360f8 B.EQ	436160

0x4360fc CMP	W13, #5

0x436100 B.EQ	436144

0x436104 CMP	W13, #6

0x436108 B.EQ	436128

0x43610c LDR	D3, [X9]

0x436110 MOVZ	W4, #1

0x436114 ADD	X1, X9, X0

0x436118 SUB	X2, X10, X0

0x43611c LDR	D0, [X9, X6]

0x436120 STR	D3, [X10]

0x436124 STR	D0, [X10, X7]

0x436128 LDR	D5, [X1]

0x43612c ADD	W4, W4, #1

0x436130 LDR	D4, [X1, X6]

0x436134 ADD	X1, X1, X0

0x436138 STR	D5, [X2]

0x43613c STR	D4, [X2, X7]

0x436140 SUB	X2, X2, X0

0x436144 LDR	D7, [X1]

0x436148 ADD	W4, W4, #1

0x43614c LDR	D6, [X1, X6]

0x436150 ADD	X1, X1, X0

0x436154 STR	D7, [X2]

0x436158 STR	D6, [X2, X7]

0x43615c SUB	X2, X2, X0

0x436160 LDR	D17, [X1]

0x436164 ADD	W4, W4, #1

0x436168 LDR	D16, [X1, X6]

0x43616c ADD	X1, X1, X0

0x436170 STR	D17, [X2]

0x436174 STR	D16, [X2, X7]

0x436178 SUB	X2, X2, X0

0x43617c LDR	D19, [X1]

0x436180 ADD	W4, W4, #1

0x436184 LDR	D18, [X1, X6]

0x436188 ADD	X1, X1, X0

0x43618c STR	D19, [X2]

0x436190 STR	D18, [X2, X7]

0x436194 SUB	X2, X2, X0

0x436198 LDR	D21, [X1]

0x43619c ADD	W4, W4, #1

0x4361a0 LDR	D20, [X1, X6]

0x4361a4 ADD	X1, X1, X0

0x4361a8 STR	D21, [X2]

0x4361ac STR	D20, [X2, X7]

0x4361b0 SUB	X2, X2, X0

0x4361b4 LDR	D23, [X1]

0x4361b8 ADD	W4, W4, #1

0x4361bc LDR	D22, [X1, X6]

0x4361c0 ADD	X1, X1, X0

0x4361c4 STR	D23, [X2]

0x4361c8 STR	D22, [X2, X7]

0x4361cc SUB	X2, X2, X0

0x4361d0 CMP	W11, W4

0x4361d4 B.EQ	4362a4

  (556) 0x4361d8 LDR	D25, [X1]

  (556) 0x4361dc ADD	X12, X1, X0

  (556) 0x4361e0 SUB	X14, X2, X0

  (556) 0x4361e4 ADD	X13, X12, X0

  (556) 0x4361e8 ADD	W4, W4, #8

  (556) 0x4361ec LDR	D24, [X1, X6]

  (556) 0x4361f0 STR	D25, [X2]

  (556) 0x4361f4 STR	D24, [X2, X7]

  (556) 0x4361f8 ADD	X2, X13, X0

  (556) 0x4361fc LDR	D26, [X1, X0]

  (556) 0x436200 SUB	X1, X14, X0

  (556) 0x436204 LDR	D27, [X12, X6]

  (556) 0x436208 STR	D26, [X14]

  (556) 0x43620c STR	D27, [X14, X7]

  (556) 0x436210 SUB	X14, X1, X0

  (556) 0x436214 LDR	D28, [X12, X0]

  (556) 0x436218 ADD	X12, X2, X0

  (556) 0x43621c LDR	D29, [X13, X6]

  (556) 0x436220 STR	D28, [X1]

  (556) 0x436224 STR	D29, [X1, X7]

  (556) 0x436228 ADD	X1, X12, X0

  (556) 0x43622c LDR	D30, [X13, X0]

  (556) 0x436230 SUB	X13, X14, X0

  (556) 0x436234 LDR	D31, [X2, X6]

  (556) 0x436238 STR	D30, [X14]

  (556) 0x43623c STR	D31, [X14, X7]

  (556) 0x436240 SUB	X14, X13, X0

  (556) 0x436244 LDR	D1, [X2, X0]

  (556) 0x436248 ADD	X2, X1, X0

  (556) 0x43624c LDR	D2, [X12, X6]

  (556) 0x436250 STR	D1, [X13]

  (556) 0x436254 STR	D2, [X13, X7]

  (556) 0x436258 ADD	X13, X2, X0

  (556) 0x43625c LDR	D3, [X12, X0]

  (556) 0x436260 SUB	X12, X14, X0

  (556) 0x436264 LDR	D0, [X1, X6]

  (556) 0x436268 STR	D3, [X14]

  (556) 0x43626c STR	D0, [X14, X7]

  (556) 0x436270 SUB	X14, X12, X0

  (556) 0x436274 LDR	D4, [X1, X0]

  (556) 0x436278 ADD	X1, X13, X0

  (556) 0x43627c LDR	D5, [X2, X6]

  (556) 0x436280 STR	D4, [X12]

  (556) 0x436284 STR	D5, [X12, X7]

  (556) 0x436288 LDR	D6, [X2, X0]

  (556) 0x43628c SUB	X2, X14, X0

  (556) 0x436290 LDR	D7, [X13, X6]

  (556) 0x436294 STR	D6, [X14]

  (556) 0x436298 STR	D7, [X14, X7]

  (556) 0x43629c CMP	W11, W4

  (556) 0x4362a0 B.NE	4361d8

0x4362a4 ORR	W12, WZR, W30

0x4362a8 CMP	W26, W17

0x4362ac B.EQ	4362d0

0x4362b0 ADD	X2, X18, X5

0x4362b4 SBFM	X4, X12, #0, #31

0x4362b8 SUB	W1, W8, W12

0x4362bc MADD	X12, X4, X25, X2

0x4362c0 SBFM	X13, X1, #0, #31

0x4362c4 MADD	X14, X13, X25, X2

0x4362c8 LDR	D16, [X3, X12,LSL #3]

0x4362cc STR	D16, [X3, X14,LSL #3]

0x4362d0 ADD	X5, X5, #1

0x4362d4 ADD	X9, X9, #8

0x4362d8 ADD	W4, W16, W5

0x4362dc ADD	X10, X10, #8

0x4362e0 CMP	W15, W4

0x4362e4 B.GT	4360c0

0x439f10 ORR	W12, WZR, W26

0x439f14 B	4362b0

/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90: 148 - 148

--------------------------------------------------------------------------------

148:             density1(j,1-k)=density1(j,0+k)

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	update_halo_kernel	update_halo_kernel.f90:754	exec
○	update_halo	update_halo.f90:78	exec
○	advection	advection.f90:56	exec
○	hydro	hydro.f90:64	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.16
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.62
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	P2, P3, P4, P5,
Function	update_halo_kernel._omp_fn.0
Source	update_halo_kernel.f90:148-148
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.75
CQA cycles if no scalar integer	10.17
CQA cycles if FP arith vectorized	11.75
CQA cycles if fully vectorized	2.54
Front-end cycles	11.13
DIV/SQRT cycles	6.00
P0 cycles	6.00
P1 cycles	11.75
P2 cycles	11.75
P3 cycles	11.75
P4 cycles	11.75
P5 cycles	7.50
P6 cycles	7.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	10.17
P10 cycles	9.83
P11 cycles	10.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	89.00
Nb uops	89.00
Nb loads	NA
Nb stores	15.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.43
Bytes prefetched	0.00
Bytes loaded	120.00
Bytes stored	120.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	21.95
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.16
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.62
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	P2, P3, P4, P5,
Function	update_halo_kernel._omp_fn.0
Source	update_halo_kernel.f90:148-148
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	11.75
CQA cycles if no scalar integer	10.17
CQA cycles if FP arith vectorized	11.75
CQA cycles if fully vectorized	2.54
Front-end cycles	11.13
DIV/SQRT cycles	6.00
P0 cycles	6.00
P1 cycles	11.75
P2 cycles	11.75
P3 cycles	11.75
P4 cycles	11.75
P5 cycles	7.50
P6 cycles	7.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	10.17
P10 cycles	9.83
P11 cycles	10.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	89.00
Nb uops	89.00
Nb loads	NA
Nb stores	15.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	20.43
Bytes prefetched	0.00
Bytes loaded	120.00
Bytes stored	120.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	21.95
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	update_halo_kernel._omp_fn.0
Source file and lines	update_halo_kernel.f90:148-148
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90:148.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=31
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 31 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 11.75 to 10.17 cycles (1.16x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 21% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 11.75 to 2.54 cycles (4.62x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 120 bytes. The binary loop is storing 120 bytes.

General properties

nb instructions	89
loop length	356
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.00	6.00	11.75	11.75	11.75	11.75	7.50	7.50	0.00	0.00	10.17	9.83	10.00	0.00	0.00
cycles	6.00	6.00	11.75	11.75	11.75	11.75	7.50	7.50	0.00	0.00	10.17	9.83	10.00	0.00	0.00

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.13
Overall L1	11.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.75 cycles. At this rate:

10% of peak load performance is reached (10.21 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
21% of peak store performance is reached (10.21 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4360c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
CMP W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 439f10 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0xa710>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ANDS W13, W11, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
ORR X2, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X1, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B.EQ 4361d8 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x69d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4361b4 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x69b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 436198 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x6998>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 43617c <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x697c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 436160 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x6960>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 436144 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x6944>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 436128 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x6928>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR D3, [X9]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X9, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X2, X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D0, [X9, X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D3, [X10]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STR D0, [X10, X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D5, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D4, [X1, X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D5, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STR D4, [X2, X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D7, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D6, [X1, X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D7, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STR D6, [X2, X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D17, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D16, [X1, X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D17, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STR D16, [X2, X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D19, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D18, [X1, X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D19, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STR D18, [X2, X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D21, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D20, [X1, X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D21, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STR D20, [X2, X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D23, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D22, [X1, X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D23, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STR D22, [X2, X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W11, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4362a4 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x6aa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR W12, WZR, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W26, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4362d0 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x6ad0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X2, X18, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SBFM X4, X12, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W1, W8, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X12, X4, X25, X2	1	0	0	0	0	1	0	0	0	0	0	0	2	1
SBFM X13, X1, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X14, X13, X25, X2	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR D16, [X3, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D16, [X3, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
ADD X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X9, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W4, W16, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W15, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 4360c0 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x68c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR W12, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 4362b0 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x6ab0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	update_halo_kernel._omp_fn.0
Source file and lines	update_halo_kernel.f90:148-148
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90:148.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=31
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 120 bytes. The binary loop is storing 120 bytes.

General properties

nb instructions	89
loop length	356
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	6.00	6.00	11.75	11.75	11.75	11.75	7.50	7.50	0.00	0.00	10.17	9.83	10.00	0.00	0.00
cycles	6.00	6.00	11.75	11.75	11.75	11.75	7.50	7.50	0.00	0.00	10.17	9.83	10.00	0.00	0.00

Cycles executing div or sqrt instructions

Cycles summary

Front-end	11.13
Overall L1	11.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 11.75 cycles. At this rate:

10% of peak load performance is reached (10.21 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
21% of peak store performance is reached (10.21 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4360c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
CMP W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 439f10 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0xa710>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ANDS W13, W11, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
ORR X2, XZR, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ORR X1, XZR, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W4, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B.EQ 4361d8 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x69d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4361b4 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x69b4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 436198 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x6998>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 43617c <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x697c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 436160 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x6960>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 436144 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x6944>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CMP W13, #6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 436128 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x6928>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR D3, [X9]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MOVZ W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X9, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X2, X10, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D0, [X9, X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D3, [X10]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STR D0, [X10, X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
LDR D5, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D4, [X1, X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D5, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STR D4, [X2, X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D7, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D6, [X1, X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D7, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STR D6, [X2, X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D17, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D16, [X1, X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D17, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STR D16, [X2, X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D19, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D18, [X1, X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D19, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STR D18, [X2, X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D21, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D20, [X1, X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D21, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STR D20, [X2, X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D23, [X1]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D22, [X1, X6]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D23, [X2]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
STR D22, [X2, X7]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
SUB X2, X2, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W11, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4362a4 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x6aa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR W12, WZR, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W26, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 4362d0 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x6ad0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X2, X18, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SBFM X4, X12, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W1, W8, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X12, X4, X25, X2	1	0	0	0	0	1	0	0	0	0	0	0	2	1
SBFM X13, X1, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MADD X14, X13, X25, X2	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR D16, [X3, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D16, [X3, X14,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
ADD X5, X5, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X9, X9, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W4, W16, W5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X10, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W15, W4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 4360c0 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x68c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ORR W12, WZR, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 4362b0 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x6ab0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code