OV - exec - Loop 554

	Loop Id: 554	Module: exec	Source: advec_mom_kernel.f90-pp.f90:195-195	Coverage: 1.07%

0x41f42c UBFM	X21, X26, #61, #60

0x41f430 ADD	X18, X3, X21

0x41f434 ADD	X14, X28, X21

0x41f438 LD1D	{Z2.D}, P0/Z, [X18, MUL VL]    [2]

0x41f43c LD1D	{Z3.D}, P0/Z, [X14, MUL VL]    [1]

0x41f440 LD1D	{Z4.D}, P0/Z, [X18, X23,LSL #3]    [7]

0x41f444 LD1D	{Z5.D}, P0/Z, [X14, X23,LSL #3]    [9]

0x41f448 ADD	X14, X2, X21

0x41f44c ADD	X18, X29, X21

0x41f450 FADD	Z2.D, Z2.D, Z4.D

0x41f454 FADD	Z3.D, Z3.D, Z5.D

0x41f458 LD1D	{Z4.D}, P0/Z, [X14, MUL VL]    [3]

0x41f45c LD1D	{Z5.D}, P0/Z, [X18, MUL VL]    [4]

0x41f460 LD1D	{Z6.D}, P0/Z, [X14, X23,LSL #3]    [8]

0x41f464 LD1D	{Z7.D}, P0/Z, [X18, X23,LSL #3]    [6]

0x41f468 FADD	Z4.D, Z4.D, Z6.D

0x41f46c FADD	Z5.D, Z5.D, Z7.D

0x41f470 FADD	Z2.D, Z2.D, Z4.D

0x41f474 FADD	Z3.D, Z3.D, Z5.D

0x41f478 FMUL	Z2.D, Z2.D, Z1.D

0x41f47c FMUL	Z3.D, Z3.D, Z1.D

0x41f480 ST1D	{Z2.D}, P0, [X4, X26,LSL #3]    [5]

0x41f484 ST1D	{Z3.D}, P0, [X30, X26,LSL #3]    [10]

0x41f488 ADD	X26, X26, X11

0x41f48c CMP	X27, X26

0x41f490 B.NE	41f42c

/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90: 195 - 195

--------------------------------------------------------------------------------

195:             ! Find staggered mesh mass fluxes and nodal masses and volumes.

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	P10, P11,
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:195-195
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	8
CQA cycles	5.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	5.00
Front-end cycles	3.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.75
P2 cycles	1.75
P3 cycles	1.75
P4 cycles	1.75
P5 cycles	4.00
P6 cycles	4.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	5.00
P10 cycles	5.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.00
Nb uops	26.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	6.40
Nb FLOP add-sub	24.00
Nb FLOP mul	8.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	P10, P11,
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:195-195
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	8
CQA cycles	5.00
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	5.00
Front-end cycles	3.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.75
P2 cycles	1.75
P3 cycles	1.75
P4 cycles	1.75
P5 cycles	4.00
P6 cycles	4.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	5.00
P10 cycles	5.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	26.00
Nb uops	26.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	6.40
Nb FLOP add-sub	24.00
Nb FLOP mul	8.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	256.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:195-195
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90:195.

The related source loop is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

24: addition or subtraction
8: multiply

The binary loop is loading 256 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	26
loop length	104
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.75	1.75	1.75	1.75	4.00	4.00	1.00	1.00	5.00	5.00	0.00	0.00	0.00
cycles	0.50	0.50	1.75	1.75	1.75	1.75	4.00	4.00	4.00	4.00	5.00	5.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.25
Data deps.	1.00
Overall L1	5.00

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

53% of peak load performance is reached (51.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41f42c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
UBFM X21, X26, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X18, X3, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X14, X28, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LD1D {Z2.D}, P0/Z, [X18, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z3.D}, P0/Z, [X14, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z4.D}, P0/Z, [X18, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z5.D}, P0/Z, [X14, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X14, X2, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X18, X29, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FADD Z2.D, Z2.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z3.D, Z3.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z4.D}, P0/Z, [X14, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z5.D}, P0/Z, [X18, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z6.D}, P0/Z, [X14, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z7.D}, P0/Z, [X18, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z4.D, Z4.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z5.D, Z5.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z2.D, Z2.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z3.D, Z3.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z2.D, Z2.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z3.D, Z3.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z2.D}, P0, [X4, X26,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ST1D {Z3.D}, P0, [X30, X26,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X26, X26, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X27, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
B.NE 41f42c <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xd0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:195-195
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

24: addition or subtraction
8: multiply

The binary loop is loading 256 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	26
loop length	104
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.75	1.75	1.75	1.75	4.00	4.00	1.00	1.00	5.00	5.00	0.00	0.00	0.00
cycles	0.50	0.50	1.75	1.75	1.75	1.75	4.00	4.00	4.00	4.00	5.00	5.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.25
Data deps.	1.00
Overall L1	5.00

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

53% of peak load performance is reached (51.20 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
26% of peak store performance is reached (12.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41f42c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
UBFM X21, X26, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X18, X3, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X14, X28, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LD1D {Z2.D}, P0/Z, [X18, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z3.D}, P0/Z, [X14, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z4.D}, P0/Z, [X18, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z5.D}, P0/Z, [X14, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X14, X2, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X18, X29, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FADD Z2.D, Z2.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z3.D, Z3.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z4.D}, P0/Z, [X14, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z5.D}, P0/Z, [X18, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z6.D}, P0/Z, [X14, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z7.D}, P0/Z, [X18, X23,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z4.D, Z4.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z5.D, Z5.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z2.D, Z2.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z3.D, Z3.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z2.D, Z2.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z3.D, Z3.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z2.D}, P0, [X4, X26,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ST1D {Z3.D}, P0, [X30, X26,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X26, X26, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X27, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
B.NE 41f42c <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0xd0c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code