OV - exec - Loop 551

	Loop Id: 551	Module: exec	Source: advec_mom_kernel.f90-pp.f90:204-208	Coverage: 3.08%

0x41fde0 UBFM	X16, X9, #61, #60

0x41fde4 ADD	X17, X2, X16

0x41fde8 ADD	X19, X6, X16

0x41fdec ADD	X23, X7, X16

0x41fdf0 ADD	X16, X21, X16

0x41fdf4 LD1D	{Z4.D}, P0/Z, [X23, X28,LSL #3]    [2]

0x41fdf8 LD1D	{Z5.D}, P0/Z, [X16, X28,LSL #3]    [8]

0x41fdfc LD1D	{Z2.D}, P0/Z, [X17, X28,LSL #3]    [6]

0x41fe00 LD1D	{Z3.D}, P0/Z, [X19, X28,LSL #3]    [10]

0x41fe04 FMUL	Z4.D, Z4.D, Z5.D

0x41fe08 FMAD	Z2.D, P0/M, Z3.D, Z4.D

0x41fe0c LD1D	{Z3.D}, P0/Z, [X17, MUL VL]    [1]

0x41fe10 LD1D	{Z4.D}, P0/Z, [X19, MUL VL]    [4]

0x41fe14 LD1D	{Z5.D}, P0/Z, [X23, MUL VL]    [12]

0x41fe18 LD1D	{Z6.D}, P0/Z, [X16, MUL VL]    [7]

0x41fe1c FMUL	Z5.D, Z5.D, Z6.D

0x41fe20 FMAD	Z3.D, P0/M, Z4.D, Z5.D

0x41fe24 LD1D	{Z4.D}, P0/Z, [X1, X9,LSL #3]    [11]

0x41fe28 FADD	Z2.D, Z2.D, Z3.D

0x41fe2c LD1D	{Z3.D}, P0/Z, [X4, X9,LSL #3]    [5]

0x41fe30 FMUL	Z2.D, Z2.D, Z1.D

0x41fe34 ST1D	{Z2.D}, P0, [X5, X9,LSL #3]    [9]

0x41fe38 FSUB	Z2.D, Z2.D, Z4.D

0x41fe3c FADD	Z2.D, Z3.D, Z2.D

0x41fe40 ST1D	{Z2.D}, P0, [X3, X9,LSL #3]    [3]

0x41fe44 ADD	X9, X9, X11

0x41fe48 CMP	X15, X9

0x41fe4c B.NE	41fde0

/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90: 204 - 208

--------------------------------------------------------------------------------

204:           DO j=x_min,x_max+1

205:             node_mass_post(j,k)=0.25_8*(density1(j  ,k-1)*post_vol(j  ,k-1)                     &

206:               +density1(j  ,k  )*post_vol(j  ,k  )                     &

207:               +density1(j-1,k-1)*post_vol(j-1,k-1)                     &

208:               +density1(j-1,k  )*post_vol(j-1,k  ))

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P10, P11,
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:204-208
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	6.00
Front-end cycles	3.50
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.75
P2 cycles	1.75
P3 cycles	1.75
P4 cycles	1.75
P5 cycles	4.00
P6 cycles	4.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	6.00
P10 cycles	6.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	28.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	6.67
Nb FLOP add-sub	12.00
Nb FLOP mul	12.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P10, P11,
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:204-208
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	6.00
CQA cycles if no scalar integer	6.00
CQA cycles if FP arith vectorized	6.00
CQA cycles if fully vectorized	6.00
Front-end cycles	3.50
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.75
P2 cycles	1.75
P3 cycles	1.75
P4 cycles	1.75
P5 cycles	4.00
P6 cycles	4.00
P7 cycles	4.00
P8 cycles	4.00
P9 cycles	6.00
P10 cycles	6.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	28.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	6.67
Nb FLOP add-sub	12.00
Nb FLOP mul	12.00
Nb FLOP fma	8.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:204-208
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90:204-208.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 40 FP arithmetical operations:

20: addition or subtraction (8 inside FMA instructions)
20: multiply (8 inside FMA instructions)

The binary loop is loading 320 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	28
loop length	112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.75	1.75	1.75	1.75	4.00	4.00	1.00	1.00	6.00	6.00	0.00	0.00	0.00
cycles	0.50	0.50	1.75	1.75	1.75	1.75	4.00	4.00	4.00	4.00	6.00	6.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.50
Data deps.	1.00
Overall L1	6.00

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

55% of peak load performance is reached (53.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41fde0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
UBFM X16, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X17, X2, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X19, X6, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X23, X7, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X16, X21, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LD1D {Z4.D}, P0/Z, [X23, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z5.D}, P0/Z, [X16, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z2.D}, P0/Z, [X17, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z3.D}, P0/Z, [X19, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z4.D, Z4.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z2.D, P0/M, Z3.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1D {Z3.D}, P0/Z, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z4.D}, P0/Z, [X19, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z5.D}, P0/Z, [X23, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z6.D}, P0/Z, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z5.D, Z5.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z3.D, P0/M, Z4.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1D {Z4.D}, P0/Z, [X1, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z2.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z3.D}, P0/Z, [X4, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z2.D, Z2.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z2.D}, P0, [X5, X9,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
FSUB Z2.D, Z2.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z2.D, Z3.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z2.D}, P0, [X3, X9,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X9, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X15, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
B.NE 41fde0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x16c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:204-208
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 40 FP arithmetical operations:

20: addition or subtraction (8 inside FMA instructions)
20: multiply (8 inside FMA instructions)

The binary loop is loading 320 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	28
loop length	112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.75	1.75	1.75	1.75	4.00	4.00	1.00	1.00	6.00	6.00	0.00	0.00	0.00
cycles	0.50	0.50	1.75	1.75	1.75	1.75	4.00	4.00	4.00	4.00	6.00	6.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.50
Data deps.	1.00
Overall L1	6.00

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.00 cycles. At this rate:

55% of peak load performance is reached (53.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41fde0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
UBFM X16, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X17, X2, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X19, X6, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X23, X7, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X16, X21, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LD1D {Z4.D}, P0/Z, [X23, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z5.D}, P0/Z, [X16, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z2.D}, P0/Z, [X17, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z3.D}, P0/Z, [X19, X28,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z4.D, Z4.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z2.D, P0/M, Z3.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1D {Z3.D}, P0/Z, [X17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z4.D}, P0/Z, [X19, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z5.D}, P0/Z, [X23, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z6.D}, P0/Z, [X16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z5.D, Z5.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMAD Z3.D, P0/M, Z4.D, Z5.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1D {Z4.D}, P0/Z, [X1, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z2.D, Z2.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z3.D}, P0/Z, [X4, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z2.D, Z2.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z2.D}, P0, [X5, X9,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
FSUB Z2.D, Z2.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FADD Z2.D, Z3.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z2.D}, P0, [X3, X9,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X9, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X15, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
B.NE 41fde0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x16c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code