OV - exec - Loop 550

	Loop Id: 550	Module: exec	Source: advec_mom_kernel.f90-pp.f90:201-210	Coverage: 0.01%

0x41fd68 LDP	X9, X8, [SP, #72]

0x41fd6c ADD	X2, X2, X18

0x41fd70 ADD	X3, X3, X18

0x41fd74 SUBS	W10, W10, #1

0x41fd78 ADD	X4, X4, X18

0x41fd7c ADD	X5, X5, X18

0x41fd80 ADD	X6, X6, X0

0x41fd84 ADD	X7, X7, X18

0x41fd88 ADD	X1, X1, X18

0x41fd8c ADD	X21, X21, X0

0x41fd90 ADD	X22, X22, X8

0x41fd94 ADD	X25, X25, X9

0x41fd98 ADD	X26, X26, X8

0x41fd9c ADD	X27, X27, X9

0x41fda0 B.LE	41fef0

0x41fda4 LDR	X8, [SP, #88]

0x41fda8 LDR	W30, [SP, #96]

0x41fdac ORR	X29, XZR, X24

0x41fdb0 CMP	X8, X11

0x41fdb4 B.CC	41fe54

0x41fdb8 LDR	X12, [SP, #88]

0x41fdbc LDR	W16, [SP, #96]

0x41fdc0 ORR	X9, XZR, XZR

0x41fdc4 UDIV	X8, X12, X11

0x41fdc8 MADD	X15, X8, X11, XZR

0x41fdcc SUB	X8, X12, X15

0x41fdd0 ADD	X29, X15, X24

0x41fdd4 SUB	W30, W16, W15

0x41fdd8 HINT	#0

0x41fddc HINT	#0

  (551) 0x41fde0 UBFM	X16, X9, #61, #60

  (551) 0x41fde4 ADD	X17, X2, X16

  (551) 0x41fde8 ADD	X19, X6, X16

  (551) 0x41fdec ADD	X23, X7, X16

  (551) 0x41fdf0 ADD	X16, X21, X16

  (551) 0x41fdf4 LD1D	{Z4.D}, P0/Z, [X23, X28,LSL #3]

  (551) 0x41fdf8 LD1D	{Z5.D}, P0/Z, [X16, X28,LSL #3]

  (551) 0x41fdfc LD1D	{Z2.D}, P0/Z, [X17, X28,LSL #3]

  (551) 0x41fe00 LD1D	{Z3.D}, P0/Z, [X19, X28,LSL #3]

  (551) 0x41fe04 FMUL	Z4.D, Z4.D, Z5.D

  (551) 0x41fe08 FMAD	Z2.D, P0/M, Z3.D, Z4.D

  (551) 0x41fe0c LD1D	{Z3.D}, P0/Z, [X17, MUL VL]

  (551) 0x41fe10 LD1D	{Z4.D}, P0/Z, [X19, MUL VL]

  (551) 0x41fe14 LD1D	{Z5.D}, P0/Z, [X23, MUL VL]

  (551) 0x41fe18 LD1D	{Z6.D}, P0/Z, [X16, MUL VL]

  (551) 0x41fe1c FMUL	Z5.D, Z5.D, Z6.D

  (551) 0x41fe20 FMAD	Z3.D, P0/M, Z4.D, Z5.D

  (551) 0x41fe24 LD1D	{Z4.D}, P0/Z, [X1, X9,LSL #3]

  (551) 0x41fe28 FADD	Z2.D, Z2.D, Z3.D

  (551) 0x41fe2c LD1D	{Z3.D}, P0/Z, [X4, X9,LSL #3]

  (551) 0x41fe30 FMUL	Z2.D, Z2.D, Z1.D

  (551) 0x41fe34 ST1D	{Z2.D}, P0, [X5, X9,LSL #3]

  (551) 0x41fe38 FSUB	Z2.D, Z2.D, Z4.D

  (551) 0x41fe3c FADD	Z2.D, Z3.D, Z2.D

  (551) 0x41fe40 ST1D	{Z2.D}, P0, [X3, X9,LSL #3]

  (551) 0x41fe44 ADD	X9, X9, X11

  (551) 0x41fe48 CMP	X15, X9

  (551) 0x41fe4c B.NE	41fde0

0x41fe50 CBZ	X8, 41fd68

0x41fe54 LDR	X9, [SP, #40]

0x41fe58 ADD	X8, X29, X22

0x41fe5c ADD	X23, X29, X26

0x41fe60 ADD	W30, W30, #1

0x41fe64 UBFM	X8, X8, #61, #60

0x41fe68 ADD	X15, X29, X25

0x41fe6c ADD	X29, X29, X27

0x41fe70 UBFM	X24, X23, #61, #60

0x41fe74 ORR	X19, XZR, XZR

0x41fe78 ADD	X15, X14, X15,LSL #3

0x41fe7c ADD	X29, X14, X29,LSL #3

0x41fe80 ADD	X17, X9, X8

0x41fe84 LDP	X9, X12, [SP, #48]

0x41fe88 ADD	X16, X12, X8

0x41fe8c ADD	X23, X12, X24

0x41fe90 ADD	X24, X13, X24

0x41fe94 ADD	X9, X9, X8

0x41fe98 ADD	X8, X13, X8

0x41fe9c HINT	#0

  (549) 0x41fea0 LDR	Q4, [X24, X19]

  (549) 0x41fea4 LDR	Q5, [X29, X19]

  (549) 0x41fea8 LDR	Q2, [X8, X19]

  (549) 0x41feac SUB	W30, W30, #1

  (549) 0x41feb0 CMP	W30, #1

  (549) 0x41feb4 LDR	Q3, [X15, X19]

  (549) 0x41feb8 FMUL	V4.2D, V4.2D, V5.2D

  (549) 0x41febc FMLA	V4.2D, V3.2D, V2.2D

  (549) 0x41fec0 LDR	D3, [X16, X19]

  (549) 0x41fec4 FADDP	D2, V4.2D

  (549) 0x41fec8 LDR	D4, [X23, X19]

  (549) 0x41fecc FMUL	D2, D2, D0

  (549) 0x41fed0 STR	D2, [X9, X19]

  (549) 0x41fed4 FSUB	D2, D2, S4

  (549) 0x41fed8 FADD	D2, D3, D2

  (549) 0x41fedc STR	D2, [X17, X19]

  (549) 0x41fee0 ADD	X19, X19, #8

  (549) 0x41fee4 B.HI	41fea0

0x41fee8 LDR	X24, [SP, #64]

0x41feec B	41fd68

/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90: 201 - 210

--------------------------------------------------------------------------------

201:         !$OMP DO

202:         DO k=y_min-1,y_max+2

203:         !$OMP SIMD

204:           DO j=x_min,x_max+1

205:             node_mass_post(j,k)=0.25_8*(density1(j  ,k-1)*post_vol(j  ,k-1)                     &

206:               +density1(j  ,k  )*post_vol(j  ,k  )                     &

207:               +density1(j-1,k-1)*post_vol(j-1,k-1)                     &

208:               +density1(j-1,k  )*post_vol(j-1,k  ))

209:             node_mass_pre(j,k)=node_mass_post(j,k)-node_flux(j,k-1)+node_flux(j,k)

210:           ENDDO

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.38
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.51
Bottlenecks
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:201-203,advec_mom_kernel.f90-pp.f90:209-210
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.50
CQA cycles if no scalar integer	6.50
CQA cycles if FP arith vectorized	6.50
CQA cycles if fully vectorized	1.48
Front-end cycles	4.31
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	6.50
P2 cycles	6.50
P3 cycles	6.50
P4 cycles	6.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.83
P10 cycles	1.83
P11 cycles	1.83
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.50 - 0.25
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	34.50
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.68
Bytes prefetched	0.00
Bytes loaded	50.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.21
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	24.06
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.31
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.45
Bottlenecks	P2, P3, P4, P5,
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:201-203,advec_mom_kernel.f90-pp.f90:209-210
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.25
CQA cycles if no scalar integer	5.25
CQA cycles if FP arith vectorized	5.25
CQA cycles if fully vectorized	1.22
Front-end cycles	3.63
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	5.25
P2 cycles	5.25
P3 cycles	5.25
P4 cycles	5.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	1.67
P10 cycles	1.67
P11 cycles	1.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	29.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.62
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.34
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	24.17
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.43
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.55
Bottlenecks	P2, P3, P4, P5,
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:201-203,advec_mom_kernel.f90-pp.f90:209-210
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.75
CQA cycles if no scalar integer	7.75
CQA cycles if FP arith vectorized	7.75
CQA cycles if fully vectorized	1.75
Front-end cycles	5.00
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	7.75
P2 cycles	7.75
P3 cycles	7.75
P4 cycles	7.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.00
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	41.00
Nb uops	40.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	7.74
Bytes prefetched	0.00
Bytes loaded	60.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.07
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	23.96
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:201-210
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90:201-210.

Analyzed code is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90:201-203,209-210.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.50 to 1.48 cycles (4.38x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 50 bytes.

General properties

nb instructions	36
loop length	144
nb stack references	0

Front-end

front end

4.31 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	6.50	6.50	6.50	6.50	0.00	0.00	0.00	0.00	1.83	1.83	1.83	0.00	0.00
cycles	1.50	1.50	6.50	6.50	6.50	6.50	0.00	0.00	0.00	0.00	1.83	1.83	1.83	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	0.50-0.25
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.31
Data deps.	1.00
Overall L1	6.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.50 cycles. At this rate:

8% of peak load performance is reached (7.68 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:201-210
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 40 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	1.67	1.67	1.67	0.00	0.00
cycles	1.50	1.50	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	1.67	1.67	1.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.63
Data deps.	1.00
Overall L1	5.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.25 cycles. At this rate:

7% of peak load performance is reached (7.62 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41fda4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDP X9, X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X2, X2, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X3, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W10, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X4, X4, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X5, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X6, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X7, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X21, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X22, X22, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X25, X25, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X26, X26, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X27, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.LE 41fef0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x17d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X29, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 41fe54 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1734>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X12, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W16, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X9, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UDIV X8, X12, X11	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
MADD X15, X8, X11, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X8, X12, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X29, X15, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W30, W16, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
CBZ X8, 41fd68 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1648>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:201-210
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 60 bytes.

General properties

nb instructions	41
loop length	164
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	7.75	7.75	7.75	7.75	0.00	0.00	0.00	0.00	2.00	2.00	2.00	0.00	0.00
cycles	1.50	1.50	7.75	7.75	7.75	7.75	0.00	0.00	0.00	0.00	2.00	2.00	2.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.00
Data deps.	1.00
Overall L1	7.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.75 cycles. At this rate:

8% of peak load performance is reached (7.74 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41fda4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDP X9, X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X2, X2, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X3, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W10, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X4, X4, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X5, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X6, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X7, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X21, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X22, X22, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X25, X25, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X26, X26, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X27, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.LE 41fef0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x17d0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X29, XZR, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X8, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 41fe54 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1734>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X29, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X23, X29, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W30, W30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X8, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X29, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X29, X29, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X24, X23, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X19, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X14, X15,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X29, X14, X29,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X9, X12, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X16, X12, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X23, X12, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X13, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X13, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
LDR X24, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 41fd68 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1648>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code