OV - exec - Loop 549

0x41fea0 LDR	Q4, [X24, X19]    [1]

0x41fea4 LDR	Q5, [X29, X19]    [8]

0x41fea8 LDR	Q2, [X8, X19]    [6]

0x41feac SUB	W30, W30, #1

0x41feb0 CMP	W30, #1

0x41feb4 LDR	Q3, [X15, X19]    [2]

0x41feb8 FMUL	V4.2D, V4.2D, V5.2D

0x41febc FMLA	V4.2D, V3.2D, V2.2D

0x41fec0 LDR	D3, [X16, X19]    [4]

0x41fec4 FADDP	D2, V4.2D

0x41fec8 LDR	D4, [X23, X19]    [7]

0x41fecc FMUL	D2, D2, D0

0x41fed0 STR	D2, [X9, X19]    [5]

0x41fed4 FSUB	D2, D2, S4

0x41fed8 FADD	D2, D3, D2

0x41fedc STR	D2, [X17, X19]    [3]

0x41fee0 ADD	X19, X19, #8

0x41fee4 B.HI	41fea0

/home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90: 204 - 209

--------------------------------------------------------------------------------

204:           DO j=x_min,x_max+1

205:             node_mass_post(j,k)=0.25_8*(density1(j  ,k-1)*post_vol(j  ,k-1)                     &

206:               +density1(j  ,k  )*post_vol(j  ,k  )                     &

207:               +density1(j-1,k-1)*post_vol(j-1,k-1)                     &

208:               +density1(j-1,k  )*post_vol(j-1,k  ))

209:             node_mass_pre(j,k)=node_mass_post(j,k)-node_flux(j,k-1)+node_flux(j,k)

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.19
Bottlenecks	P10, P11, P12,
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:204-209
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	1
CQA cycles	2.67
CQA cycles if no scalar integer	2.67
CQA cycles if FP arith vectorized	2.67
CQA cycles if fully vectorized	1.00
Front-end cycles	2.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.67
P10 cycles	2.67
P11 cycles	2.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.00
Nb uops	18.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	3.75
Nb FLOP add-sub	3.00
Nb FLOP mul	3.00
Nb FLOP fma	2.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	36.00
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	50.00
Vectorization ratio load	66.67
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	35.42
Vector-efficiency ratio load	41.67
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	2.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.19
Bottlenecks	P10, P11, P12,
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:204-209
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	1
CQA cycles	2.67
CQA cycles if no scalar integer	2.67
CQA cycles if FP arith vectorized	2.67
CQA cycles if fully vectorized	1.00
Front-end cycles	2.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.67
P10 cycles	2.67
P11 cycles	2.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.00
Nb uops	18.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	3.75
Nb FLOP add-sub	3.00
Nb FLOP mul	3.00
Nb FLOP fma	2.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	36.00
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	50.00
Vectorization ratio load	66.67
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	35.42
Vector-efficiency ratio load	41.67
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:204-209
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90:204-209.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

use profile-guided optimization flags of your compiler
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace do i=1,n foo(i) with: select case (n) case (4): do i=1,4 foo(i) case (6): do i=1,6 foo(i) default : do i=1,n foo(i) end select

Vectorization

Your loop is partially vectorized. Only 35% of vector register length is used (average across all VPU instructions).

Details

50% of VPU instructions are used in vector version (process two or more data elements in vector registers):

66% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 2 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 10 FP arithmetical operations:

5: addition or subtraction (2 inside FMA instructions)
5: multiply (2 inside FMA instructions)

The binary loop is loading 80 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	18
loop length	72
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	0.75	0.75	2.00	2.00	2.00	2.00	2.67	2.67	2.67	0.00	0.00
cycles	0.50	0.50	0.75	0.75	0.75	0.75	2.00	2.00	2.00	2.00	2.67	2.67	2.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.25
Data deps.	1.00
Overall L1	2.67

Vectorization ratios

INT

all	40%
load	66%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

FP

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	50%
load	66%
store	0%
mul	100%
add-sub	0%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.67 cycles. At this rate:

31% of peak load performance is reached (30.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41fea0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR Q4, [X24, X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR Q5, [X29, X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR Q2, [X8, X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUB W30, W30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
LDR Q3, [X15, X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL V4.2D, V4.2D, V5.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMLA V4.2D, V3.2D, V2.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D3, [X16, X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADDP D2, V4.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR D4, [X23, X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D2, D2, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR D2, [X9, X19]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
FSUB D2, D2, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D2, D3, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D2, [X17, X19]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X19, X19, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.HI 41fea0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1780>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:204-209
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90:204-209.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

use profile-guided optimization flags of your compiler
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace do i=1,n foo(i) with: select case (n) case (4): do i=1,4 foo(i) case (6): do i=1,6 foo(i) default : do i=1,n foo(i) end select

Vectorization

Your loop is partially vectorized. Only 35% of vector register length is used (average across all VPU instructions).

Details

50% of VPU instructions are used in vector version (process two or more data elements in vector registers):

66% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 2 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 10 FP arithmetical operations:

5: addition or subtraction (2 inside FMA instructions)
5: multiply (2 inside FMA instructions)

The binary loop is loading 80 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	18
loop length	72
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	0.75	0.75	2.00	2.00	2.00	2.00	2.67	2.67	2.67	0.00	0.00
cycles	0.50	0.50	0.75	0.75	0.75	0.75	2.00	2.00	2.00	2.00	2.67	2.67	2.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.25
Data deps.	1.00
Overall L1	2.67

Vectorization ratios

INT

all	40%
load	66%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

FP

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	50%
load	66%
store	0%
mul	100%
add-sub	0%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.67 cycles. At this rate:

31% of peak load performance is reached (30.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
12% of peak store performance is reached (6.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41fea0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR Q4, [X24, X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR Q5, [X29, X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR Q2, [X8, X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUB W30, W30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W30, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
LDR Q3, [X15, X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL V4.2D, V4.2D, V5.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMLA V4.2D, V3.2D, V2.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D3, [X16, X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FADDP D2, V4.2D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR D4, [X23, X19]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D2, D2, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR D2, [X9, X19]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
FSUB D2, D2, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D2, D3, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
STR D2, [X17, X19]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X19, X19, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.HI 41fea0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1780>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code