OV - exec - Loop 540

	Loop Id: 540	Module: exec	Source: advec_mom_kernel.f90-pp.f90:215-241 [...]	Coverage: 3.89%

0x42000c FSUB	D4, D0, S4

0x420010 SUB	W2, W2, #1

0x420014 CMP	W2, #1

0x420018 FMADD	D4, D4, D16, D5

0x42001c FMUL	D3, D3, D4

0x420020 STR	D3, [X13, X3,LSL #3]    [1]

0x420024 ADD	X3, X3, #1

0x420028 B.LE	41ffe0

0x42002c LDR	D3, [X16, X3,LSL #3]    [6]

0x420030 MOVI	D16, #0

0x420034 FCMP	D3, #0

0x420038 FABS	D4, D3

0x42003c CSINC	W5, W8, W8, #5

0x420040 CSEL	W4, W0, W1, #5

0x420044 SBFM	X5, X5, #0, #31

0x420048 SBFM	X4, X4, #0, #31

0x42004c MADD	X5, X10, X5, X3

0x420050 MADD	X4, X10, X4, X3

0x420054 LDR	D5, [X11, X5,LSL #3]    [5]

0x420058 LDR	D6, [X12, X4,LSL #3]    [8]

0x42005c CSINC	X4, X8, X8, #4

0x420060 MADD	X4, X10, X4, X3

0x420064 FDIV	D4, D4, D5

0x420068 LDR	D5, [X12, X5,LSL #3]    [9]

0x42006c FSUB	D7, D5, S6

0x420070 LDR	D6, [X12, X4,LSL #3]    [7]

0x420074 FSUB	D6, D6, S5

0x420078 FMUL	D17, D7, D6

0x42007c FCMP	D17, #0

0x420080 B.LE	42000c

0x420084 LDP	X5, X6, [X20, #312]    [4]

0x420088 FCMP	D3, #0

0x42008c FABS	D7, D7

0x420090 FADD	D18, D4, D0

0x420094 CSEL	W4, W0, W18, #5

0x420098 FMUL	D18, D18, D7

0x42009c FABS	D17, D6

0x4200a0 SBFM	X4, X4, #0, #31

0x4200a4 LDR	X6, [X6]    [3]

0x4200a8 SUB	X4, X4, X6

0x4200ac SUB	X7, X8, X6

0x4200b0 LDR	D19, [X5, X4,LSL #3]    [2]

0x4200b4 LDR	D16, [X5, X7,LSL #3]    [10]

0x4200b8 FDIV	D18, D18, D19

0x4200bc FSUB	D19, D1, S4

0x4200c0 FMUL	D19, D19, D17

0x4200c4 FDIV	D19, D19, D16

0x4200c8 FADD	D18, D19, D18

0x4200cc FMUL	D16, D16, D18

0x4200d0 FDIV	D16, D16, D2

0x4200d4 FCMP	D16, D7

0x4200d8 FCSEL	D7, D7, D16, #10

0x4200dc FCMP	D7, D17

0x4200e0 FCSEL	D7, D17, D7, #10

0x4200e4 FCMP	D6, #0

0x4200e8 FNEG	D16, D7

0x4200ec FCSEL	D16, D7, D16, #8

0x4200f0 B	42000c

/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90: 215 - 241

--------------------------------------------------------------------------------

215:         DO j=x_min,x_max+1

[...]

227: # 227 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_mom_kernel.f90"

228:           sigma=ABS(node_flux(j,k))/(node_mass_pre(j,donor))

229:           width=celldy(k)

230:           vdiffuw=vel1(j,donor)-vel1(j,upwind)

231:           vdiffdw=vel1(j,downwind)-vel1(j,donor)

232:           limiter=0.0

233:           IF(vdiffuw*vdiffdw.GT.0.0)THEN

234:             auw=ABS(vdiffuw)

235:             adw=ABS(vdiffdw)

236:             wind=1.0_8

237:             IF(vdiffdw.LE.0.0) wind=-1.0_8

238:             limiter=wind*MIN(width*((2.0_8-sigma)*adw/width+(1.0_8+sigma)*auw/celldy(dif))/6.0_8,auw,adw)

239:           ENDIF

240:           advec_vel_s=vel1(j,donor)+(1.0_8-sigma)*limiter

241:           mom_flux(j,k)=advec_vel_s*node_flux(j,k)

Path /

Metric	Value
CQA speedup if no scalar integer	2.30
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.49 - 7.22
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.12
Bottlenecks
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:215-215,advec_mom_kernel.f90-pp.f90:227-241
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.75
CQA cycles if no scalar integer	2.50
CQA cycles if FP arith vectorized	5.75
CQA cycles if fully vectorized	1.28 - 0.80
Front-end cycles	5.50
DIV/SQRT cycles	1.25
P0 cycles	1.25
P1 cycles	3.25
P2 cycles	3.25
P3 cycles	3.38
P4 cycles	3.13
P5 cycles	5.38
P6 cycles	5.38
P7 cycles	5.38
P8 cycles	5.38
P9 cycles	2.83
P10 cycles	2.50
P11 cycles	2.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	2.50 - 1.25
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	44.00
Nb uops	44.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.17
Nb FLOP add-sub	4.50
Nb FLOP mul	3.50
Nb FLOP fma	1.00
Nb FLOP div	2.50
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.08
Bytes prefetched	0.00
Bytes loaded	60.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	22.47
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Metric	Value
CQA speedup if no scalar integer	2.74
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.88 - 7.52
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.07
Bottlenecks	P6, P7, P8, P9,
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:215-215,advec_mom_kernel.f90-pp.f90:227-241
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.75
CQA cycles if no scalar integer	2.83
CQA cycles if FP arith vectorized	7.75
CQA cycles if fully vectorized	2.00 - 1.03
Front-end cycles	7.25
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	3.75
P2 cycles	3.75
P3 cycles	3.75
P4 cycles	3.75
P5 cycles	7.75
P6 cycles	7.75
P7 cycles	7.75
P8 cycles	7.75
P9 cycles	3.50
P10 cycles	3.17
P11 cycles	3.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	4.00 - 2.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	58.00
Nb uops	58.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.19
Nb FLOP add-sub	6.00
Nb FLOP mul	5.00
Nb FLOP fma	1.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.35
Bytes prefetched	0.00
Bytes loaded	80.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	22.73
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Metric	Value
CQA speedup if no scalar integer	1.73
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.67
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.25
Bottlenecks	micro-operation queue,
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:215-215,advec_mom_kernel.f90-pp.f90:227-241
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.75
CQA cycles if no scalar integer	2.17
CQA cycles if FP arith vectorized	3.75
CQA cycles if fully vectorized	0.56
Front-end cycles	3.75
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	2.75
P2 cycles	2.75
P3 cycles	3.00
P4 cycles	2.50
P5 cycles	3.00
P6 cycles	3.00
P7 cycles	3.00
P8 cycles	3.00
P9 cycles	2.17
P10 cycles	1.83
P11 cycles	2.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	30.00
Nb uops	30.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	2.13
Nb FLOP add-sub	3.00
Nb FLOP mul	2.00
Nb FLOP fma	1.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	12.80
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	22.22
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:215-241
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90:215,227-241.

The related source loop is not unrolled or unrolled with no peel/tail loop.
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 22% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.75 to 0.80 cycles (7.22x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 12.5 FP arithmetical operations:

5.50: addition or subtraction (1 inside FMA instructions)
4.50: multiply (1 inside FMA instructions)
2.50: divide

The binary loop is loading 60 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.18 FP operations per loaded or stored byte.

General properties

nb instructions	44
loop length	176
nb stack references	0

Front-end

front end

5.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.25	1.25	3.25	3.25	3.38	3.13	5.38	5.38	5.38	5.38	2.83	2.50	2.67	0.00	0.00
cycles	1.25	1.25	3.25	3.25	3.38	3.13	5.38	5.38	5.38	5.38	2.83	2.50	2.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	2.50-1.25
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	5.50
Data deps.	1.00
Overall L1	5.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.75 cycles. At this rate:

10% of peak load performance is reached (10.49 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.58 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:215-241
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.75 to 2.83 cycles (2.74x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 17 FP arithmetical operations:

7: addition or subtraction (1 inside FMA instructions)
6: multiply (1 inside FMA instructions)
4: divide

The binary loop is loading 80 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	58
loop length	232
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	3.75	3.75	3.75	3.75	7.75	7.75	7.75	7.75	3.50	3.17	3.33	0.00	0.00
cycles	1.50	1.50	3.75	3.75	3.75	3.75	7.75	7.75	7.75	7.75	3.50	3.17	3.33	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	4.00-2.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.25
Data deps.	1.00
Overall L1	7.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.75 cycles. At this rate:

10% of peak load performance is reached (10.32 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.03 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 42002c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
FSUB D4, D0, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SUB W2, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
FMADD D4, D4, D16, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D3, D3, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR D3, [X13, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.LE 41ffe0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x18c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D3, [X16, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MOVI D16, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMP D3, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FABS D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
CSINC W5, W8, W8, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CSEL W4, W0, W1, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X5, X5, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X4, X4, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X5, X10, X5, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X4, X10, X4, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR D5, [X11, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D6, [X12, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
CSINC X4, X8, X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X4, X10, X4, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FDIV D4, D4, D5	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
LDR D5, [X12, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSUB D7, D5, S6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR D6, [X12, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSUB D6, D6, S5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D17, D7, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMP D17, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LE 42000c <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x18ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDP X5, X6, [X20, #312]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	1
FCMP D3, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FABS D7, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FADD D18, D4, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
CSEL W4, W0, W18, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMUL D18, D18, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FABS D17, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SBFM X4, X4, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR X6, [X6]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB X4, X4, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB X7, X8, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D19, [X5, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D16, [X5, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FDIV D18, D18, D19	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FSUB D19, D1, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D19, D19, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FDIV D19, D19, D16	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FADD D18, D19, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D16, D16, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FDIV D16, D16, D2	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FCMP D16, D7	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FCSEL D7, D7, D16, #10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMP D7, D17	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FCSEL D7, D17, D7, #10	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMP D6, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FNEG D16, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCSEL D16, D7, D16, #8	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
B 42000c <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x18ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:215-241
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.75 to 2.17 cycles (1.73x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

4: addition or subtraction (1 inside FMA instructions)
3: multiply (1 inside FMA instructions)
1: divide

The binary loop is loading 40 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	30
loop length	120
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.00	1.00	2.75	2.75	3.00	2.50	3.00	3.00	3.00	3.00	2.17	1.83	2.00	0.00	0.00
cycles	1.00	1.00	2.75	2.75	3.00	2.50	3.00	3.00	3.00	3.00	2.17	1.83	2.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.75
Data deps.	1.00
Overall L1	3.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.75 cycles. At this rate:

11% of peak load performance is reached (10.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.13 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 42002c

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
FSUB D4, D0, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
SUB W2, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
FMADD D4, D4, D16, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D3, D3, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR D3, [X13, X3,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X3, X3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.LE 41ffe0 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x18c0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D3, [X16, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MOVI D16, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMP D3, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FABS D4, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
CSINC W5, W8, W8, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CSEL W4, W0, W1, #5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X5, X5, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X4, X4, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X5, X10, X5, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X4, X10, X4, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR D5, [X11, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D6, [X12, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
CSINC X4, X8, X8, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X4, X10, X4, X3	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FDIV D4, D4, D5	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
LDR D5, [X12, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSUB D7, D5, S6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR D6, [X12, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSUB D6, D6, S5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D17, D7, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FCMP D17, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LE 42000c <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x18ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code