OV - exec - Loop 537

	Loop Id: 537	Module: exec	Source: advec_mom_kernel.f90-pp.f90:247-250	Coverage: 0.01%

0x420240 ADD	X1, X1, X18

0x420244 ADD	X0, X0, X18

0x420248 SUBS	W10, W10, #1

0x42024c ADD	X2, X2, X18

0x420250 ADD	X3, X3, X18

0x420254 ADD	X4, X4, X18

0x420258 ADD	X5, X5, X18

0x42025c ADD	X6, X6, X18

0x420260 ADD	X7, X7, X18

0x420264 ADD	X20, X20, X18

0x420268 ADD	X21, X21, X18

0x42026c ADD	X22, X22, X11

0x420270 ADD	X23, X23, X11

0x420274 B.LE	420378

0x420278 ORR	X25, XZR, X8

0x42027c ORR	W24, WZR, W9

0x420280 CMP	X17, X16

0x420284 B.CC	420318

0x420288 UDIV	X12, X17, X16

0x42028c ORR	X19, XZR, XZR

0x420290 ADDVL	X28, X0, #1

0x420294 ADDVL	X29, X3, #1

0x420298 ADDVL	X30, X5, #1

0x42029c ADDVL	X14, X21, #1

0x4202a0 MADD	X26, X12, X16, XZR

0x4202a4 ADDVL	X12, X7, #1

0x4202a8 SUB	X27, X17, X26

0x4202ac ADD	X25, X26, X8

0x4202b0 SUB	W24, W9, W26

0x4202b4 HINT	#0

0x4202b8 HINT	#0

0x4202bc HINT	#0

  (538) 0x4202c0 LD1D	{Z0.D}, P0/Z, [X1, X19,LSL #3]

  (538) 0x4202c4 LD1D	{Z1.D}, P0/Z, [X28, X19,LSL #3]

  (538) 0x4202c8 LD1D	{Z2.D}, P0/Z, [X20, X19,LSL #3]

  (538) 0x4202cc LD1D	{Z3.D}, P0/Z, [X14, X19,LSL #3]

  (538) 0x4202d0 LD1D	{Z4.D}, P0/Z, [X6, X19,LSL #3]

  (538) 0x4202d4 FMLA	Z0.D, P0/M, Z2.D, Z4.D

  (538) 0x4202d8 LD1D	{Z5.D}, P0/Z, [X12, X19,LSL #3]

  (538) 0x4202dc FMLA	Z1.D, P0/M, Z3.D, Z5.D

  (538) 0x4202e0 LD1D	{Z2.D}, P0/Z, [X4, X19,LSL #3]

  (538) 0x4202e4 LD1D	{Z3.D}, P0/Z, [X30, X19,LSL #3]

  (538) 0x4202e8 FSUB	Z0.D, Z0.D, Z2.D

  (538) 0x4202ec FSUB	Z1.D, Z1.D, Z3.D

  (538) 0x4202f0 LD1D	{Z2.D}, P0/Z, [X2, X19,LSL #3]

  (538) 0x4202f4 LD1D	{Z3.D}, P0/Z, [X29, X19,LSL #3]

  (538) 0x4202f8 FDIV	Z0.D, P0/M, Z0.D, Z2.D

  (538) 0x4202fc FDIV	Z1.D, P0/M, Z1.D, Z3.D

  (538) 0x420300 ST1D	{Z0.D}, P0, [X6, X19,LSL #3]

  (538) 0x420304 ST1D	{Z1.D}, P0, [X12, X19,LSL #3]

  (538) 0x420308 ADD	X19, X19, X16

  (538) 0x42030c CMP	X26, X19

  (538) 0x420310 B.NE	4202c0

0x420314 CBZ	X27, 420240

0x420318 ADD	X12, X25, X22

0x42031c LDR	X14, [SP, #88]

0x420320 ADD	W24, W24, #1

0x420324 ADD	X19, X13, X12,LSL #3

0x420328 ADD	X12, X25, X23

0x42032c UBFM	X12, X12, #61, #60

0x420330 ADD	X27, X14, X12

0x420334 LDR	X14, [SP, #96]

0x420338 ADD	X25, X15, X12

0x42033c ADD	X26, X13, X12

0x420340 ADD	X28, X14, X12

  (536) 0x420344 LDR	D2, [X27]

  (536) 0x420348 LDR	D0, [X19], #8

  (536) 0x42034c LDR	D1, [X28], #8

  (536) 0x420350 FMADD	D0, D1, D2, D0

  (536) 0x420354 SUB	W24, W24, #1

  (536) 0x420358 CMP	W24, #1

  (536) 0x42035c LDR	D1, [X26], #8

  (536) 0x420360 FSUB	D0, D0, S1

  (536) 0x420364 LDR	D1, [X25], #8

  (536) 0x420368 FDIV	D0, D0, D1

  (536) 0x42036c STR	D0, [X27], #8

  (536) 0x420370 B.HI	420344

0x420374 B	420240

/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90: 247 - 250

--------------------------------------------------------------------------------

247:       !$OMP SIMD

248:         DO j=x_min,x_max+1

249:           vel1 (j,k)=(vel1(j,k)*node_mass_pre(j,k)+mom_flux(j,k-1)-mom_flux(j,k))/node_mass_post(j,k)

250:         ENDDO

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.80
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.71
Bottlenecks	P2, P3, P4, P5,
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:247-250
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.00
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	9.00
CQA cycles if fully vectorized	1.88
Front-end cycles	5.25
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	9.00
P2 cycles	9.00
P3 cycles	9.00
P4 cycles	9.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.67
P10 cycles	0.67
P11 cycles	0.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	45.00
Nb uops	42.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.78
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.21
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	23.37
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	21.88

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.80
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.71
Bottlenecks	P2, P3, P4, P5,
Function	advec_mom_kernel
Source	advec_mom_kernel.f90-pp.f90:247-250
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.00
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	9.00
CQA cycles if fully vectorized	1.88
Front-end cycles	5.25
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	9.00
P2 cycles	9.00
P3 cycles	9.00
P4 cycles	9.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.67
P10 cycles	0.67
P11 cycles	0.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	45.00
Nb uops	42.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	1.78
Bytes prefetched	0.00
Bytes loaded	16.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.21
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	23.37
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	21.88

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:247-250
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90:247-250.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 9.00 to 1.87 cycles (4.80x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 16 bytes.

General properties

nb instructions	45
loop length	180
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	9.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00
cycles	2.00	2.00	9.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	5.25
Overall L1	9.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.00 cycles. At this rate:

1% of peak load performance is reached (1.78 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 420240

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADD X1, X1, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W10, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X2, X2, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X3, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X5, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X6, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X7, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X20, X20, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X21, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X22, X22, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X23, X23, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.LE 420378 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1c58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X25, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W24, WZR, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X17, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 420318 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1bf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X12, X17, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
ORR X19, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X28, X0, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADDVL X29, X3, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADDVL X30, X5, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADDVL X14, X21, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X26, X12, X16, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADDVL X12, X7, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X27, X17, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X25, X26, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W24, W9, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
CBZ X27, 420240 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1b20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X12, X25, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W24, W24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X19, X13, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X25, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X12, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X14, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X25, X15, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X26, X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X28, X14, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 420240 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1b20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	advec_mom_kernel
Source file and lines	advec_mom_kernel.f90-pp.f90:247-250
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_mom_kernel.f90-pp.f90:247-250.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 16 bytes.

General properties

nb instructions	45
loop length	180
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	9.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00
cycles	2.00	2.00	9.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	0.67	0.67	0.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	5.25
Overall L1	9.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.00 cycles. At this rate:

1% of peak load performance is reached (1.78 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 420240

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
ADD X1, X1, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUBS W10, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X2, X2, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X3, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X5, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X6, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X7, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X20, X20, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X21, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X22, X22, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X23, X23, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.LE 420378 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1c58>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ORR X25, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR W24, WZR, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X17, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 420318 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1bf8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
UDIV X12, X17, X16	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
ORR X19, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADDVL X28, X0, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADDVL X29, X3, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADDVL X30, X5, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADDVL X14, X21, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
MADD X26, X12, X16, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADDVL X12, X7, #1	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X27, X17, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X25, X26, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W24, W9, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
CBZ X27, 420240 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1b20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X12, X25, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W24, W24, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X19, X13, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X25, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X12, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X14, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X14, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X25, X15, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X26, X13, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X28, X14, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 420240 <__nv_advec_mom_kernel_mod_advec_mom_kernel__F1L79_1_+0x1b20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code