OV - exec - Loop 535

	Loop Id: 535	Module: exec	Source: advec_cell_kernel.f90-pp.f90:90-91	Coverage: 1.35%

0x41b8a0 ADD	X0, X5, X26,LSL #3

0x41b8a4 LD1D	{Z0.D}, P0/Z, [X2, X26,LSL #3]    [4]

0x41b8a8 LD1D	{Z1.D}, P0/Z, [X0, X25,LSL #3]    [2]

0x41b8ac LD1D	{Z2.D}, P0/Z, [X0, MUL VL]    [7]

0x41b8b0 FSUB	Z1.D, Z1.D, Z2.D

0x41b8b4 LD1D	{Z2.D}, P0/Z, [X7, X26,LSL #3]    [5]

0x41b8b8 FADD	Z0.D, Z0.D, Z1.D

0x41b8bc FSUB	Z0.D, Z0.D, Z2.D

0x41b8c0 LD1D	{Z2.D}, P0/Z, [X6, X26,LSL #3]    [6]

0x41b8c4 FADD	Z0.D, Z0.D, Z2.D

0x41b8c8 ST1D	{Z0.D}, P0, [X4, X26,LSL #3]    [3]

0x41b8cc FSUB	Z0.D, Z0.D, Z1.D

0x41b8d0 ST1D	{Z0.D}, P0, [X3, X26,LSL #3]    [1]

0x41b8d4 ADD	X26, X26, X11

0x41b8d8 CMP	X27, X26

0x41b8dc B.NE	41b8a0

/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_cell_kernel.f90-pp.f90: 90 - 91

--------------------------------------------------------------------------------

90:           DO j=x_min-2,x_max+2

91:             pre_vol(j,k)=volume(j,k)+(vol_flux_x(j+1,k  )-vol_flux_x(j,k)+vol_flux_y(j  ,k+1)-vol_flux_y(j,k))

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.40
Bottlenecks	P10, P11,
Function	__nv_advec_cell_kernel_module_advec_cell_kernel__F1L81_1_
Source	advec_cell_kernel.f90-pp.f90:90-91
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	3.50
CQA cycles if no scalar integer	3.50
CQA cycles if FP arith vectorized	3.50
CQA cycles if fully vectorized	3.50
Front-end cycles	2.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	2.50
P6 cycles	2.50
P7 cycles	2.50
P8 cycles	2.50
P9 cycles	3.50
P10 cycles	3.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	16.00
Nb uops	16.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	5.71
Nb FLOP add-sub	20.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.40
Bottlenecks	P10, P11,
Function	__nv_advec_cell_kernel_module_advec_cell_kernel__F1L81_1_
Source	advec_cell_kernel.f90-pp.f90:90-91
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	3.50
CQA cycles if no scalar integer	3.50
CQA cycles if FP arith vectorized	3.50
CQA cycles if fully vectorized	3.50
Front-end cycles	2.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.75
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.75
P5 cycles	2.50
P6 cycles	2.50
P7 cycles	2.50
P8 cycles	2.50
P9 cycles	3.50
P10 cycles	3.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	16.00
Nb uops	16.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	5.71
Nb FLOP add-sub	20.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	64.00
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__nv_advec_cell_kernel_module_advec_cell_kernel__F1L81_1_
Source file and lines	advec_cell_kernel.f90-pp.f90:90-91
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/advec_cell_kernel.f90-pp.f90:90-91.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 20 FP arithmetical operations:

20: addition or subtraction

The binary loop is loading 160 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

General properties

nb instructions	16
loop length	64
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	0.75	0.75	2.50	2.50	1.00	1.00	3.50	3.50	0.00	0.00	0.00
cycles	0.50	0.50	0.75	0.75	0.75	0.75	2.50	2.50	2.50	2.50	3.50	3.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.00
Data deps.	1.00
Overall L1	3.50

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.50 cycles. At this rate:

47% of peak load performance is reached (45.71 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
38% of peak store performance is reached (18.29 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41b8a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
ADD X0, X5, X26,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LD1D {Z0.D}, P0/Z, [X2, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z1.D}, P0/Z, [X0, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z2.D}, P0/Z, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z1.D, Z1.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z2.D}, P0/Z, [X7, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z0.D, Z0.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z2.D}, P0/Z, [X6, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z0.D, Z0.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z0.D}, P0, [X4, X26,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
FSUB Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z0.D}, P0, [X3, X26,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X26, X26, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X27, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
B.NE 41b8a0 <__nv_advec_cell_kernel_module_advec_cell_kernel__F1L81_1_+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	__nv_advec_cell_kernel_module_advec_cell_kernel__F1L81_1_
Source file and lines	advec_cell_kernel.f90-pp.f90:90-91
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 20 FP arithmetical operations:

20: addition or subtraction

The binary loop is loading 160 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.09 FP operations per loaded or stored byte.

General properties

nb instructions	16
loop length	64
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.75	0.75	0.75	0.75	2.50	2.50	1.00	1.00	3.50	3.50	0.00	0.00	0.00
cycles	0.50	0.50	0.75	0.75	0.75	0.75	2.50	2.50	2.50	2.50	3.50	3.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.00
Data deps.	1.00
Overall L1	3.50

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.50 cycles. At this rate:

47% of peak load performance is reached (45.71 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
38% of peak store performance is reached (18.29 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41b8a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
ADD X0, X5, X26,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LD1D {Z0.D}, P0/Z, [X2, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z1.D}, P0/Z, [X0, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z2.D}, P0/Z, [X0, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FSUB Z1.D, Z1.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z2.D}, P0/Z, [X7, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FSUB Z0.D, Z0.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z2.D}, P0/Z, [X6, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z0.D, Z0.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z0.D}, P0, [X4, X26,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
FSUB Z0.D, Z0.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
ST1D {Z0.D}, P0, [X3, X26,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X26, X26, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X27, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
B.NE 41b8a0 <__nv_advec_cell_kernel_module_advec_cell_kernel__F1L81_1_+0x1e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code