OV - exec - Loop 527

0x430640 CNTD	X18, ALL

0x430644 SUB	W13, W18, #1

0x430648 CMP	W30, W13

0x43064c B.CC	439ef8

0x430650 CNTB	X0, ALL

0x430654 ADD	X12, X25, X8

0x430658 SUB	X10, XZR, X0

0x43065c ADD	X1, X11, X8

0x430660 ADD	X17, X10, #8

0x430664 ADD	X13, X9, X1,LSL #3

0x430668 MOVZ	W14, #0

0x43066c ADD	X16, X17, X12,LSL #3

0x430670 ADD	X18, X9, X16

0x430674 HINT	#0

0x430678 HINT	#0

0x43067c HINT	#0

  (529) 0x430680 LD1D	{Z22.D}, P7/Z, [X18, MUL VL]

  (529) 0x430684 ORR	W15, WZR, W14

  (529) 0x430688 REV	Z23.D, Z22.D

  (529) 0x43068c ADD	W14, W14, W3

  (529) 0x430690 ST1D	{Z23.D}, P7, [X13, MUL VL]

  (529) 0x430694 ADD	X18, X18, X4

  (529) 0x430698 ADD	X13, X13, X5

  (529) 0x43069c CMP	W6, W14

  (529) 0x4306a0 B.CS	430680

0x4306a4 CNTD	X2, ALL

0x4306a8 ADD	W1, W2, #1

0x4306ac ADD	W2, W15, W1

0x4306b0 CMP	W24, W14

0x4306b4 B.EQ	4307f0

0x4306b8 SBFM	X10, X2, #0, #31

0x4306bc ADD	X1, X9, X12,LSL #3

0x4306c0 SUB	X0, X8, X10

0x4306c4 SUB	W12, W24, W10

0x4306c8 ADD	X17, X0, X11

0x4306cc ADD	X0, X10, #1

0x4306d0 ADD	X15, X9, X17,LSL #3

0x4306d4 AND	W16, W12, #128

0x4306d8 LDR	D24, [X9, X17,LSL #3]

0x4306dc SUB	X2, X15, #8

0x4306e0 STR	D24, [X1, X10,LSL #3]

0x4306e4 CMP	W24, W0

0x4306e8 B.LT	4307f0

0x4306ec CBZ	W16, 430780

  (528) 0x430780 ORR	X10, XZR, X2

  (528) 0x430784 ADD	X12, X0, #1

  (528) 0x430788 ADD	X18, X0, #2

  (528) 0x43078c ADD	X17, X0, #3

  (528) 0x430790 LDR	D1, [X10], #504

  (528) 0x430794 ADD	X16, X0, #4

  (528) 0x430798 ADD	X15, X0, #5

  (528) 0x43079c ADD	X14, X0, #6

  (528) 0x4307a0 ADD	X13, X0, #7

  (528) 0x4307a4 SUB	X2, X2, #64

  (528) 0x4307a8 STR	D1, [X1, X0,LSL #3]

  (528) 0x4307ac ADD	X0, X0, #8

  (528) 0x4307b0 LDR	D2, [X2, #56]

  (528) 0x4307b4 STR	D2, [X1, X12,LSL #3]

  (528) 0x4307b8 LDUR	D3, [X10, #504]

  (528) 0x4307bc STR	D3, [X1, X18,LSL #3]

  (528) 0x4307c0 LDR	D4, [X2, #40]

  (528) 0x4307c4 STR	D4, [X1, X17,LSL #3]

  (528) 0x4307c8 LDR	D5, [X2, #32]

  (528) 0x4307cc STR	D5, [X1, X16,LSL #3]

  (528) 0x4307d0 LDR	D6, [X2, #24]

  (528) 0x4307d4 STR	D6, [X1, X15,LSL #3]

  (528) 0x4307d8 LDR	D7, [X2, #16]

  (528) 0x4307dc STR	D7, [X1, X14,LSL #3]

  (528) 0x4307e0 LDR	D16, [X2, #8]

  (528) 0x4307e4 STR	D16, [X1, X13,LSL #3]

  (528) 0x4307e8 CMP	W24, W0

  (528) 0x4307ec B.GE	430780

0x4307f0 ADD	W7, W7, #1

0x4307f4 ADD	X8, X8, X23

0x4307f8 CMP	W26, W7

0x4307fc B.GT	430640

0x439ef8 MOVZ	W2, #1

0x439efc ADD	X12, X25, X8

0x439f00 B	4306b8

/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90: 260 - 264

--------------------------------------------------------------------------------

260:         !$OMP DO

261:         DO k=y_min-depth,y_max+depth

262:         !$OMP SIMD

263:           DO j=1,depth

264:             energy1(x_max+j,k)=energy1(x_max+1-j,k)

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	update_halo_kernel	update_halo_kernel.f90:754	exec
○	update_halo	update_halo.f90:78	exec
○	advection	advection.f90:103	exec
○	hydro	hydro.f90:64	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec

Path /

Metric	Value
CQA speedup if no scalar integer	9.30
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.05
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.59
Bottlenecks	P2, P3, P4, P5,
Function	update_halo_kernel._omp_fn.0
Source	update_halo_kernel.f90:260-260,update_halo_kernel.f90:264-264
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.75
CQA cycles if no scalar integer	0.83
CQA cycles if FP arith vectorized	7.75
CQA cycles if fully vectorized	1.28
Front-end cycles	4.88
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	7.75
P2 cycles	7.75
P3 cycles	7.75
P4 cycles	7.75
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.83
P10 cycles	0.50
P11 cycles	0.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	39.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.06
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	19.32
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	21.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.25

Metric	Value
CQA speedup if no scalar integer	9.30
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.05
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.59
Bottlenecks	P2, P3, P4, P5,
Function	update_halo_kernel._omp_fn.0
Source	update_halo_kernel.f90:260-260,update_halo_kernel.f90:264-264
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.75
CQA cycles if no scalar integer	0.83
CQA cycles if FP arith vectorized	7.75
CQA cycles if fully vectorized	1.28
Front-end cycles	4.88
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	7.75
P2 cycles	7.75
P3 cycles	7.75
P4 cycles	7.75
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.83
P10 cycles	0.50
P11 cycles	0.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	42.00
Nb uops	39.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.06
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	19.32
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	21.25
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	update_halo_kernel._omp_fn.0
Source file and lines	update_halo_kernel.f90:260-264
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90:260-264.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90:260,264.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.75 to 0.83 cycles (9.30x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 19% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 7.75 to 1.28 cycles (6.05x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	42
loop length	168
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	7.75	7.75	7.75	7.75	0.50	0.50	0.00	0.00	0.83	0.50	0.67	0.00	0.00
cycles	3.00	3.00	7.75	7.75	7.75	7.75	0.50	0.50	0.00	0.00	0.83	0.50	0.67	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.88
Overall L1	7.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.75 cycles. At this rate:

1% of peak load performance is reached (1.03 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.03 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 430640

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
CNTD X18, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB W13, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W30, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 439ef8 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0xa6f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CNTB X0, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X12, X25, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X9, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X17, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X9, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
CNTD X2, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W1, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W2, W15, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W24, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4307f0 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0xff0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X10, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X9, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X0, X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W24, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X0, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X9, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W16, W12, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D24, [X9, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
SUB X2, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D24, [X1, X10,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP W24, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4307f0 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0xff0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W16, 430780 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0xf80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W7, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W26, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 430640 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X25, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4306b8 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0xeb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	update_halo_kernel._omp_fn.0
Source file and lines	update_halo_kernel.f90:260-264
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90:260-264.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90:260,264.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.75 to 0.83 cycles (9.30x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 19% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 7.75 to 1.28 cycles (6.05x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	42
loop length	168
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	7.75	7.75	7.75	7.75	0.50	0.50	0.00	0.00	0.83	0.50	0.67	0.00	0.00
cycles	3.00	3.00	7.75	7.75	7.75	7.75	0.50	0.50	0.00	0.00	0.83	0.50	0.67	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.88
Overall L1	7.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.75 cycles. At this rate:

1% of peak load performance is reached (1.03 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.03 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 430640

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
CNTD X18, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB W13, W18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W30, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 439ef8 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0xa6f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CNTB X0, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X12, X25, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X10, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X11, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X10, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X9, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W14, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X17, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X9, X16	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
CNTD X2, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD W1, W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD W2, W15, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W24, W14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 4307f0 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0xff0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X10, X2, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X9, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X0, X8, X10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W12, W24, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X0, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X9, X17,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W16, W12, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D24, [X9, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
SUB X2, X15, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D24, [X1, X10,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP W24, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 4307f0 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0xff0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W16, 430780 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0xf80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W7, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W26, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 430640 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0xe40>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W2, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X25, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4306b8 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0xeb8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code