OV - exec - Loop 514

	Loop Id: 514	Module: exec	Source: accelerate_kernel.f90-pp.f90:60-78 [...]	Coverage: 0.01%

0x41ab48 LDR	X9, [SP, #128]

0x41ab4c SUBS	W3, W3, #1

0x41ab50 ADD	X0, X0, X9

0x41ab54 ADD	X19, X19, X9

0x41ab58 ADD	X4, X4, X9

0x41ab5c ADD	X13, X13, X9

0x41ab60 ADD	X15, X15, X9

0x41ab64 ADD	X5, X5, X9

0x41ab68 ADD	X23, X23, X9

0x41ab6c ADD	X24, X24, X9

0x41ab70 ADD	X25, X25, X9

0x41ab74 LDR	X9, [SP, #120]

0x41ab78 ADD	X26, X26, X9

0x41ab7c ADD	X27, X27, X9

0x41ab80 ADD	X28, X28, X9

0x41ab84 ADD	X29, X29, X9

0x41ab88 ADD	X30, X30, X9

0x41ab8c ADD	X20, X20, X9

0x41ab90 LDR	X9, [SP, #136]

0x41ab94 ADD	X21, X21, X9

0x41ab98 ADD	X22, X22, X9

0x41ab9c LDR	X9, [SP, #144]

0x41aba0 ADD	X18, X18, X9

0x41aba4 ADD	X1, X1, X9

0x41aba8 B.LE	41ae7c

0x41abac LDR	X9, [SP, #152]

0x41abb0 ORR	X6, XZR, X2

0x41abb4 CMP	X9, X7

0x41abb8 LDR	W9, [SP, #164]

0x41abbc B.CC	41ace8

0x41abc0 LDR	X10, [SP, #152]

0x41abc4 ORR	X11, XZR, XZR

0x41abc8 UDIV	X9, X10, X7

0x41abcc MADD	X12, X9, X7, XZR

0x41abd0 LDR	W9, [SP, #164]

0x41abd4 SUB	X10, X10, X12

0x41abd8 ADD	X6, X12, X2

0x41abdc SUB	W9, W9, W12

  (515) 0x41abe0 UBFM	X14, X11, #61, #60

  (515) 0x41abe4 ADD	X16, X15, X14

  (515) 0x41abe8 ADD	X17, X13, X14

  (515) 0x41abec LD1D	{Z4.D}, P0/Z, [X16, X8,LSL #3]

  (515) 0x41abf0 LD1D	{Z5.D}, P0/Z, [X17, X8,LSL #3]

  (515) 0x41abf4 LD1D	{Z6.D}, P0/Z, [X16, MUL VL]

  (515) 0x41abf8 LD1D	{Z7.D}, P0/Z, [X17, MUL VL]

  (515) 0x41abfc ADD	X16, X25, X14

  (515) 0x41ac00 ADD	X17, X24, X14

  (515) 0x41ac04 FMUL	Z6.D, Z6.D, Z7.D

  (515) 0x41ac08 FMAD	Z4.D, P0/M, Z5.D, Z6.D

  (515) 0x41ac0c LD1D	{Z5.D}, P0/Z, [X16, MUL VL]

  (515) 0x41ac10 LD1D	{Z6.D}, P0/Z, [X17, MUL VL]

  (515) 0x41ac14 LD1D	{Z7.D}, P0/Z, [X16, X8,LSL #3]

  (515) 0x41ac18 LD1D	{Z16.D}, P0/Z, [X17, X8,LSL #3]

  (515) 0x41ac1c ADD	X16, X23, X14

  (515) 0x41ac20 FMUL	Z7.D, Z7.D, Z16.D

  (515) 0x41ac24 FMAD	Z5.D, P0/M, Z6.D, Z7.D

  (515) 0x41ac28 FADD	Z4.D, Z4.D, Z5.D

  (515) 0x41ac2c LD1D	{Z5.D}, P0/Z, [X30, X11,LSL #3]

  (515) 0x41ac30 LD1D	{Z6.D}, P0/Z, [X16, MUL VL]

  (515) 0x41ac34 LD1D	{Z7.D}, P0/Z, [X16, X8,LSL #3]

  (515) 0x41ac38 ADD	X16, X4, X14

  (515) 0x41ac3c LD1D	{Z17.D}, P0/Z, [X20, X11,LSL #3]

  (515) 0x41ac40 FMUL	Z4.D, Z4.D, Z3.D

  (515) 0x41ac44 LD1D	{Z18.D}, P0/Z, [X16, MUL VL]

  (515) 0x41ac48 LD1D	{Z19.D}, P0/Z, [X16, X8,LSL #3]

  (515) 0x41ac4c LD1D	{Z21.D}, P0/Z, [X29, X11,LSL #3]

  (515) 0x41ac50 ADD	X16, X19, X14

  (515) 0x41ac54 FDIVR	Z4.D, P0/M, Z4.D, Z1.D

  (515) 0x41ac58 FSUB	Z16.D, Z6.D, Z7.D

  (515) 0x41ac5c FSUB	Z6.D, Z18.D, Z6.D

  (515) 0x41ac60 FSUB	Z20.D, Z18.D, Z19.D

  (515) 0x41ac64 FSUB	Z7.D, Z19.D, Z7.D

  (515) 0x41ac68 LD1D	{Z19.D}, P0/Z, [X16, X8,LSL #3]

  (515) 0x41ac6c FMUL	Z20.D, Z20.D, Z21.D

  (515) 0x41ac70 FMAD	Z16.D, P0/M, Z17.D, Z20.D

  (515) 0x41ac74 FMLS	Z5.D, P0/M, Z4.D, Z16.D

  (515) 0x41ac78 LD1D	{Z16.D}, P0/Z, [X27, X11,LSL #3]

  (515) 0x41ac7c LD1D	{Z18.D}, P0/Z, [X16, MUL VL]

  (515) 0x41ac80 ADD	X16, X5, X14

  (515) 0x41ac84 ADD	X14, X0, X14

  (515) 0x41ac88 FMUL	Z6.D, Z6.D, Z18.D

  (515) 0x41ac8c FMLA	Z6.D, P0/M, Z7.D, Z19.D

  (515) 0x41ac90 LD1D	{Z7.D}, P0/Z, [X16, MUL VL]

  (515) 0x41ac94 LD1D	{Z20.D}, P0/Z, [X16, X8,LSL #3]

  (515) 0x41ac98 LD1D	{Z22.D}, P0/Z, [X14, MUL VL]

  (515) 0x41ac9c LD1D	{Z23.D}, P0/Z, [X14, X8,LSL #3]

  (515) 0x41aca0 FSUB	Z24.D, Z22.D, Z23.D

  (515) 0x41aca4 FMUL	Z21.D, Z21.D, Z24.D

  (515) 0x41aca8 FSUB	Z24.D, Z7.D, Z20.D

  (515) 0x41acac FSUB	Z7.D, Z22.D, Z7.D

  (515) 0x41acb0 FMUL	Z7.D, Z18.D, Z7.D

  (515) 0x41acb4 FMAD	Z17.D, P0/M, Z24.D, Z21.D

  (515) 0x41acb8 FMLS	Z5.D, P0/M, Z4.D, Z17.D

  (515) 0x41acbc ST1D	{Z5.D}, P0, [X28, X11,LSL #3]

  (515) 0x41acc0 MOVPRFX	Z5, Z16

  (515) 0x41acc4 FMLS	Z5.D, P0/M, Z4.D, Z6.D

  (515) 0x41acc8 FSUB	Z6.D, Z23.D, Z20.D

  (515) 0x41accc FMAD	Z6.D, P0/M, Z19.D, Z7.D

  (515) 0x41acd0 FMSB	Z4.D, P0/M, Z6.D, Z5.D

  (515) 0x41acd4 ST1D	{Z4.D}, P0, [X26, X11,LSL #3]

  (515) 0x41acd8 ADD	X11, X11, X7

  (515) 0x41acdc CMP	X12, X11

  (515) 0x41ace0 B.NE	41abe0

0x41ace4 CBZ	X10, 41ab48

0x41ace8 LDR	X14, [SP, #88]

0x41acec STP	X5, X4, [SP, #168]

0x41acf0 ADD	W4, W9, #1

0x41acf4 ADD	X9, X6, X21

0x41acf8 STP	X0, X20, [SP, #184]

0x41acfc ADD	X10, X6, X22

0x41ad00 ADD	X11, X6, X18

0x41ad04 ORR	X20, XZR, X6

0x41ad08 STP	X1, X18, [SP, #200]

0x41ad0c STP	X22, X21, [SP, #216]

0x41ad10 LDP	X0, X21, [SP, #56]

0x41ad14 UBFM	X2, X10, #61, #60

0x41ad18 ADD	X1, X6, X1

0x41ad1c UBFM	X18, X11, #61, #60

0x41ad20 LDP	X17, X7, [SP, #24]

0x41ad24 ADD	X6, X14, X9,LSL #3

0x41ad28 LDR	X9, [SP, #104]

0x41ad2c ADD	X11, X14, X2

0x41ad30 UBFM	X20, X1, #61, #60

0x41ad34 LDP	X5, X1, [SP, #72]

0x41ad38 ADD	X16, X21, X18

0x41ad3c STR	W3, [SP, #236]

0x41ad40 ORR	X3, XZR, XZR

0x41ad44 ADD	X17, X17, X18

0x41ad48 ADD	X0, X0, X2

0x41ad4c ADD	X5, X5, X2

0x41ad50 ADD	X12, X9, X2

0x41ad54 LDR	X9, [SP, #96]

0x41ad58 ADD	X1, X1, X20

0x41ad5c ADD	X14, X9, X2

0x41ad60 LDP	X9, X22, [SP, #40]

0x41ad64 ADD	X2, X7, X20

0x41ad68 ADD	X10, X22, X18

0x41ad6c ADD	X9, X9, X18

0x41ad70 ADD	X18, X7, X18

0x41ad74 ADD	X7, X22, X20

0x41ad78 ADD	X20, X21, X20

0x41ad7c HINT	#0

  (513) 0x41ad80 ADD	X21, X18, X3

  (513) 0x41ad84 ADD	X22, X17, X3

  (513) 0x41ad88 SUB	W4, W4, #1

  (513) 0x41ad8c CMP	W4, #1

  (513) 0x41ad90 LDP	D4, D5, [X21]

  (513) 0x41ad94 ADD	X21, X2, X3

  (513) 0x41ad98 LDP	D6, D7, [X22]

  (513) 0x41ad9c ADD	X22, X1, X3

  (513) 0x41ada0 LDP	D17, D16, [X21]

  (513) 0x41ada4 LDP	D18, D19, [X22, #1016]

  (513) 0x41ada8 ADD	X21, X20, X3

  (513) 0x41adac ADD	X22, X16, X3

  (513) 0x41adb0 FMUL	D5, D5, D7

  (513) 0x41adb4 FMADD	D4, D4, D6, D5

  (513) 0x41adb8 FMUL	D7, D17, D18

  (513) 0x41adbc LDR	D17, [X11, X3]

  (513) 0x41adc0 FMADD	D5, D16, D19, D7

  (513) 0x41adc4 LDP	D7, D6, [X22, #1016]

  (513) 0x41adc8 LDR	D16, [X6, X3]

  (513) 0x41adcc ADD	X22, X9, X3

  (513) 0x41add0 FADD	D4, D4, D5

  (513) 0x41add4 LDP	D18, D5, [X21, #1016]

  (513) 0x41add8 ADD	X21, X7, X3

  (513) 0x41addc FMUL	D4, D4, D2

  (513) 0x41ade0 LDP	D20, D19, [X21, #1016]

  (513) 0x41ade4 ADD	X21, X10, X3

  (513) 0x41ade8 FSUB	D23, D6, S7

  (513) 0x41adec LDP	D22, D21, [X21, #1016]

  (513) 0x41adf0 FMUL	D23, D23, D17

  (513) 0x41adf4 FDIV	D4, D0, D4

  (513) 0x41adf8 FSUB	D7, D7, S18

  (513) 0x41adfc FSUB	D24, D21, S22

  (513) 0x41ae00 FMUL	D17, D17, D24

  (513) 0x41ae04 FSUB	D24, D5, S18

  (513) 0x41ae08 FSUB	D5, D6, S5

  (513) 0x41ae0c LDR	D6, [X12, X3]

  (513) 0x41ae10 LDR	D18, [X5, X3]

  (513) 0x41ae14 FMADD	D23, D24, D16, D23

  (513) 0x41ae18 FSUB	D24, D19, S20

  (513) 0x41ae1c FMADD	D16, D16, D24, D17

  (513) 0x41ae20 LDP	D17, D24, [X22]

  (513) 0x41ae24 FMSUB	D6, D4, D23, D6

  (513) 0x41ae28 FMUL	D5, D5, D24

  (513) 0x41ae2c FMADD	D5, D7, D17, D5

  (513) 0x41ae30 FSUB	D7, D21, S19

  (513) 0x41ae34 FMSUB	D6, D4, D16, D6

  (513) 0x41ae38 FMUL	D7, D24, D7

  (513) 0x41ae3c FMSUB	D5, D4, D5, D18

  (513) 0x41ae40 STR	D6, [X14, X3]

  (513) 0x41ae44 FSUB	D6, D22, S20

  (513) 0x41ae48 FMADD	D6, D17, D6, D7

  (513) 0x41ae4c FMSUB	D4, D4, D6, D5

  (513) 0x41ae50 STR	D4, [X0, X3]

  (513) 0x41ae54 ADD	X3, X3, #8

  (513) 0x41ae58 B.HI	41ad80

0x41ae5c LDR	X2, [SP, #112]

0x41ae60 LDR	W3, [SP, #236]

0x41ae64 LDP	X22, X21, [SP, #216]

0x41ae68 CNTD	X7, ALL

0x41ae6c LDP	X1, X18, [SP, #200]

0x41ae70 LDP	X0, X20, [SP, #184]

0x41ae74 LDP	X5, X4, [SP, #168]

0x41ae78 B	41ab48

/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/accelerate_kernel.f90-pp.f90: 60 - 78

--------------------------------------------------------------------------------

60:     !$OMP DO PRIVATE(j,k,stepbymass_s)

61:     DO k=y_min,y_max+1

62:     !$OMP SIMD

63:       DO j=x_min,x_max+1

[...]

69: # 69 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/accelerate_kernel.f90"

70:         xvel1(j,k)=xvel0(j,k)-stepbymass_s*(xarea(j  ,k  )*(pressure(j  ,k  )-pressure(j-1,k  ))    &

71:           +xarea(j  ,k-1)*(pressure(j  ,k-1)-pressure(j-1,k-1)))

72:         yvel1(j,k)=yvel0(j,k)-stepbymass_s*(yarea(j  ,k  )*(pressure(j  ,k  )-pressure(j  ,k-1))    &

73:           +yarea(j-1,k  )*(pressure(j-1,k  )-pressure(j-1,k-1)))

74:         xvel1(j,k)=xvel1(j,k)-stepbymass_s*(xarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j-1,k  )) &

75:           +xarea(j  ,k-1)*(viscosity(j  ,k-1)-viscosity(j-1,k-1)))

76:         yvel1(j,k)=yvel1(j,k)-stepbymass_s*(yarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j  ,k-1)) &

77:           +yarea(j-1,k  )*(viscosity(j-1,k  )-viscosity(j-1,k-1)))

78:       ENDDO

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.37
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.33
Bottlenecks
Function	__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_
Source	accelerate_kernel.f90-pp.f90:60-62,accelerate_kernel.f90-pp.f90:77-78
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.50
CQA cycles if no scalar integer	9.50
CQA cycles if FP arith vectorized	9.50
CQA cycles if fully vectorized	2.17
Front-end cycles	7.13
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	9.50
P2 cycles	9.50
P3 cycles	9.50
P4 cycles	9.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	5.42
P10 cycles	5.25
P11 cycles	5.33
P12 cycles	1.25
P13 cycles	1.25
P14 cycles	0.50 - 0.25
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	57.50
Nb uops	57.00
Nb loads	NA
Nb stores	2.50
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	15.50
Bytes prefetched	0.00
Bytes loaded	132.00
Bytes stored	34.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.45
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	24.38
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.31
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.44
Bottlenecks	P2, P3, P4, P5,
Function	__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_
Source	accelerate_kernel.f90-pp.f90:60-62,accelerate_kernel.f90-pp.f90:77-78
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.00
CQA cycles if no scalar integer	7.00
CQA cycles if FP arith vectorized	7.00
CQA cycles if fully vectorized	1.63
Front-end cycles	4.88
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	7.00
P2 cycles	7.00
P3 cycles	7.00
P4 cycles	7.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	2.67
P10 cycles	2.67
P11 cycles	2.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	39.00
Nb uops	39.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.00
Bytes prefetched	0.00
Bytes loaded	56.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.50
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	24.43
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.41
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.28
Bottlenecks	P2, P3, P4, P5,
Function	__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_
Source	accelerate_kernel.f90-pp.f90:60-62,accelerate_kernel.f90-pp.f90:77-78
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	2.72
Front-end cycles	9.38
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	12.00
P2 cycles	12.00
P3 cycles	12.00
P4 cycles	12.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	8.17
P10 cycles	7.83
P11 cycles	8.00
P12 cycles	2.50
P13 cycles	2.50
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	76.00
Nb uops	75.00
Nb loads	NA
Nb stores	5.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.00
Bytes prefetched	0.00
Bytes loaded	208.00
Bytes stored	68.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.39
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	24.32
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_
Source file and lines	accelerate_kernel.f90-pp.f90:60-78
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/accelerate_kernel.f90-pp.f90:60-63,69-78.

Analyzed code is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/accelerate_kernel.f90-pp.f90:60-62,77-78.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 9.50 to 2.17 cycles (4.37x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 132 bytes. The binary loop is storing 34 bytes.

General properties

nb instructions	57.50
loop length	230
nb stack references	0

Front-end

front end

7.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	9.50	9.50	9.50	9.50	0.00	0.00	0.00	0.00	5.42	5.25	5.33	1.25	1.25
cycles	1.50	1.50	9.50	9.50	9.50	9.50	0.00	0.00	0.00	0.00	5.42	5.25	5.33	1.25	1.25

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	0.50-0.25
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.13
Data deps.	1.00
Overall L1	9.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.50 cycles. At this rate:

13% of peak load performance is reached (12.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (2.83 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Function	__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_
Source file and lines	accelerate_kernel.f90-pp.f90:60-78
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 56 bytes.

General properties

nb instructions	39
loop length	156
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	2.67	2.67	2.67	0.00	0.00
cycles	1.50	1.50	7.00	7.00	7.00	7.00	0.00	0.00	0.00	0.00	2.67	2.67	2.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.88
Data deps.	1.00
Overall L1	7.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41abac

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	Latency	Recip. throughput
LDR X9, [SP, #128]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUBS W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
ADD X0, X0, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X19, X19, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X4, X4, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X13, X13, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X15, X15, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X5, X5, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X23, X23, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X24, X24, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X25, X25, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X26, X26, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X27, X27, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X28, X28, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X29, X29, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X30, X30, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X20, X20, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X9, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X21, X21, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X22, X22, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
LDR X9, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ADD X18, X18, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X1, X1, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
B.LE 41ae7c <__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_+0x52c>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X9, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR X6, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CMP X9, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.33
LDR W9, [SP, #164]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
B.CC 41ace8 <__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_+0x398>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LDR X10, [SP, #152]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
ORR X11, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
UDIV X9, X10, X7	1	0	0	0	0	1	0	0	0	0	5-20	1-0.50
MADD X12, X9, X7, XZR	1	0	0	0	0	1	0	0	0	0	2	1
LDR W9, [SP, #164]	1	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
SUB X10, X10, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
ADD X6, X12, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
SUB W9, W9, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.25
CBZ X10, 41ab48 <__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	1	0.50

Function	__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_
Source file and lines	accelerate_kernel.f90-pp.f90:60-78
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 208 bytes. The binary loop is storing 68 bytes.

General properties

nb instructions	76
loop length	304
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	12.00	12.00	12.00	12.00	0.00	0.00	0.00	0.00	8.17	7.83	8.00	2.50	2.50
cycles	1.50	1.50	12.00	12.00	12.00	12.00	0.00	0.00	0.00	0.00	8.17	7.83	8.00	2.50	2.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	9.38
Data deps.	1.00
Overall L1	12.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

18% of peak load performance is reached (17.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (5.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41abac

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR X9, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUBS W3, W3, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X0, X0, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X19, X19, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X13, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X15, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X5, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X23, X23, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X24, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X25, X25, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X26, X26, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X27, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X28, X28, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X29, X29, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X30, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X20, X20, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X21, X21, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X22, X22, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X18, X18, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.LE 41ae7c <__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_+0x52c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X6, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP X9, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR W9, [SP, #164]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B.CC 41ace8 <__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_+0x398>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X14, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STP X5, X4, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD W4, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X6, X21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X0, X20, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X10, X6, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X6, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X20, XZR, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X1, X18, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X22, X21, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDP X0, X21, [SP, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
UBFM X2, X10, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X18, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X17, X7, [SP, #24]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X6, X14, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [SP, #104]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X14, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X20, X1, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X5, X1, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X16, X21, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W3, [SP, #236]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X3, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X17, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X5, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X9, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X1, X1, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X14, X9, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X9, X22, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X2, X7, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X22, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X7, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X22, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X20, X21, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
LDR X2, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W3, [SP, #236]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X22, X21, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CNTD X7, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDP X1, X18, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X0, X20, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X5, X4, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 41ab48 <__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_+0x1f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code