OV - exec - Loop 513

	Loop Id: 513	Module: exec	Source: accelerate_kernel.f90-pp.f90:63-77 [...]	Coverage: 0.02%

0x41ad80 ADD	X21, X18, X3

0x41ad84 ADD	X22, X17, X3

0x41ad88 SUB	W4, W4, #1

0x41ad8c CMP	W4, #1

0x41ad90 LDP	D4, D5, [X21]    [15]

0x41ad94 ADD	X21, X2, X3

0x41ad98 LDP	D6, D7, [X22]    [10]

0x41ad9c ADD	X22, X1, X3

0x41ada0 LDP	D17, D16, [X21]    [13]

0x41ada4 LDP	D18, D19, [X22, #1016]    [2]

0x41ada8 ADD	X21, X20, X3

0x41adac ADD	X22, X16, X3

0x41adb0 FMUL	D5, D5, D7

0x41adb4 FMADD	D4, D4, D6, D5

0x41adb8 FMUL	D7, D17, D18

0x41adbc LDR	D17, [X11, X3]    [3]

0x41adc0 FMADD	D5, D16, D19, D7

0x41adc4 LDP	D7, D6, [X22, #1016]    [14]

0x41adc8 LDR	D16, [X6, X3]    [6]

0x41adcc ADD	X22, X9, X3

0x41add0 FADD	D4, D4, D5

0x41add4 LDP	D18, D5, [X21, #1016]    [7]

0x41add8 ADD	X21, X7, X3

0x41addc FMUL	D4, D4, D2

0x41ade0 LDP	D20, D19, [X21, #1016]    [5]

0x41ade4 ADD	X21, X10, X3

0x41ade8 FSUB	D23, D6, S7

0x41adec LDP	D22, D21, [X21, #1016]    [12]

0x41adf0 FMUL	D23, D23, D17

0x41adf4 FDIV	D4, D0, D4

0x41adf8 FSUB	D7, D7, S18

0x41adfc FSUB	D24, D21, S22

0x41ae00 FMUL	D17, D17, D24

0x41ae04 FSUB	D24, D5, S18

0x41ae08 FSUB	D5, D6, S5

0x41ae0c LDR	D6, [X12, X3]    [11]

0x41ae10 LDR	D18, [X5, X3]    [9]

0x41ae14 FMADD	D23, D24, D16, D23

0x41ae18 FSUB	D24, D19, S20

0x41ae1c FMADD	D16, D16, D24, D17

0x41ae20 LDP	D17, D24, [X22]    [8]

0x41ae24 FMSUB	D6, D4, D23, D6

0x41ae28 FMUL	D5, D5, D24

0x41ae2c FMADD	D5, D7, D17, D5

0x41ae30 FSUB	D7, D21, S19

0x41ae34 FMSUB	D6, D4, D16, D6

0x41ae38 FMUL	D7, D24, D7

0x41ae3c FMSUB	D5, D4, D5, D18

0x41ae40 STR	D6, [X14, X3]    [4]

0x41ae44 FSUB	D6, D22, S20

0x41ae48 FMADD	D6, D17, D6, D7

0x41ae4c FMSUB	D4, D4, D6, D5

0x41ae50 STR	D4, [X0, X3]    [1]

0x41ae54 ADD	X3, X3, #8

0x41ae58 B.HI	41ad80

/home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/accelerate_kernel.f90-pp.f90: 63 - 77

--------------------------------------------------------------------------------

63:       DO j=x_min,x_max+1

[...]

69: # 69 "/home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/accelerate_kernel.f90"

70:         xvel1(j,k)=xvel0(j,k)-stepbymass_s*(xarea(j  ,k  )*(pressure(j  ,k  )-pressure(j-1,k  ))    &

71:           +xarea(j  ,k-1)*(pressure(j  ,k-1)-pressure(j-1,k-1)))

72:         yvel1(j,k)=yvel0(j,k)-stepbymass_s*(yarea(j  ,k  )*(pressure(j  ,k  )-pressure(j  ,k-1))    &

73:           +yarea(j-1,k  )*(pressure(j-1,k  )-pressure(j-1,k-1)))

74:         xvel1(j,k)=xvel1(j,k)-stepbymass_s*(xarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j-1,k  )) &

75:           +xarea(j  ,k-1)*(viscosity(j  ,k-1)-viscosity(j-1,k-1)))

76:         yvel1(j,k)=yvel1(j,k)-stepbymass_s*(yarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j  ,k-1)) &

77:           +yarea(j-1,k  )*(viscosity(j-1,k  )-viscosity(j-1,k-1)))

Path /

Metric	Value
CQA speedup if no scalar integer	1.45
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.63
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P6, P7, P8, P9,
Function	__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_
Source	accelerate_kernel.f90-pp.f90:63-63,accelerate_kernel.f90-pp.f90:69-77
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	1
CQA cycles	7.25
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	7.25
CQA cycles if fully vectorized	2.00
Front-end cycles	6.88
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	7.25
P6 cycles	7.25
P7 cycles	7.25
P8 cycles	7.25
P9 cycles	5.00
P10 cycles	5.00
P11 cycles	5.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	55.00
Nb uops	55.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	5.10
Nb FLOP add-sub	9.00
Nb FLOP mul	7.00
Nb FLOP fma	10.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.48
Bytes prefetched	0.00
Bytes loaded	176.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	52.94
Vectorization ratio load	69.23
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	36.76
Vector-efficiency ratio load	42.31
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	1.45
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.63
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P6, P7, P8, P9,
Function	__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_
Source	accelerate_kernel.f90-pp.f90:63-63,accelerate_kernel.f90-pp.f90:69-77
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	1
CQA cycles	7.25
CQA cycles if no scalar integer	5.00
CQA cycles if FP arith vectorized	7.25
CQA cycles if fully vectorized	2.00
Front-end cycles	6.88
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	7.25
P6 cycles	7.25
P7 cycles	7.25
P8 cycles	7.25
P9 cycles	5.00
P10 cycles	5.00
P11 cycles	5.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	55.00
Nb uops	55.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	5.10
Nb FLOP add-sub	9.00
Nb FLOP mul	7.00
Nb FLOP fma	10.00
Nb FLOP div	1.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.48
Bytes prefetched	0.00
Bytes loaded	176.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	52.94
Vectorization ratio load	69.23
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	36.76
Vector-efficiency ratio load	42.31
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_
Source file and lines	accelerate_kernel.f90-pp.f90:63-77
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-307-1706/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/accelerate_kernel.f90-pp.f90:63,69-77.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.25 to 5.00 cycles (1.45x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

use profile-guided optimization flags of your compiler
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace do i=1,n foo(i) with: select case (n) case (4): do i=1,4 foo(i) case (6): do i=1,6 foo(i) default : do i=1,n foo(i) end select

Vectorization

Your loop is partially vectorized. Only 36% of vector register length is used (average across all VPU instructions).

Details

52% of VPU instructions are used in vector version (process two or more data elements in vector registers):

69% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 10 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 37 FP arithmetical operations:

19: addition or subtraction (10 inside FMA instructions)
17: multiply (10 inside FMA instructions)
1: divide

The binary loop is loading 176 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	55
loop length	220
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	3.00	3.00	3.00	3.00	7.25	7.25	7.25	7.25	5.00	5.00	5.00	0.00	0.00
cycles	0.50	0.50	3.00	3.00	3.00	3.00	7.25	7.25	7.25	7.25	5.00	5.00	5.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.88
Data deps.	1.00
Overall L1	7.25

Vectorization ratios

all	52%
load	69%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.25 cycles. At this rate:

25% of peak load performance is reached (24.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.21 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41ad80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
ADD X21, X18, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X22, X17, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
LDP D4, D5, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X21, X2, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP D6, D7, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X22, X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP D17, D16, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDP D18, D19, [X22, #1016]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X21, X20, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X22, X16, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMUL D5, D5, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D4, D4, D6, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D7, D17, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D17, [X11, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D5, D16, D19, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDP D7, D6, [X22, #1016]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D16, [X6, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X22, X9, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FADD D4, D4, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDP D18, D5, [X21, #1016]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X21, X7, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMUL D4, D4, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDP D20, D19, [X21, #1016]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X21, X10, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FSUB D23, D6, S7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDP D22, D21, [X21, #1016]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D23, D23, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FDIV D4, D0, D4	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FSUB D7, D7, S18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D24, D21, S22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D17, D17, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FSUB D24, D5, S18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D5, D6, S5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR D6, [X12, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D18, [X5, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D23, D24, D16, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FSUB D24, D19, S20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMADD D16, D16, D24, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDP D17, D24, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D6, D4, D23, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D5, D5, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D5, D7, D17, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FSUB D7, D21, S19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMSUB D6, D4, D16, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D7, D24, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMSUB D5, D4, D5, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STR D6, [X14, X3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
FSUB D6, D22, S20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMADD D6, D17, D6, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMSUB D4, D4, D6, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STR D4, [X0, X3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X3, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.HI 41ad80 <__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_+0x430>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_
Source file and lines	accelerate_kernel.f90-pp.f90:63-77
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.25 to 5.00 cycles (1.45x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Unrolling/vectorization cost

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

use profile-guided optimization flags of your compiler
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace do i=1,n foo(i) with: select case (n) case (4): do i=1,4 foo(i) case (6): do i=1,6 foo(i) default : do i=1,n foo(i) end select

Vectorization

Your loop is partially vectorized. Only 36% of vector register length is used (average across all VPU instructions).

Details

52% of VPU instructions are used in vector version (process two or more data elements in vector registers):

69% of VPU loads are used in vector version.
0% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 10 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 37 FP arithmetical operations:

19: addition or subtraction (10 inside FMA instructions)
17: multiply (10 inside FMA instructions)
1: divide

The binary loop is loading 176 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	55
loop length	220
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	3.00	3.00	3.00	3.00	7.25	7.25	7.25	7.25	5.00	5.00	5.00	0.00	0.00
cycles	0.50	0.50	3.00	3.00	3.00	3.00	7.25	7.25	7.25	7.25	5.00	5.00	5.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.88
Data deps.	1.00
Overall L1	7.25

Vectorization ratios

all	52%
load	69%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.25 cycles. At this rate:

25% of peak load performance is reached (24.28 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.21 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41ad80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
ADD X21, X18, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X22, X17, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SUB W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
LDP D4, D5, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X21, X2, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP D6, D7, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X22, X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP D17, D16, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDP D18, D19, [X22, #1016]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X21, X20, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X22, X16, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMUL D5, D5, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D4, D4, D6, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D7, D17, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDR D17, [X11, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D5, D16, D19, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDP D7, D6, [X22, #1016]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D16, [X6, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X22, X9, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FADD D4, D4, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDP D18, D5, [X21, #1016]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X21, X7, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FMUL D4, D4, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
LDP D20, D19, [X21, #1016]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X21, X10, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FSUB D23, D6, S7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDP D22, D21, [X21, #1016]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMUL D23, D23, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FDIV D4, D0, D4	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FSUB D7, D7, S18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D24, D21, S22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D17, D17, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FSUB D24, D5, S18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D5, D6, S5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR D6, [X12, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D18, [X5, X3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D23, D24, D16, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FSUB D24, D19, S20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMADD D16, D16, D24, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDP D17, D24, [X22]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMSUB D6, D4, D23, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D5, D5, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D5, D7, D17, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FSUB D7, D21, S19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMSUB D6, D4, D16, D6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D7, D24, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMSUB D5, D4, D5, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STR D6, [X14, X3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
FSUB D6, D22, S20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMADD D6, D17, D6, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMSUB D4, D4, D6, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STR D4, [X0, X3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X3, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
B.HI 41ad80 <__nv_accelerate_kernel_module_accelerate_kernel__F1L57_1_+0x430>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code