OV - exec - Loop 51

	Loop Id: 51	Module: exec	Source: PdV_kernel.f90-pp.f90:109-138 [...]	Coverage: 0.01%

0x419360 LDP	X8, X9, [SP, #144]

0x419364 SUBS	W11, W11, #1

0x419368 ADD	X19, X19, X8

0x41936c ADD	X23, X23, X8

0x419370 ADD	X24, X24, X8

0x419374 ADD	X26, X26, X8

0x419378 ADD	X16, X16, X8

0x41937c ADD	X0, X0, X8

0x419380 ADD	X4, X4, X8

0x419384 ADD	X2, X2, X8

0x419388 ADD	X17, X17, X8

0x41938c LDR	X8, [SP, #136]

0x419390 ADD	X25, X25, X9

0x419394 ADD	X28, X28, X9

0x419398 ADD	X1, X1, X8

0x41939c ADD	X5, X5, X8

0x4193a0 ADD	X6, X6, X8

0x4193a4 ADD	X7, X7, X8

0x4193a8 ADD	X21, X21, X8

0x4193ac ADD	X22, X22, X8

0x4193b0 ADD	X20, X20, X8

0x4193b4 ADD	X10, X10, X8

0x4193b8 ADD	X30, X30, X8

0x4193bc LDR	X8, [SP, #160]

0x4193c0 ADD	X27, X27, X8

0x4193c4 ADD	X29, X29, X8

0x4193c8 B.LE	419c20

0x4193cc LDR	X8, [SP, #168]

0x4193d0 LDR	X12, [SP, #184]

0x4193d4 LDR	W9, [SP, #176]

0x4193d8 CMP	X8, X15

0x4193dc STR	W11, [SP, #300]

0x4193e0 STR	X29, [SP, #288]

0x4193e4 B.CC	419574

0x4193e8 LDR	X9, [SP, #168]

0x4193ec ORR	X11, XZR, XZR

0x4193f0 UDIV	X8, X9, X15

0x4193f4 MADD	X13, X8, X15, XZR

0x4193f8 SUB	X8, X9, X13

0x4193fc LDR	X9, [SP, #184]

0x419400 STR	X8, [SP, #272]

0x419404 ADD	X12, X13, X9

0x419408 LDR	W9, [SP, #176]

0x41940c SUB	W8, W9, W13

0x419410 STR	W8, [SP, #280]

0x419414 HINT	#0

0x419418 HINT	#0

0x41941c HINT	#0

  (52) 0x419420 UBFM	X14, X11, #61, #60

  (52) 0x419424 ORR	X8, XZR, X16

  (52) 0x419428 ORR	X9, XZR, X0

  (52) 0x41942c ORR	X29, XZR, X2

  (52) 0x419430 ADD	X15, X26, X14

  (52) 0x419434 LD1D	{Z7.D}, P0/Z, [X15, MUL VL]

  (52) 0x419438 ADD	X16, X17, X14

  (52) 0x41943c LD1D	{Z16.D}, P0/Z, [X16, MUL VL]

  (52) 0x419440 ADD	X0, X24, X14

  (52) 0x419444 ADD	X2, X2, X14

  (52) 0x419448 ADD	X3, X4, X14

  (52) 0x41944c FADD	Z7.D, Z7.D, Z16.D

  (52) 0x419450 LD1D	{Z16.D}, P0/Z, [X0, MUL VL]

  (52) 0x419454 LD1D	{Z17.D}, P0/Z, [X2, MUL VL]

  (52) 0x419458 FADD	Z16.D, Z16.D, Z17.D

  (52) 0x41945c FADD	Z7.D, Z7.D, Z16.D

  (52) 0x419460 LD1D	{Z16.D}, P0/Z, [X3, MUL VL]

  (52) 0x419464 LD1D	{Z17.D}, P0/Z, [X16, X18,LSL #3]

  (52) 0x419468 LD1D	{Z18.D}, P0/Z, [X2, X18,LSL #3]

  (52) 0x41946c ORR	X16, XZR, X8

  (52) 0x419470 ORR	X2, XZR, X29

  (52) 0x419474 FMUL	Z7.D, Z7.D, Z16.D

  (52) 0x419478 LD1D	{Z16.D}, P0/Z, [X15, X18,LSL #3]

  (52) 0x41947c ADD	X15, X9, X14

  (52) 0x419480 FMUL	Z7.D, Z7.D, Z5.D

  (52) 0x419484 FADD	Z16.D, Z16.D, Z17.D

  (52) 0x419488 LD1D	{Z17.D}, P0/Z, [X0, X18,LSL #3]

  (52) 0x41948c FMUL	Z7.D, Z2.D, Z7.D

  (52) 0x419490 ORR	X0, XZR, X9

  (52) 0x419494 FADD	Z17.D, Z17.D, Z18.D

  (52) 0x419498 FADD	Z16.D, Z16.D, Z17.D

  (52) 0x41949c LD1D	{Z17.D}, P0/Z, [X3, X18,LSL #3]

  (52) 0x4194a0 FMUL	Z16.D, Z17.D, Z16.D

  (52) 0x4194a4 LD1D	{Z17.D}, P0/Z, [X15, X18,LSL #3]

  (52) 0x4194a8 LD1D	{Z18.D}, P0/Z, [X15, MUL VL]

  (52) 0x4194ac ADD	X15, X8, X14

  (52) 0x4194b0 FMUL	Z16.D, Z16.D, Z5.D

  (52) 0x4194b4 FADD	Z17.D, Z17.D, Z18.D

  (52) 0x4194b8 LD1D	{Z18.D}, P0/Z, [X15, X18,LSL #3]

  (52) 0x4194bc LD1D	{Z19.D}, P0/Z, [X15, MUL VL]

  (52) 0x4194c0 ADD	X15, X23, X14

  (52) 0x4194c4 ADD	X14, X19, X14

  (52) 0x4194c8 FNMLS	Z7.D, P0/M, Z2.D, Z16.D

  (52) 0x4194cc FADD	Z18.D, Z18.D, Z19.D

  (52) 0x4194d0 FADD	Z17.D, Z17.D, Z18.D

  (52) 0x4194d4 LD1D	{Z18.D}, P0/Z, [X10, X11,LSL #3]

  (52) 0x4194d8 FMUL	Z17.D, Z17.D, Z18.D

  (52) 0x4194dc LD1D	{Z18.D}, P0/Z, [X15, X18,LSL #3]

  (52) 0x4194e0 LD1D	{Z19.D}, P0/Z, [X15, MUL VL]

  (52) 0x4194e4 CNTD	X15, ALL

  (52) 0x4194e8 FMUL	Z17.D, Z17.D, Z5.D

  (52) 0x4194ec FADD	Z18.D, Z18.D, Z19.D

  (52) 0x4194f0 LD1D	{Z19.D}, P0/Z, [X14, X18,LSL #3]

  (52) 0x4194f4 LD1D	{Z20.D}, P0/Z, [X14, MUL VL]

  (52) 0x4194f8 LD1D	{Z16.D}, P0/Z, [X20, X11,LSL #3]

  (52) 0x4194fc FADD	Z19.D, Z19.D, Z20.D

  (52) 0x419500 LD1D	{Z20.D}, P0/Z, [X7, X11,LSL #3]

  (52) 0x419504 FADD	Z18.D, Z18.D, Z19.D

  (52) 0x419508 LD1D	{Z19.D}, P0/Z, [X30, X11,LSL #3]

  (52) 0x41950c FMUL	Z18.D, Z19.D, Z18.D

  (52) 0x419510 LD1D	{Z19.D}, P0/Z, [X21, X11,LSL #3]

  (52) 0x419514 FMUL	Z18.D, Z18.D, Z5.D

  (52) 0x419518 FMLA	Z7.D, P0/M, Z2.D, Z18.D

  (52) 0x41951c LD1D	{Z18.D}, P0/Z, [X22, X11,LSL #3]

  (52) 0x419520 FDIV	Z20.D, P0/M, Z20.D, Z19.D

  (52) 0x419524 FMLS	Z7.D, P0/M, Z2.D, Z17.D

  (52) 0x419528 FDIV	Z18.D, P0/M, Z18.D, Z19.D

  (52) 0x41952c FADD	Z17.D, Z16.D, Z7.D

  (52) 0x419530 FDIVR	Z17.D, P0/M, Z17.D, Z16.D

  (52) 0x419534 FDIVR	Z16.D, P0/M, Z16.D, Z6.D

  (52) 0x419538 FADD	Z18.D, Z18.D, Z20.D

  (52) 0x41953c FMUL	Z7.D, Z7.D, Z18.D

  (52) 0x419540 LD1D	{Z18.D}, P0/Z, [X6, X11,LSL #3]

  (52) 0x419544 FMSB	Z7.D, P0/M, Z16.D, Z18.D

  (52) 0x419548 ST1D	{Z7.D}, P0, [X5, X11,LSL #3]

  (52) 0x41954c FMUL	Z7.D, Z19.D, Z17.D

  (52) 0x419550 ST1D	{Z7.D}, P0, [X1, X11,LSL #3]

  (52) 0x419554 ADD	X11, X11, X15

  (52) 0x419558 CMP	X13, X11

  (52) 0x41955c B.NE	419420

0x419560 LDR	W11, [SP, #300]

0x419564 LDR	X29, [SP, #288]

0x419568 LDR	W9, [SP, #280]

0x41956c LDR	X8, [SP, #272]

0x419570 CBZ	X8, 419360

0x419574 ADD	X14, X12, X28

0x419578 STP	X0, X16, [SP, #208]

0x41957c STP	X23, X19, [SP, #240]

0x419580 LDR	X16, [SP, #112]

0x419584 LDR	X23, [SP, #32]

0x419588 ADD	W13, W9, #1

0x41958c ADD	X9, X12, X25

0x419590 ADD	X11, X12, X27

0x419594 STP	X30, X28, [SP, #256]

0x419598 ADD	X12, X12, X29

0x41959c STP	X26, X24, [SP, #224]

0x4195a0 STP	X2, X4, [SP, #192]

0x4195a4 ORR	X8, XZR, XZR

0x4195a8 UBFM	X30, X14, #61, #60

0x4195ac UBFM	X11, X11, #61, #60

0x4195b0 LDP	X14, X19, [SP, #120]

0x4195b4 UBFM	X24, X12, #61, #60

0x4195b8 STP	X27, X25, [SP, #272]

0x4195bc ADD	X15, X16, X9,LSL #3

0x4195c0 ADD	X0, X23, X11

0x4195c4 ADD	X4, X16, X30

0x4195c8 LDP	X25, X16, [SP, #96]

0x4195cc ADD	X3, X25, X11

0x4195d0 ADD	X9, X14, X11

0x4195d4 ADD	X2, X19, X11

0x4195d8 ADD	X12, X14, X24

0x4195dc ADD	X14, X23, X24

0x4195e0 ADD	X23, X19, X24

0x4195e4 LDR	X19, [SP, #40]

0x4195e8 LDR	X11, [SP, #88]

0x4195ec ADD	X16, X16, X24

0x4195f0 ADD	X24, X25, X24

0x4195f4 ADD	X25, X19, X30

0x4195f8 LDR	X19, [SP, #56]

0x4195fc ADD	X11, X11, X30

0x419600 ADD	X26, X19, X30

0x419604 LDR	X19, [SP, #48]

0x419608 ADD	X27, X19, X30

0x41960c LDR	X19, [SP, #72]

0x419610 ADD	X28, X19, X30

0x419614 LDR	X19, [SP, #80]

0x419618 ADD	X29, X19, X30

0x41961c LDR	X19, [SP, #64]

0x419620 ADD	X30, X19, X30

  (50) 0x419624 LDR	Q7, [X3, X8]

  (50) 0x419628 LDR	Q16, [X24, X8]

  (50) 0x41962c LDR	Q17, [X23, X8]

  (50) 0x419630 ADD	X19, X14, X8

  (50) 0x419634 SUB	W13, W13, #1

  (50) 0x419638 LDR	D20, [X28, X8]

  (50) 0x41963c CMP	W13, #1

  (50) 0x419640 FADD	V7.2D, V7.2D, V16.2D

  (50) 0x419644 LDR	Q16, [X2, X8]

  (50) 0x419648 FADD	V16.2D, V16.2D, V17.2D

  (50) 0x41964c FADD	V7.2D, V7.2D, V16.2D

  (50) 0x419650 LDR	Q16, [X16, X8]

  (50) 0x419654 FMUL	V7.2D, V16.2D, V7.2D

  (50) 0x419658 LDP	D17, D16, [X19, #1016]

  (50) 0x41965c ADD	X19, X12, X8

  (50) 0x419660 FMUL	V7.2D, V7.2D, V1.2D

  (50) 0x419664 FADD	D16, D16, D17

  (50) 0x419668 LDP	D18, D17, [X19, #1016]

  (50) 0x41966c ADD	X19, X0, X8

  (50) 0x419670 FMUL	V7.2D, V7.2D, V0.D[0]

  (50) 0x419674 FADD	D17, D17, D18

  (50) 0x419678 FADD	D16, D16, D17

  (50) 0x41967c LDR	D17, [X4, X8]

  (50) 0x419680 FMUL	D16, D16, D17

  (50) 0x419684 LDP	D18, D17, [X19, #1016]

  (50) 0x419688 ADD	X19, X9, X8

  (50) 0x41968c FMUL	D16, D16, D3

  (50) 0x419690 FADD	D17, D17, D18

  (50) 0x419694 LDP	D19, D18, [X19, #1016]

  (50) 0x419698 FADD	D18, D18, D19

  (50) 0x41969c LDR	D19, [X29, X8]

  (50) 0x4196a0 FADD	D17, D17, D18

  (50) 0x4196a4 LDR	D18, [X15, X8]

  (50) 0x4196a8 FDIV	D20, D20, D19

  (50) 0x4196ac FMUL	D17, D18, D17

  (50) 0x4196b0 DUP	V18.2D, V7.D[1]

  (50) 0x4196b4 FSUB	V7.2D, V18.2D, V7.2D

  (50) 0x4196b8 LDR	D18, [X30, X8]

  (50) 0x4196bc FMUL	D17, D17, D3

  (50) 0x4196c0 FMADD	D7, D0, D17, D7

  (50) 0x4196c4 FDIV	D18, D18, D19

  (50) 0x4196c8 FMSUB	D7, D0, D16, D7

  (50) 0x4196cc LDR	D16, [X11, X8]

  (50) 0x4196d0 FADD	D17, D16, D7

  (50) 0x4196d4 FDIV	D17, D16, D17

  (50) 0x4196d8 FDIV	D16, D4, D16

  (50) 0x4196dc FADD	D18, D18, D20

  (50) 0x4196e0 FMUL	D7, D7, D18

  (50) 0x4196e4 LDR	D18, [X27, X8]

  (50) 0x4196e8 FMADD	D7, D16, D7, D18

  (50) 0x4196ec STR	D7, [X26, X8]

  (50) 0x4196f0 FMUL	D7, D19, D17

  (50) 0x4196f4 STR	D7, [X25, X8]

  (50) 0x4196f8 ADD	X8, X8, #8

  (50) 0x4196fc B.HI	419624

0x419700 LDR	W11, [SP, #300]

0x419704 LDP	X27, X25, [SP, #272]

0x419708 LDP	X30, X28, [SP, #256]

0x41970c CNTD	X15, ALL

0x419710 LDR	X29, [SP, #288]

0x419714 LDP	X23, X19, [SP, #240]

0x419718 LDP	X26, X24, [SP, #224]

0x41971c LDP	X0, X16, [SP, #208]

0x419720 LDP	X2, X4, [SP, #192]

0x419724 B	419360

/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/PdV_kernel.f90-pp.f90: 109 - 138

--------------------------------------------------------------------------------

109:       !$OMP            energy_change,recip_volume,volume_change_s)

110:       DO k=y_min,y_max

111:       !$OMP SIMD

112:         DO j=x_min,x_max

113: # 113 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

114:           left_flux=  (xarea(j  ,k  )*(xvel0(j  ,k  )+xvel0(j  ,k+1)                     &

115:             +xvel1(j  ,k  )+xvel1(j  ,k+1)))*0.25_8*dt

116:           right_flux= (xarea(j+1,k  )*(xvel0(j+1,k  )+xvel0(j+1,k+1)                     &

117:             +xvel1(j+1,k  )+xvel1(j+1,k+1)))*0.25_8*dt

118:           bottom_flux=(yarea(j  ,k  )*(yvel0(j  ,k  )+yvel0(j+1,k  )                     &

119:             +yvel1(j  ,k  )+yvel1(j+1,k  )))*0.25_8*dt

120:           top_flux=   (yarea(j  ,k+1)*(yvel0(j  ,k+1)+yvel0(j+1,k+1)                     &

121:             +yvel1(j  ,k+1)+yvel1(j+1,k+1)))*0.25_8*dt

122:           total_flux=right_flux-left_flux+top_flux-bottom_flux

123: # 123 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

[...]

129:

130:           recip_volume=1.0/volume(j,k)

131: # 131 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

132:           energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume

133: # 133 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

134:           energy1(j,k)=energy0(j,k)-energy_change

135: # 135 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

136:           density1(j,k)=density0(j,k)*volume_change_s

137: # 137 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

138:         ENDDO

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.34
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.19
Bottlenecks
Function	__nv_pdv_kernel_module_pdv_kernel__F1L67_1_
Source	PdV_kernel.f90-pp.f90:109-111,PdV_kernel.f90-pp.f90:135-138
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	10.25
CQA cycles if no scalar integer	10.25
CQA cycles if FP arith vectorized	10.25
CQA cycles if fully vectorized	2.36
Front-end cycles	8.63
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	10.25
P2 cycles	10.25
P3 cycles	10.25
P4 cycles	10.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	8.33
P10 cycles	8.33
P11 cycles	8.33
P12 cycles	3.00
P13 cycles	3.00
P14 cycles	0.50 - 0.25
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	70.50
Nb uops	69.00
Nb loads	NA
Nb stores	6.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.31
Bytes prefetched	0.00
Bytes loaded	180.00
Bytes stored	66.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.49
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	24.45
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.36
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	P2, P3, P4, P5,
Function	__nv_pdv_kernel_module_pdv_kernel__F1L67_1_
Source	PdV_kernel.f90-pp.f90:109-111,PdV_kernel.f90-pp.f90:135-138
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.50
CQA cycles if no scalar integer	7.50
CQA cycles if FP arith vectorized	7.50
CQA cycles if fully vectorized	1.72
Front-end cycles	6.25
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	7.50
P2 cycles	7.50
P3 cycles	7.50
P4 cycles	7.50
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	5.67
P10 cycles	5.67
P11 cycles	5.67
P12 cycles	2.00
P13 cycles	2.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	53.00
Nb uops	50.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.00
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	24.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.52
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	24.48
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.33
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.18
Bottlenecks	P2, P3, P4, P5,
Function	__nv_pdv_kernel_module_pdv_kernel__F1L67_1_
Source	PdV_kernel.f90-pp.f90:109-111,PdV_kernel.f90-pp.f90:135-138
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	13.00
CQA cycles if no scalar integer	13.00
CQA cycles if FP arith vectorized	13.00
CQA cycles if fully vectorized	3.00
Front-end cycles	11.00
DIV/SQRT cycles	1.50
P0 cycles	1.50
P1 cycles	13.00
P2 cycles	13.00
P3 cycles	13.00
P4 cycles	13.00
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	11.00
P10 cycles	11.00
P11 cycles	11.00
P12 cycles	4.00
P13 cycles	4.00
P14 cycles	0.00
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	88.00
Nb uops	88.00
Nb loads	NA
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.62
Bytes prefetched	0.00
Bytes loaded	264.00
Bytes stored	108.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.46
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	24.42
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__nv_pdv_kernel_module_pdv_kernel__F1L67_1_
Source file and lines	PdV_kernel.f90-pp.f90:109-138
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/PdV_kernel.f90-pp.f90:109-123,129-138.

Analyzed code is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/PdV_kernel.f90-pp.f90:109-111,135-138.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 10.25 to 2.36 cycles (4.34x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 180 bytes. The binary loop is storing 66 bytes.

General properties

nb instructions	70.50
loop length	282
nb stack references	0

Front-end

front end

8.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	10.25	10.25	10.25	10.25	0.00	0.00	0.00	0.00	8.33	8.33	8.33	3.00	3.00
cycles	1.50	1.50	10.25	10.25	10.25	10.25	0.00	0.00	0.00	0.00	8.33	8.33	8.33	3.00	3.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	0.50-0.25
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	8.63
Data deps.	3.00
Overall L1	10.25

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 10.25 cycles. At this rate:

17% of peak load performance is reached (16.55 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (5.75 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

Function	__nv_pdv_kernel_module_pdv_kernel__F1L67_1_
Source file and lines	PdV_kernel.f90-pp.f90:109-138
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 96 bytes. The binary loop is storing 24 bytes.

General properties

nb instructions	53
loop length	212
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	5.67	5.67	5.67	2.00	2.00
cycles	1.50	1.50	7.50	7.50	7.50	7.50	0.00	0.00	0.00	0.00	5.67	5.67	5.67	2.00	2.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	1.00-0.50
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	6.25
Data deps.	3.00
Overall L1	7.50

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.50 cycles. At this rate:

13% of peak load performance is reached (12.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (3.20 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4193cc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDP X8, X9, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUBS W11, W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X19, X19, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X23, X23, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X24, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X26, X26, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X16, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X17, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X25, X25, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X28, X28, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X5, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X6, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X7, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X21, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X22, X22, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X20, X20, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X30, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X27, X27, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X29, X29, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.LE 419c20 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0xb00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
STR W11, [SP, #300]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X29, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.CC 419574 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x454>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X11, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UDIV X8, X9, X15	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
MADD X13, X8, X15, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X8, X9, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X9, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
STR X8, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X12, X13, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W9, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
SUB W8, W9, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W8, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
HINT #0
HINT #0
HINT #0
LDR W11, [SP, #300]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X29, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X8, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CBZ X8, 419360 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x240>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	__nv_pdv_kernel_module_pdv_kernel__F1L67_1_
Source file and lines	PdV_kernel.f90-pp.f90:109-138
Module	exec

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 264 bytes. The binary loop is storing 108 bytes.

General properties

nb instructions	88
loop length	352
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	1.50	1.50	13.00	13.00	13.00	13.00	0.00	0.00	0.00	0.00	11.00	11.00	11.00	4.00	4.00
cycles	1.50	1.50	13.00	13.00	13.00	13.00	0.00	0.00	0.00	0.00	11.00	11.00	11.00	4.00	4.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	11.00
Data deps.	3.00
Overall L1	13.00

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 13.00 cycles. At this rate:

21% of peak load performance is reached (20.31 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
17% of peak store performance is reached (8.31 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4193cc

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDP X8, X9, [SP, #144]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUBS W11, W11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
ADD X19, X19, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X23, X23, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X24, X24, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X26, X26, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X16, X16, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X4, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X2, X2, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X17, X17, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X8, [SP, #136]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X25, X25, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X28, X28, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X1, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X5, X5, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X6, X6, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X7, X7, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X21, X21, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X22, X22, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X20, X20, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X10, X10, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X30, X30, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X8, [SP, #160]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X27, X27, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X29, X29, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B.LE 419c20 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0xb00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #168]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X12, [SP, #184]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [SP, #176]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
STR W11, [SP, #300]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STR X29, [SP, #288]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
B.CC 419574 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x454>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X14, X12, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X0, X16, [SP, #208]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X23, X19, [SP, #240]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X16, [SP, #112]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X23, [SP, #32]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD W13, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X9, X12, X25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X11, X12, X27	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X30, X28, [SP, #256]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X12, X12, X29	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X26, X24, [SP, #224]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
STP X2, X4, [SP, #192]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ORR X8, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X30, X14, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
UBFM X11, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDP X14, X19, [SP, #120]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
UBFM X24, X12, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STP X27, X25, [SP, #272]	1	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X15, X16, X9,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X23, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X4, X16, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDP X25, X16, [SP, #96]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X3, X25, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X9, X14, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X2, X19, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X12, X14, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X14, X23, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X23, X19, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X19, [SP, #40]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X11, [SP, #88]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X16, X16, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X24, X25, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X25, X19, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X19, [SP, #56]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X11, X11, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X26, X19, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X19, [SP, #48]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X27, X19, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X19, [SP, #72]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X28, X19, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X19, [SP, #80]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X29, X19, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR X19, [SP, #64]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X30, X19, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR W11, [SP, #300]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X27, X25, [SP, #272]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X30, X28, [SP, #256]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CNTD X15, ALL	1	0	0	0	0	1	0	0	0	0	0	0	2	1
LDR X29, [SP, #288]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X23, X19, [SP, #240]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X26, X24, [SP, #224]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X0, X16, [SP, #208]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X2, X4, [SP, #192]	1	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
B 419360 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x240>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code