OV - exec - Loop 507

0x430b30 CMP	W26, W25

0x430b34 B.CC	439eec

0x430b38 CNTB	X2, ALL

0x430b3c ADD	X24, X14, X8

0x430b40 SUB	X0, XZR, X2

0x430b44 ADD	X1, X12, X8

0x430b48 ADD	X13, X0, #8

0x430b4c ADD	X16, X9, X1,LSL #3

0x430b50 MOVZ	W18, #0

0x430b54 ADD	X11, X13, X24,LSL #3

0x430b58 ADD	X17, X9, X11

0x430b5c HINT	#0

  (509) 0x430b60 LD1D	{Z26.D}, P3/Z, [X17, MUL VL]

  (509) 0x430b64 ORR	W15, WZR, W18

  (509) 0x430b68 REV	Z27.D, Z26.D

  (509) 0x430b6c ADD	W18, W18, W3

  (509) 0x430b70 ST1D	{Z27.D}, P3, [X16, MUL VL]

  (509) 0x430b74 ADD	X17, X17, X4

  (509) 0x430b78 ADD	X16, X16, X5

  (509) 0x430b7c CMP	W18, W6

  (509) 0x430b80 B.LS	430b60

0x430b84 ADD	W23, W15, W30

0x430b88 CMP	W18, W22

0x430b8c B.EQ	430cc8

0x430b90 SBFM	X23, X23, #0, #31

0x430b94 ADD	X1, X9, X24,LSL #3

0x430b98 SUB	X24, X8, X23

0x430b9c SUB	W0, W22, W23

0x430ba0 ADD	X2, X24, X12

0x430ba4 AND	W13, W0, #128

0x430ba8 ADD	X11, X9, X2,LSL #3

0x430bac ADD	X0, X23, #1

0x430bb0 LDR	D28, [X9, X2,LSL #3]

0x430bb4 SUB	X2, X11, #8

0x430bb8 STR	D28, [X1, X23,LSL #3]

0x430bbc CMP	W22, W0

0x430bc0 B.LT	430cc8

0x430bc4 CBZ	W13, 430c58

  (508) 0x430c58 ORR	X11, XZR, X2

  (508) 0x430c5c ADD	X13, X0, #1

  (508) 0x430c60 ADD	X24, X0, #2

  (508) 0x430c64 ADD	X23, X0, #3

  (508) 0x430c68 LDR	D5, [X11], #504

  (508) 0x430c6c ADD	X18, X0, #4

  (508) 0x430c70 ADD	X17, X0, #5

  (508) 0x430c74 ADD	X16, X0, #6

  (508) 0x430c78 ADD	X15, X0, #7

  (508) 0x430c7c SUB	X2, X2, #64

  (508) 0x430c80 STR	D5, [X1, X0,LSL #3]

  (508) 0x430c84 ADD	X0, X0, #8

  (508) 0x430c88 LDR	D6, [X2, #56]

  (508) 0x430c8c STR	D6, [X1, X13,LSL #3]

  (508) 0x430c90 LDUR	D7, [X11, #504]

  (508) 0x430c94 STR	D7, [X1, X24,LSL #3]

  (508) 0x430c98 LDR	D16, [X2, #40]

  (508) 0x430c9c STR	D16, [X1, X23,LSL #3]

  (508) 0x430ca0 LDR	D17, [X2, #32]

  (508) 0x430ca4 STR	D17, [X1, X18,LSL #3]

  (508) 0x430ca8 LDR	D18, [X2, #24]

  (508) 0x430cac STR	D18, [X1, X17,LSL #3]

  (508) 0x430cb0 LDR	D19, [X2, #16]

  (508) 0x430cb4 STR	D19, [X1, X16,LSL #3]

  (508) 0x430cb8 LDR	D20, [X2, #8]

  (508) 0x430cbc STR	D20, [X1, X15,LSL #3]

  (508) 0x430cc0 CMP	W22, W0

  (508) 0x430cc4 B.GE	430c58

0x430cc8 ADD	W7, W7, #1

0x430ccc ADD	X8, X8, X28

0x430cd0 CMP	W10, W7

0x430cd4 B.GT	430b30

0x439eec MOVZ	W23, #1

0x439ef0 ADD	X24, X14, X8

0x439ef4 B	430b90

/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90: 346 - 350

--------------------------------------------------------------------------------

346:         !$OMP DO

347:         DO k=y_min-depth,y_max+depth

348:         !$OMP SIMD

349:           DO j=1,depth

350:             viscosity(x_max+j,k)=viscosity(x_max+1-j,k)

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	update_halo_kernel	update_halo_kernel.f90:754	exec
○	update_halo	update_halo.f90:78	exec
○	timestep	timestep.f90:82	exec
○	hydro	hydro.f90:54	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec

Path /

Metric	Value
CQA speedup if no scalar integer	6.75
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.35
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.54
Bottlenecks	P2, P3, P4, P5,
Function	update_halo_kernel._omp_fn.0
Source	update_halo_kernel.f90:346-346,update_halo_kernel.f90:350-350
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.75
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	6.75
CQA cycles if fully vectorized	1.06
Front-end cycles	4.38
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	6.75
P2 cycles	6.75
P3 cycles	6.75
P4 cycles	6.75
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.83
P10 cycles	0.50
P11 cycles	0.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	35.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.37
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	19.12
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	22.22
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	6.75
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.35
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.54
Bottlenecks	P2, P3, P4, P5,
Function	update_halo_kernel._omp_fn.0
Source	update_halo_kernel.f90:346-346,update_halo_kernel.f90:350-350
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	6.75
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	6.75
CQA cycles if fully vectorized	1.06
Front-end cycles	4.38
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	6.75
P2 cycles	6.75
P3 cycles	6.75
P4 cycles	6.75
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.83
P10 cycles	0.50
P11 cycles	0.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	36.00
Nb uops	35.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.37
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	19.12
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	22.22
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	update_halo_kernel._omp_fn.0
Source file and lines	update_halo_kernel.f90:346-350
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90:346-350.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90:346,350.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.75 to 1.00 cycles (6.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 19% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.75 to 1.06 cycles (6.35x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	36
loop length	144
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	6.75	6.75	6.75	6.75	0.50	0.50	0.00	0.00	0.83	0.50	0.67	0.00	0.00
cycles	3.00	3.00	6.75	6.75	6.75	6.75	0.50	0.50	0.00	0.00	0.83	0.50	0.67	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.38
Overall L1	6.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.75 cycles. At this rate:

1% of peak load performance is reached (1.19 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.19 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 430b30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
CMP W26, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 439eec <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0xa6ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CNTB X2, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X24, X14, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X0, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X12, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X9, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W18, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X13, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
ADD W23, W15, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W18, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 430cc8 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x14c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X23, X23, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X9, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X24, X8, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W0, W22, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X24, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W13, W0, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X9, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D28, [X9, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
SUB X2, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D28, [X1, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP W22, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 430cc8 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x14c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W13, 430c58 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x1458>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W7, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W10, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 430b30 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x1330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X14, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 430b90 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x1390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	update_halo_kernel._omp_fn.0
Source file and lines	update_halo_kernel.f90:346-350
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90:346-350.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90:346,350.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.75 to 1.00 cycles (6.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 19% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 6.75 to 1.06 cycles (6.35x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	36
loop length	144
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	6.75	6.75	6.75	6.75	0.50	0.50	0.00	0.00	0.83	0.50	0.67	0.00	0.00
cycles	3.00	3.00	6.75	6.75	6.75	6.75	0.50	0.50	0.00	0.00	0.83	0.50	0.67	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	4.38
Overall L1	6.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 6.75 cycles. At this rate:

1% of peak load performance is reached (1.19 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.19 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 430b30

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
CMP W26, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 439eec <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0xa6ec>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CNTB X2, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
ADD X24, X14, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X0, XZR, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X12, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X9, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ W18, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X13, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X9, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
ADD W23, W15, W30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W18, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 430cc8 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x14c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X23, X23, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X9, X24,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X24, X8, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W0, W22, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X24, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W13, W0, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X9, X2,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR D28, [X9, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
SUB X2, X11, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR D28, [X1, X23,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP W22, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 430cc8 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x14c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W13, 430c58 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x1458>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W7, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, X28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W10, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 430b30 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x1330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W23, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X14, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 430b90 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x1390>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

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ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code