OV - exec - Loop 490

0x439380 CMP	W17, W23

0x439384 B.CC	439e08

0x439388 ADD	X27, X1, #8

0x43938c ADD	X12, X1, X3

0x439390 MOVZ	X11, #0

0x439394 HINT	#0

0x439398 HINT	#0

0x43939c HINT	#0

  (492) 0x4393a0 LD1D	{Z6.D}, P6/Z, [X27, X11,LSL #3]

  (492) 0x4393a4 ORR	W14, WZR, W11

  (492) 0x4393a8 ADD	W15, W4, W11

  (492) 0x4393ac FNEG	Z6.D, P6/M, Z6.D

  (492) 0x4393b0 ADD	X11, X11, X5

  (492) 0x4393b4 REV	Z7.D, Z6.D

  (492) 0x4393b8 ST1D	{Z7.D}, P6, [X12, MUL VL]

  (492) 0x4393bc ADD	X12, X12, X3

  (492) 0x4393c0 CMP	W6, W11

  (492) 0x4393c4 B.CS	4393a0

0x4393c8 ADD	W9, W14, W25

0x4393cc CMP	W15, W22

0x4393d0 B.EQ	43954c

0x4393d4 SBFM	X16, X9, #0, #31

0x4393d8 ADD	X13, X24, X1

0x4393dc ADD	X30, X13, #8

0x4393e0 SUB	W2, W22, W9

0x4393e4 SUB	X26, X30, W9,SXTW #3

0x4393e8 LDR	D1, [X1, X16,LSL #3]

0x4393ec ADD	X28, X10, X26

0x4393f0 ADD	X0, X16, #1

0x4393f4 AND	W9, W2, #128

0x4393f8 SUB	X27, X28, #8

0x4393fc FNEG	D16, D1

0x439400 STR	D16, [X10, X26]

0x439404 CMP	W22, W0

0x439408 B.LT	43954c

0x43940c CBZ	W9, 4394bc

  (491) 0x4394bc LDR	D30, [X1, X0,LSL #3]

  (491) 0x4394c0 ORR	X30, XZR, X27

  (491) 0x4394c4 ADD	X11, X0, #1

  (491) 0x4394c8 ADD	X16, X0, #2

  (491) 0x4394cc ADD	X15, X0, #3

  (491) 0x4394d0 ADD	X14, X0, #4

  (491) 0x4394d4 ADD	X13, X0, #5

  (491) 0x4394d8 ADD	X12, X0, #6

  (491) 0x4394dc ADD	X2, X0, #7

  (491) 0x4394e0 ADD	X0, X0, #8

  (491) 0x4394e4 SUB	X27, X27, #64

  (491) 0x4394e8 FNEG	D31, D30

  (491) 0x4394ec STR	D31, [X30], #504

  (491) 0x4394f0 LDR	D2, [X1, X11,LSL #3]

  (491) 0x4394f4 FNEG	D3, D2

  (491) 0x4394f8 STR	D3, [X27, #56]

  (491) 0x4394fc LDR	D4, [X1, X16,LSL #3]

  (491) 0x439500 FNEG	D5, D4

  (491) 0x439504 STUR	D5, [X30, #504]

  (491) 0x439508 LDR	D6, [X1, X15,LSL #3]

  (491) 0x43950c FNEG	D7, D6

  (491) 0x439510 STR	D7, [X27, #40]

  (491) 0x439514 LDR	D1, [X1, X14,LSL #3]

  (491) 0x439518 FNEG	D16, D1

  (491) 0x43951c STR	D16, [X27, #32]

  (491) 0x439520 LDR	D17, [X1, X13,LSL #3]

  (491) 0x439524 FNEG	D18, D17

  (491) 0x439528 STR	D18, [X27, #24]

  (491) 0x43952c LDR	D19, [X1, X12,LSL #3]

  (491) 0x439530 FNEG	D20, D19

  (491) 0x439534 STR	D20, [X27, #16]

  (491) 0x439538 LDR	D21, [X1, X2,LSL #3]

  (491) 0x43953c FNEG	D22, D21

  (491) 0x439540 STR	D22, [X27, #8]

  (491) 0x439544 CMP	W22, W0

  (491) 0x439548 B.GE	4394bc

0x43954c ADD	W7, W7, #1

0x439550 ADD	X1, X1, X18

0x439554 CMP	W8, W7

0x439558 B.GT	439380

0x439e08 MOVZ	W9, #1

0x439e0c B	4393d4

/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90: 426 - 430

--------------------------------------------------------------------------------

426:         !$OMP DO

427:         DO k=y_min-depth,y_max+1+depth

428:         !$OMP SIMD

429:           DO j=1,depth

430:             xvel0(1-j,k)=-xvel0(1+j,k)

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	update_halo_kernel	update_halo_kernel.f90:754	exec
○	update_halo	update_halo.f90:78	exec
○	timestep	timestep.f90:74	exec
○	hydro	hydro.f90:54	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec

Path /

Metric	Value
CQA speedup if no scalar integer	6.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.93
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks	P2, P3, P4, P5,
Function	update_halo_kernel._omp_fn.0
Source	update_halo_kernel.f90:426-426,update_halo_kernel.f90:430-430
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	0.83
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	0.84
Front-end cycles	3.63
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	5.00
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	5.00
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.83
P10 cycles	0.50
P11 cycles	0.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	32.00
Nb uops	29.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.20
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	19.85
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	22.22
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.58

Metric	Value
CQA speedup if no scalar integer	6.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.93
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.38
Bottlenecks	P2, P3, P4, P5,
Function	update_halo_kernel._omp_fn.0
Source	update_halo_kernel.f90:426-426,update_halo_kernel.f90:430-430
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	0.83
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	0.84
Front-end cycles	3.63
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	5.00
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	5.00
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.50
P8 cycles	0.50
P9 cycles	0.83
P10 cycles	0.50
P11 cycles	0.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	32.00
Nb uops	29.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.20
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	19.85
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	22.22
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.58

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	update_halo_kernel._omp_fn.0
Source file and lines	update_halo_kernel.f90:426-430
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90:426-430.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90:426,430.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.00 to 0.83 cycles (6.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 19% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.00 to 0.84 cycles (5.93x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	5.00	5.00	5.00	5.00	0.50	0.50	0.50	0.50	0.83	0.50	0.67	0.00	0.00
cycles	3.00	3.00	5.00	5.00	5.00	5.00	0.50	0.50	0.50	0.50	0.83	0.50	0.67	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.63
Overall L1	5.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

1% of peak load performance is reached (1.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.60 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 439380

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
CMP W17, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 439e08 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0xa608>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X27, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
ADD W9, W14, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W15, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 43954c <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x9d4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X16, X9, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X24, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W2, W22, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X26, X30, W9,SXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
LDR D1, [X1, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X28, X10, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W9, W2, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X27, X28, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FNEG D16, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D16, [X10, X26]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP W22, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 43954c <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x9d4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W9, 4394bc <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x9cbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W7, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W8, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 439380 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x9b80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4393d4 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x9bd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	update_halo_kernel._omp_fn.0
Source file and lines	update_halo_kernel.f90:426-430
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90:426-430.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90:426,430.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.00 to 0.83 cycles (6.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 19% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.00 to 0.84 cycles (5.93x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	5.00	5.00	5.00	5.00	0.50	0.50	0.50	0.50	0.83	0.50	0.67	0.00	0.00
cycles	3.00	3.00	5.00	5.00	5.00	5.00	0.50	0.50	0.50	0.50	0.83	0.50	0.67	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.63
Overall L1	5.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

1% of peak load performance is reached (1.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.60 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 439380

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
CMP W17, W23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.CC 439e08 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0xa608>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X27, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X12, X1, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
MOVZ X11, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
ADD W9, W14, W25	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W15, W22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.EQ 43954c <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x9d4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X16, X9, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X24, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X13, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W2, W22, W9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X26, X30, W9,SXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50
LDR D1, [X1, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
ADD X28, X10, X26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X0, X16, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
AND W9, W2, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB X27, X28, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
FNEG D16, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
STR D16, [X10, X26]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50
CMP W22, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LT 43954c <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x9d4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W9, 4394bc <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x9cbc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W7, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W8, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 439380 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x9b80>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 4393d4 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x9bd4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code