OV - exec - Loop 49

	Loop Id: 49	Module: exec	Source: PdV_kernel.f90-pp.f90:77-99 [...]	Coverage: 6.74%

0x4199c0 UBFM	X13, X11, #61, #60

0x4199c4 ADD	X14, X7, X13

0x4199c8 ADD	X15, X25, X13

0x4199cc ADD	X18, X24, X13

0x4199d0 LD1D	{Z18.D}, P0/Z, [X14, MUL VL]    [15]

0x4199d4 LD1D	{Z19.D}, P0/Z, [X15, MUL VL]    [9]

0x4199d8 FADD	Z18.D, Z18.D, Z19.D

0x4199dc LD1D	{Z19.D}, P0/Z, [X18, MUL VL]    [1]

0x4199e0 LD1D	{Z20.D}, P0/Z, [X15, X19,LSL #3]    [10]

0x4199e4 FADD	Z18.D, Z18.D, Z18.D

0x4199e8 FMUL	Z18.D, Z18.D, Z19.D

0x4199ec LD1D	{Z19.D}, P0/Z, [X14, X19,LSL #3]    [2]

0x4199f0 ADD	X14, X23, X13

0x4199f4 ADD	X13, X22, X13

0x4199f8 FMUL	Z18.D, Z18.D, Z7.D

0x4199fc FADD	Z19.D, Z19.D, Z20.D

0x419a00 LD1D	{Z20.D}, P0/Z, [X18, X19,LSL #3]    [13]

0x419a04 FMUL	Z18.D, Z5.D, Z18.D

0x419a08 FADD	Z19.D, Z19.D, Z19.D

0x419a0c FMUL	Z18.D, P0/M, Z18.D, #0

0x419a10 FMUL	Z19.D, Z20.D, Z19.D

0x419a14 LD1D	{Z20.D}, P0/Z, [X14, X19,LSL #3]    [8]

0x419a18 LD1D	{Z21.D}, P0/Z, [X14, MUL VL]    [14]

0x419a1c FMUL	Z19.D, Z19.D, Z7.D

0x419a20 FADD	Z20.D, Z20.D, Z21.D

0x419a24 LD1D	{Z21.D}, P0/Z, [X1, X11,LSL #3]    [16]

0x419a28 FMUL	Z19.D, Z5.D, Z19.D

0x419a2c FADD	Z20.D, Z20.D, Z20.D

0x419a30 FNMLS	Z18.D, P0/M, Z19.D, Z16.D

0x419a34 FMUL	Z20.D, Z20.D, Z21.D

0x419a38 LD1D	{Z21.D}, P0/Z, [X13, X19,LSL #3]    [18]

0x419a3c LD1D	{Z22.D}, P0/Z, [X13, MUL VL]    [4]

0x419a40 LD1D	{Z23.D}, P0/Z, [X29, X11,LSL #3]    [11]

0x419a44 LD1D	{Z19.D}, P0/Z, [X17, X11,LSL #3]    [7]

0x419a48 FMUL	Z20.D, Z20.D, Z7.D

0x419a4c FADD	Z21.D, Z21.D, Z22.D

0x419a50 LD1D	{Z22.D}, P0/Z, [X21, X11,LSL #3]    [5]

0x419a54 FMUL	Z20.D, Z5.D, Z20.D

0x419a58 FADD	Z21.D, Z21.D, Z21.D

0x419a5c FMUL	Z21.D, Z22.D, Z21.D

0x419a60 LD1D	{Z22.D}, P0/Z, [X30, X11,LSL #3]    [19]

0x419a64 FMUL	Z21.D, Z21.D, Z7.D

0x419a68 FMUL	Z21.D, Z5.D, Z21.D

0x419a6c FDIV	Z23.D, P0/M, Z23.D, Z22.D

0x419a70 FMLA	Z18.D, P0/M, Z21.D, Z16.D

0x419a74 LD1D	{Z21.D}, P0/Z, [X16, X11,LSL #3]    [12]

0x419a78 FMLS	Z18.D, P0/M, Z20.D, Z16.D

0x419a7c FDIV	Z21.D, P0/M, Z21.D, Z22.D

0x419a80 FADD	Z20.D, Z19.D, Z18.D

0x419a84 FDIVR	Z20.D, P0/M, Z20.D, Z19.D

0x419a88 FDIVR	Z19.D, P0/M, Z19.D, Z17.D

0x419a8c FADD	Z21.D, Z21.D, Z23.D

0x419a90 FMUL	Z18.D, Z18.D, Z21.D

0x419a94 LD1D	{Z21.D}, P0/Z, [X28, X11,LSL #3]    [17]

0x419a98 FMSB	Z18.D, P0/M, Z19.D, Z21.D

0x419a9c ST1D	{Z18.D}, P0, [X27, X11,LSL #3]    [3]

0x419aa0 FMUL	Z18.D, Z22.D, Z20.D

0x419aa4 ST1D	{Z18.D}, P0, [X26, X11,LSL #3]    [6]

0x419aa8 ADD	X11, X11, X20

0x419aac CMP	X12, X11

0x419ab0 B.NE	4199c0

/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/PdV_kernel.f90-pp.f90: 77 - 99

--------------------------------------------------------------------------------

77: # 77 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

78:           left_flux=  (xarea(j  ,k  )*(xvel0(j  ,k  )+xvel0(j  ,k+1)                     &

79:             +xvel0(j  ,k  )+xvel0(j  ,k+1)))*0.25_8*dt*0.5

80:           right_flux= (xarea(j+1,k  )*(xvel0(j+1,k  )+xvel0(j+1,k+1)                     &

81:             +xvel0(j+1,k  )+xvel0(j+1,k+1)))*0.25_8*dt*0.5

82:           bottom_flux=(yarea(j  ,k  )*(yvel0(j  ,k  )+yvel0(j+1,k  )                     &

83:             +yvel0(j  ,k  )+yvel0(j+1,k  )))*0.25_8*dt*0.5

84:           top_flux=   (yarea(j  ,k+1)*(yvel0(j  ,k+1)+yvel0(j+1,k+1)                     &

85:             +yvel0(j  ,k+1)+yvel0(j+1,k+1)))*0.25_8*dt*0.5

86:           total_flux=right_flux-left_flux+top_flux-bottom_flux

87: # 87 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

[...]

93:

94:           recip_volume=1.0/volume(j,k)

95: # 95 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

96:           energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume

97: # 97 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

98:           energy1(j,k)=energy0(j,k)-energy_change

99: # 99 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	P6, P7,
Function	__nv_pdv_kernel_module_pdv_kernel__F1L67_1_
Source	PdV_kernel.f90-pp.f90:77-87,PdV_kernel.f90-pp.f90:93-99
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	16.50
CQA cycles if no scalar integer	16.50
CQA cycles if FP arith vectorized	16.50
CQA cycles if fully vectorized	16.50
Front-end cycles	7.63
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	16.50
P6 cycles	16.50
P7 cycles	14.50
P8 cycles	14.50
P9 cycles	9.50
P10 cycles	9.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	4.00 - 2.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	61.00
Nb uops	61.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	8.97
Nb FLOP add-sub	40.00
Nb FLOP mul	60.00
Nb FLOP fma	16.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	36.85
Bytes prefetched	0.00
Bytes loaded	544.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14
Bottlenecks	P6, P7,
Function	__nv_pdv_kernel_module_pdv_kernel__F1L67_1_
Source	PdV_kernel.f90-pp.f90:77-87,PdV_kernel.f90-pp.f90:93-99
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	16.50
CQA cycles if no scalar integer	16.50
CQA cycles if FP arith vectorized	16.50
CQA cycles if fully vectorized	16.50
Front-end cycles	7.63
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	2.00
P2 cycles	2.00
P3 cycles	2.00
P4 cycles	2.00
P5 cycles	16.50
P6 cycles	16.50
P7 cycles	14.50
P8 cycles	14.50
P9 cycles	9.50
P10 cycles	9.50
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	4.00 - 2.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	61.00
Nb uops	61.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	8.97
Nb FLOP add-sub	40.00
Nb FLOP mul	60.00
Nb FLOP fma	16.00
Nb FLOP div	16.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	36.85
Bytes prefetched	0.00
Bytes loaded	544.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__nv_pdv_kernel_module_pdv_kernel__F1L67_1_
Source file and lines	PdV_kernel.f90-pp.f90:77-99
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/PdV_kernel.f90-pp.f90:77-87,93-99.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 148 FP arithmetical operations:

56: addition or subtraction (16 inside FMA instructions)
76: multiply (16 inside FMA instructions)
16: divide

The binary loop is loading 544 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.24 FP operations per loaded or stored byte.

General properties

nb instructions	61
loop length	244
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.00	2.00	2.00	2.00	16.50	16.50	1.00	1.00	9.50	9.50	0.00	0.00	0.00
cycles	0.50	0.50	2.00	2.00	2.00	2.00	16.50	16.50	14.50	14.50	9.50	9.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	4.00-2.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.63
Data deps.	1.00
Overall L1	16.50

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.50 cycles. At this rate:

34% of peak load performance is reached (32.97 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (3.88 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4199c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
UBFM X13, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X14, X7, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X15, X25, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X18, X24, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LD1D {Z18.D}, P0/Z, [X14, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z19.D}, P0/Z, [X15, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z18.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z19.D}, P0/Z, [X18, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P0/Z, [X15, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z18.D, Z18.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z18.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z19.D}, P0/Z, [X14, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X14, X23, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X13, X22, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMUL Z18.D, Z18.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z19.D, Z19.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z20.D}, P0/Z, [X18, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z18.D, Z5.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z19.D, Z19.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z18.D, P0/M, Z18.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z19.D, Z20.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z20.D}, P0/Z, [X14, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z21.D}, P0/Z, [X14, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z19.D, Z19.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z20.D, Z20.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z21.D}, P0/Z, [X1, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z19.D, Z5.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z20.D, Z20.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FNMLS Z18.D, P0/M, Z19.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z20.D, Z20.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z21.D}, P0/Z, [X13, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z22.D}, P0/Z, [X13, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P0/Z, [X29, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z19.D}, P0/Z, [X17, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z20.D, Z20.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z21.D, Z21.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z22.D}, P0/Z, [X21, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z20.D, Z5.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z21.D, Z21.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z21.D, Z22.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z22.D}, P0/Z, [X30, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z21.D, Z21.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z21.D, Z5.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIV Z23.D, P0/M, Z23.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMLA Z18.D, P0/M, Z21.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1D {Z21.D}, P0/Z, [X16, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLS Z18.D, P0/M, Z20.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FDIV Z21.D, P0/M, Z21.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FADD Z20.D, Z19.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIVR Z20.D, P0/M, Z20.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIVR Z19.D, P0/M, Z19.D, Z17.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FADD Z21.D, Z21.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z18.D, Z18.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z21.D}, P0/Z, [X28, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMSB Z18.D, P0/M, Z19.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z18.D}, P0, [X27, X11,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
FMUL Z18.D, Z22.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z18.D}, P0, [X26, X11,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X11, X11, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
B.NE 4199c0 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x8a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	__nv_pdv_kernel_module_pdv_kernel__F1L67_1_
Source file and lines	PdV_kernel.f90-pp.f90:77-99
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All VPU instructions are used in vector version (process two or more data elements in vector registers).

FMA

Detected 16 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 148 FP arithmetical operations:

56: addition or subtraction (16 inside FMA instructions)
76: multiply (16 inside FMA instructions)
16: divide

The binary loop is loading 544 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.24 FP operations per loaded or stored byte.

General properties

nb instructions	61
loop length	244
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.00	2.00	2.00	2.00	16.50	16.50	1.00	1.00	9.50	9.50	0.00	0.00	0.00
cycles	0.50	0.50	2.00	2.00	2.00	2.00	16.50	16.50	14.50	14.50	9.50	9.50	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	4.00-2.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.63
Data deps.	1.00
Overall L1	16.50

Vectorization ratios

INT

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.50 cycles. At this rate:

34% of peak load performance is reached (32.97 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (3.88 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4199c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
UBFM X13, X11, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X14, X7, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X15, X25, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X18, X24, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LD1D {Z18.D}, P0/Z, [X14, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z19.D}, P0/Z, [X15, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z18.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z19.D}, P0/Z, [X18, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P0/Z, [X15, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z18.D, Z18.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z18.D, Z18.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z19.D}, P0/Z, [X14, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
ADD X14, X23, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD X13, X22, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
FMUL Z18.D, Z18.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z19.D, Z19.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z20.D}, P0/Z, [X18, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z18.D, Z5.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z19.D, Z19.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z18.D, P0/M, Z18.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z19.D, Z20.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z20.D}, P0/Z, [X14, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z21.D}, P0/Z, [X14, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z19.D, Z19.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z20.D, Z20.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z21.D}, P0/Z, [X1, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z19.D, Z5.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z20.D, Z20.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FNMLS Z18.D, P0/M, Z19.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FMUL Z20.D, Z20.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z21.D}, P0/Z, [X13, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z22.D}, P0/Z, [X13, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P0/Z, [X29, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z19.D}, P0/Z, [X17, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z20.D, Z20.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z21.D, Z21.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
LD1D {Z22.D}, P0/Z, [X21, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z20.D, Z5.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z21.D, Z21.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z21.D, Z22.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z22.D}, P0/Z, [X30, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z21.D, Z21.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FMUL Z21.D, Z5.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FDIV Z23.D, P0/M, Z23.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FMLA Z18.D, P0/M, Z21.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
LD1D {Z21.D}, P0/Z, [X16, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMLS Z18.D, P0/M, Z20.D, Z16.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
FDIV Z21.D, P0/M, Z21.D, Z22.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FADD Z20.D, Z19.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FDIVR Z20.D, P0/M, Z20.D, Z19.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FDIVR Z19.D, P0/M, Z19.D, Z17.D	1	0	0	0	0	0	0	1	0	0	0	0	0	7-15	1-0.50
FADD Z21.D, Z21.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z18.D, Z18.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
LD1D {Z21.D}, P0/Z, [X28, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMSB Z18.D, P0/M, Z19.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
ST1D {Z18.D}, P0, [X27, X11,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
FMUL Z18.D, Z22.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z18.D}, P0, [X26, X11,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X11, X11, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP X12, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.33
B.NE 4199c0 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x8a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code