OV - exec - Loop 48

	Loop Id: 48	Module: exec	Source: PdV_kernel.f90-pp.f90:73-102 [...]	Coverage: 0.01%

0x419920 LDP	X8, X9, [SP, #216]

0x419924 SUBS	W4, W4, #1

0x419928 ADD	X22, X22, X8

0x41992c ADD	X7, X7, X8

0x419930 ADD	X23, X23, X8

0x419934 ADD	X24, X24, X8

0x419938 ADD	X25, X25, X8

0x41993c LDR	X8, [SP, #208]

0x419940 ADD	X2, X2, X9

0x419944 ADD	X6, X6, X9

0x419948 ADD	X26, X26, X8

0x41994c ADD	X27, X27, X8

0x419950 ADD	X28, X28, X8

0x419954 ADD	X29, X29, X8

0x419958 ADD	X30, X30, X8

0x41995c ADD	X16, X16, X8

0x419960 ADD	X17, X17, X8

0x419964 ADD	X1, X1, X8

0x419968 ADD	X21, X21, X8

0x41996c LDR	X8, [SP, #232]

0x419970 ADD	X0, X0, X8

0x419974 ADD	X5, X5, X8

0x419978 B.LE	419c20

0x41997c LDR	X8, [SP, #240]

0x419980 LDR	W9, [SP, #248]

0x419984 CMP	X8, X20

0x419988 ORR	X8, XZR, X3

0x41998c B.CC	419ab8

0x419990 LDR	X9, [SP, #240]

0x419994 ORR	X11, XZR, XZR

0x419998 UDIV	X8, X9, X20

0x41999c MADD	X12, X8, X20, XZR

0x4199a0 SUB	X10, X9, X12

0x4199a4 LDR	W9, [SP, #248]

0x4199a8 ADD	X8, X12, X3

0x4199ac SUB	W9, W9, W12

0x4199b0 HINT	#0

0x4199b4 HINT	#0

0x4199b8 HINT	#0

0x4199bc HINT	#0

  (49) 0x4199c0 UBFM	X13, X11, #61, #60

  (49) 0x4199c4 ADD	X14, X7, X13

  (49) 0x4199c8 ADD	X15, X25, X13

  (49) 0x4199cc ADD	X18, X24, X13

  (49) 0x4199d0 LD1D	{Z18.D}, P0/Z, [X14, MUL VL]

  (49) 0x4199d4 LD1D	{Z19.D}, P0/Z, [X15, MUL VL]

  (49) 0x4199d8 FADD	Z18.D, Z18.D, Z19.D

  (49) 0x4199dc LD1D	{Z19.D}, P0/Z, [X18, MUL VL]

  (49) 0x4199e0 LD1D	{Z20.D}, P0/Z, [X15, X19,LSL #3]

  (49) 0x4199e4 FADD	Z18.D, Z18.D, Z18.D

  (49) 0x4199e8 FMUL	Z18.D, Z18.D, Z19.D

  (49) 0x4199ec LD1D	{Z19.D}, P0/Z, [X14, X19,LSL #3]

  (49) 0x4199f0 ADD	X14, X23, X13

  (49) 0x4199f4 ADD	X13, X22, X13

  (49) 0x4199f8 FMUL	Z18.D, Z18.D, Z7.D

  (49) 0x4199fc FADD	Z19.D, Z19.D, Z20.D

  (49) 0x419a00 LD1D	{Z20.D}, P0/Z, [X18, X19,LSL #3]

  (49) 0x419a04 FMUL	Z18.D, Z5.D, Z18.D

  (49) 0x419a08 FADD	Z19.D, Z19.D, Z19.D

  (49) 0x419a0c FMUL	Z18.D, P0/M, Z18.D, #0

  (49) 0x419a10 FMUL	Z19.D, Z20.D, Z19.D

  (49) 0x419a14 LD1D	{Z20.D}, P0/Z, [X14, X19,LSL #3]

  (49) 0x419a18 LD1D	{Z21.D}, P0/Z, [X14, MUL VL]

  (49) 0x419a1c FMUL	Z19.D, Z19.D, Z7.D

  (49) 0x419a20 FADD	Z20.D, Z20.D, Z21.D

  (49) 0x419a24 LD1D	{Z21.D}, P0/Z, [X1, X11,LSL #3]

  (49) 0x419a28 FMUL	Z19.D, Z5.D, Z19.D

  (49) 0x419a2c FADD	Z20.D, Z20.D, Z20.D

  (49) 0x419a30 FNMLS	Z18.D, P0/M, Z19.D, Z16.D

  (49) 0x419a34 FMUL	Z20.D, Z20.D, Z21.D

  (49) 0x419a38 LD1D	{Z21.D}, P0/Z, [X13, X19,LSL #3]

  (49) 0x419a3c LD1D	{Z22.D}, P0/Z, [X13, MUL VL]

  (49) 0x419a40 LD1D	{Z23.D}, P0/Z, [X29, X11,LSL #3]

  (49) 0x419a44 LD1D	{Z19.D}, P0/Z, [X17, X11,LSL #3]

  (49) 0x419a48 FMUL	Z20.D, Z20.D, Z7.D

  (49) 0x419a4c FADD	Z21.D, Z21.D, Z22.D

  (49) 0x419a50 LD1D	{Z22.D}, P0/Z, [X21, X11,LSL #3]

  (49) 0x419a54 FMUL	Z20.D, Z5.D, Z20.D

  (49) 0x419a58 FADD	Z21.D, Z21.D, Z21.D

  (49) 0x419a5c FMUL	Z21.D, Z22.D, Z21.D

  (49) 0x419a60 LD1D	{Z22.D}, P0/Z, [X30, X11,LSL #3]

  (49) 0x419a64 FMUL	Z21.D, Z21.D, Z7.D

  (49) 0x419a68 FMUL	Z21.D, Z5.D, Z21.D

  (49) 0x419a6c FDIV	Z23.D, P0/M, Z23.D, Z22.D

  (49) 0x419a70 FMLA	Z18.D, P0/M, Z21.D, Z16.D

  (49) 0x419a74 LD1D	{Z21.D}, P0/Z, [X16, X11,LSL #3]

  (49) 0x419a78 FMLS	Z18.D, P0/M, Z20.D, Z16.D

  (49) 0x419a7c FDIV	Z21.D, P0/M, Z21.D, Z22.D

  (49) 0x419a80 FADD	Z20.D, Z19.D, Z18.D

  (49) 0x419a84 FDIVR	Z20.D, P0/M, Z20.D, Z19.D

  (49) 0x419a88 FDIVR	Z19.D, P0/M, Z19.D, Z17.D

  (49) 0x419a8c FADD	Z21.D, Z21.D, Z23.D

  (49) 0x419a90 FMUL	Z18.D, Z18.D, Z21.D

  (49) 0x419a94 LD1D	{Z21.D}, P0/Z, [X28, X11,LSL #3]

  (49) 0x419a98 FMSB	Z18.D, P0/M, Z19.D, Z21.D

  (49) 0x419a9c ST1D	{Z18.D}, P0, [X27, X11,LSL #3]

  (49) 0x419aa0 FMUL	Z18.D, Z22.D, Z20.D

  (49) 0x419aa4 ST1D	{Z18.D}, P0, [X26, X11,LSL #3]

  (49) 0x419aa8 ADD	X11, X11, X20

  (49) 0x419aac CMP	X12, X11

  (49) 0x419ab0 B.NE	4199c0

0x419ab4 CBZ	X10, 419920

0x419ab8 ADD	W11, W9, #1

0x419abc STP	X2, X0, [SP, #280]

0x419ac0 ADD	X9, X8, X0

0x419ac4 LDP	X20, X0, [SP, #184]

0x419ac8 ADD	X12, X8, X2

0x419acc STP	X6, X5, [SP, #264]

0x419ad0 UBFM	X9, X9, #61, #60

0x419ad4 ADD	X13, X8, X5

0x419ad8 UBFM	X18, X13, #61, #60

0x419adc STR	W4, [SP, #300]

0x419ae0 ADD	X8, X8, X6

0x419ae4 STR	X7, [SP, #256]

0x419ae8 UBFM	X7, X8, #61, #60

0x419aec ORR	X10, XZR, XZR

0x419af0 ADD	X15, X20, X12,LSL #3

0x419af4 LDP	X12, X8, [SP, #112]

0x419af8 ADD	X14, X0, X9

0x419afc ADD	X8, X8, X7

0x419b00 ADD	X2, X12, X9

0x419b04 LDP	X5, X9, [SP, #168]

0x419b08 ADD	X12, X12, X18

0x419b0c ADD	X13, X9, X18

0x419b10 ADD	X9, X0, X18

0x419b14 LDP	X18, X4, [SP, #136]

0x419b18 LDP	X0, X3, [SP, #152]

0x419b1c ADD	X5, X5, X7

0x419b20 ADD	X6, X18, X7

0x419b24 LDR	X18, [SP, #128]

0x419b28 ADD	X0, X0, X7

0x419b2c ADD	X3, X3, X7

0x419b30 ADD	X4, X4, X7

0x419b34 ADD	X18, X18, X7

0x419b38 ADD	X7, X20, X7

0x419b3c HINT	#0

  (47) 0x419b40 LDR	Q18, [X14, X10]

  (47) 0x419b44 LDR	Q19, [X9, X10]

  (47) 0x419b48 ADD	X20, X12, X10

  (47) 0x419b4c LDR	D22, [X3, X10]

  (47) 0x419b50 SUB	W11, W11, #1

  (47) 0x419b54 CMP	W11, #1

  (47) 0x419b58 LDR	D23, [X0, X10]

  (47) 0x419b5c FDIV	D23, D23, D22

  (47) 0x419b60 FADD	V18.2D, V18.2D, V19.2D

  (47) 0x419b64 LDR	Q19, [X13, X10]

  (47) 0x419b68 FADD	V18.2D, V18.2D, V18.2D

  (47) 0x419b6c FMUL	V18.2D, V19.2D, V18.2D

  (47) 0x419b70 LDP	D20, D19, [X20, #1016]

  (47) 0x419b74 ADD	X20, X2, X10

  (47) 0x419b78 FMUL	V18.2D, V18.2D, V1.2D

  (47) 0x419b7c FADD	D19, D19, D20

  (47) 0x419b80 LDR	D20, [X7, X10]

  (47) 0x419b84 FMUL	V18.2D, V18.2D, V0.D[0]

  (47) 0x419b88 FADD	D19, D19, D19

  (47) 0x419b8c FMUL	V18.2D, V18.2D, V2.2D

  (47) 0x419b90 FMUL	D19, D19, D20

  (47) 0x419b94 LDP	D21, D20, [X20, #1016]

  (47) 0x419b98 FMUL	D19, D19, D3

  (47) 0x419b9c FADD	D20, D20, D21

  (47) 0x419ba0 LDR	D21, [X15, X10]

  (47) 0x419ba4 FMUL	D19, D0, D19

  (47) 0x419ba8 FADD	D20, D20, D20

  (47) 0x419bac FMUL	D20, D21, D20

  (47) 0x419bb0 DUP	V21.2D, V18.D[1]

  (47) 0x419bb4 FSUB	V18.2D, V21.2D, V18.2D

  (47) 0x419bb8 LDR	D21, [X4, X10]

  (47) 0x419bbc FMUL	D20, D20, D3

  (47) 0x419bc0 FMUL	D20, D0, D20

  (47) 0x419bc4 FDIV	D21, D21, D22

  (47) 0x419bc8 FMADD	D18, D20, D4, D18

  (47) 0x419bcc FMSUB	D18, D19, D4, D18

  (47) 0x419bd0 LDR	D19, [X5, X10]

  (47) 0x419bd4 FADD	D20, D19, D18

  (47) 0x419bd8 FDIV	D20, D19, D20

  (47) 0x419bdc FDIV	D19, D6, D19

  (47) 0x419be0 FADD	D21, D21, D23

  (47) 0x419be4 FMUL	D18, D18, D21

  (47) 0x419be8 LDR	D21, [X18, X10]

  (47) 0x419bec FMADD	D18, D19, D18, D21

  (47) 0x419bf0 STR	D18, [X6, X10]

  (47) 0x419bf4 FMUL	D18, D22, D20

  (47) 0x419bf8 STR	D18, [X8, X10]

  (47) 0x419bfc ADD	X10, X10, #8

  (47) 0x419c00 B.HI	419b40

0x419c04 LDR	X3, [SP, #200]

0x419c08 LDR	W4, [SP, #300]

0x419c0c LDP	X2, X0, [SP, #280]

0x419c10 CNTD	X20, ALL

0x419c14 LDP	X6, X5, [SP, #264]

0x419c18 LDR	X7, [SP, #256]

0x419c1c B	419920

/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/PdV_kernel.f90-pp.f90: 73 - 102

--------------------------------------------------------------------------------

73:       !$OMP            energy_change,recip_volume,volume_change_s)

74:       DO k=y_min,y_max

75:       !$OMP SIMD

76:         DO j=x_min,x_max

77: # 77 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

78:           left_flux=  (xarea(j  ,k  )*(xvel0(j  ,k  )+xvel0(j  ,k+1)                     &

79:             +xvel0(j  ,k  )+xvel0(j  ,k+1)))*0.25_8*dt*0.5

80:           right_flux= (xarea(j+1,k  )*(xvel0(j+1,k  )+xvel0(j+1,k+1)                     &

81:             +xvel0(j+1,k  )+xvel0(j+1,k+1)))*0.25_8*dt*0.5

82:           bottom_flux=(yarea(j  ,k  )*(yvel0(j  ,k  )+yvel0(j+1,k  )                     &

83:             +yvel0(j  ,k  )+yvel0(j+1,k  )))*0.25_8*dt*0.5

84:           top_flux=   (yarea(j  ,k+1)*(yvel0(j  ,k+1)+yvel0(j+1,k+1)                     &

85:             +yvel0(j  ,k+1)+yvel0(j+1,k+1)))*0.25_8*dt*0.5

86:           total_flux=right_flux-left_flux+top_flux-bottom_flux

87: # 87 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

[...]

93:

94:           recip_volume=1.0/volume(j,k)

95: # 95 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

96:           energy_change=(pressure(j,k)/density0(j,k)+viscosity(j,k)/density0(j,k))*total_flux*recip_volume

97: # 97 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

98:           energy1(j,k)=energy0(j,k)-energy_change

99: # 99 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

100:           density1(j,k)=density0(j,k)*volume_change_s

101: # 101 "/home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/PdV_kernel.f90"

102:         ENDDO

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.39
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.32
Bottlenecks	P2, P3, P4, P5,
Function	__nv_pdv_kernel_module_pdv_kernel__F1L67_1_
Source	PdV_kernel.f90-pp.f90:73-75,PdV_kernel.f90-pp.f90:101-102
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.75
CQA cycles if no scalar integer	12.75
CQA cycles if FP arith vectorized	12.75
CQA cycles if fully vectorized	2.91
Front-end cycles	9.63
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	12.75
P2 cycles	12.75
P3 cycles	12.75
P4 cycles	12.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	7.33
P10 cycles	7.33
P11 cycles	7.33
P12 cycles	2.00
P13 cycles	2.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	82.00
Nb uops	77.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.82
Bytes prefetched	0.00
Bytes loaded	196.00
Bytes stored	44.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.17
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	24.04
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	25.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.39
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.32
Bottlenecks	P2, P3, P4, P5,
Function	__nv_pdv_kernel_module_pdv_kernel__F1L67_1_
Source	PdV_kernel.f90-pp.f90:73-75,PdV_kernel.f90-pp.f90:101-102
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.75
CQA cycles if no scalar integer	12.75
CQA cycles if FP arith vectorized	12.75
CQA cycles if fully vectorized	2.91
Front-end cycles	9.63
DIV/SQRT cycles	2.00
P0 cycles	2.00
P1 cycles	12.75
P2 cycles	12.75
P3 cycles	12.75
P4 cycles	12.75
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	7.33
P10 cycles	7.33
P11 cycles	7.33
P12 cycles	2.00
P13 cycles	2.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	82.00
Nb uops	77.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.82
Bytes prefetched	0.00
Bytes loaded	196.00
Bytes stored	44.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	0.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	0.00
Vector-efficiency ratio all	24.17
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	24.04
Vector-efficiency ratio fma	25.00
Vector-efficiency ratio div_sqrt	25.00
Vector-efficiency ratio other	25.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__nv_pdv_kernel_module_pdv_kernel__F1L67_1_
Source file and lines	PdV_kernel.f90-pp.f90:73-102
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/PdV_kernel.f90-pp.f90:73-87,93-102.

Analyzed code is defined in /home/hbollore/qaas-runs/170-308-3604/intel/CloverLeafFC/build/build/CMakeFiles/clover_leaf.dir/CloverLeaf_ref/kernels/PdV_kernel.f90-pp.f90:73-75,101-102.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 24% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 12.75 to 2.91 cycles (4.39x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 196 bytes. The binary loop is storing 44 bytes.

General properties

nb instructions	82
loop length	328
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	12.75	12.75	12.75	12.75	0.00	0.00	0.00	0.00	7.33	7.33	7.33	2.00	2.00
cycles	2.00	2.00	12.75	12.75	12.75	12.75	0.00	0.00	0.00	0.00	7.33	7.33	7.33	2.00	2.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	9.63
Overall L1	12.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.75 cycles. At this rate:

16% of peak load performance is reached (15.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (3.45 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 419920

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDP X8, X9, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUBS W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X22, X22, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X7, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X23, X23, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X24, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X25, X25, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X2, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X6, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X26, X26, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X27, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X28, X28, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X29, X29, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X30, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X16, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X17, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X21, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X5, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.LE 419c20 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0xb00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ORR X8, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.CC 419ab8 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x998>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X11, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UDIV X8, X9, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
MADD X12, X8, X20, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X10, X9, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W9, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X12, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W9, W9, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
CBZ X10, 419920 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x800>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W11, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X2, X0, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X9, X8, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X0, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X12, X8, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X6, X5, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X9, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X8, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X18, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W4, [SP, #300]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X8, X8, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X7, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X7, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X20, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X12, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X14, X0, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X12, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X5, X9, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X12, X12, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X9, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X0, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X18, X4, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X0, X3, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X5, X5, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X18, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X18, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X3, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X18, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X20, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
LDR X3, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W4, [SP, #300]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X2, X0, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CNTD X20, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDP X6, X5, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X7, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 419920 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x800>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	__nv_pdv_kernel_module_pdv_kernel__F1L67_1_
Source file and lines	PdV_kernel.f90-pp.f90:73-102
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 196 bytes. The binary loop is storing 44 bytes.

General properties

nb instructions	82
loop length	328
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

9.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.00	2.00	12.75	12.75	12.75	12.75	0.00	0.00	0.00	0.00	7.33	7.33	7.33	2.00	2.00
cycles	2.00	2.00	12.75	12.75	12.75	12.75	0.00	0.00	0.00	0.00	7.33	7.33	7.33	2.00	2.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	9.63
Overall L1	12.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	0%
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.75 cycles. At this rate:

16% of peak load performance is reached (15.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (3.45 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 419920

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDP X8, X9, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
SUBS W4, W4, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ADD X22, X22, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X7, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X23, X23, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X24, X24, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X25, X25, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X2, X2, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X6, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X26, X26, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X27, X27, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X28, X28, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X29, X29, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X30, X30, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X16, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X17, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X1, X1, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X21, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X8, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X5, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.LE 419c20 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0xb00>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X8, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W9, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP X8, X20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
ORR X8, XZR, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B.CC 419ab8 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x998>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X9, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X11, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UDIV X8, X9, X20	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	1-0.50
MADD X12, X8, X20, XZR	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
SUB X10, X9, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W9, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X12, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
SUB W9, W9, W12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
HINT #0
HINT #0
HINT #0
CBZ X10, 419920 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x800>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD W11, W9, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X2, X0, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X9, X8, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X20, X0, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X12, X8, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STP X6, X5, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X9, X9, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X8, X5	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
UBFM X18, X13, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR W4, [SP, #300]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
ADD X8, X8, X6	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
STR X7, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
UBFM X7, X8, #61, #60	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ORR X10, XZR, XZR	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X15, X20, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X12, X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X14, X0, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X12, X9	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X5, X9, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X12, X12, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X13, X9, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X0, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDP X18, X4, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDP X0, X3, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
ADD X5, X5, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X6, X18, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X18, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X0, X0, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X3, X3, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X18, X18, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X20, X7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
HINT #0
LDR X3, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR W4, [SP, #300]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDP X2, X0, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
CNTD X20, ALL	1	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1
LDP X6, X5, [SP, #264]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	1
LDR X7, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
B 419920 <__nv_pdv_kernel_module_pdv_kernel__F1L67_1_+0x800>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code