OV - exec - Loop 455

0x433dac CMP	W13, W15

0x433db0 B.CC	439e10

0x433db4 ADD	X28, X2, #8

0x433db8 ADD	X27, X2, X4

0x433dbc MOVZ	X22, #0

  (457) 0x433dc0 LD1D	{Z2.D}, P2/Z, [X28, X22,LSL #3]

  (457) 0x433dc4 ORR	W23, WZR, W22

  (457) 0x433dc8 ADD	W24, W7, W22

  (457) 0x433dcc REV	Z3.D, Z2.D

  (457) 0x433dd0 ADD	X22, X22, X8

  (457) 0x433dd4 ST1D	{Z3.D}, P2, [X27, MUL VL]

  (457) 0x433dd8 ADD	X27, X27, X4

  (457) 0x433ddc CMP	W9, W22

  (457) 0x433de0 B.CS	433dc0

0x433de4 ADD	W26, W23, W17

0x433de8 CMP	W24, W21

0x433dec B.EQ	433f28

0x433df0 SBFM	X18, X26, #0, #31

0x433df4 ADD	X1, X16, X2

0x433df8 SUB	W30, W21, W26

0x433dfc ADD	X6, X1, #8

0x433e00 SUB	X3, X6, W26,SXTW #3

0x433e04 LDR	D4, [X2, X18,LSL #3]

0x433e08 ADD	X25, X12, X3

0x433e0c ADD	X0, X18, #1

0x433e10 AND	W5, W30, #128

0x433e14 SUB	X26, X25, #8

0x433e18 STR	D4, [X12, X3]

0x433e1c CMP	W21, W0

0x433e20 B.LT	433f28

0x433e24 CBZ	W5, 433eb8

  (456) 0x433eb8 LDR	D1, [X2, X0,LSL #3]

  (456) 0x433ebc ORR	X28, XZR, X26

  (456) 0x433ec0 ADD	X27, X0, #1

  (456) 0x433ec4 ADD	X24, X0, #2

  (456) 0x433ec8 ADD	X23, X0, #3

  (456) 0x433ecc ADD	X22, X0, #4

  (456) 0x433ed0 ADD	X18, X0, #5

  (456) 0x433ed4 ADD	X1, X0, #6

  (456) 0x433ed8 ADD	X6, X0, #7

  (456) 0x433edc ADD	X0, X0, #8

  (456) 0x433ee0 SUB	X26, X26, #64

  (456) 0x433ee4 STR	D1, [X28], #504

  (456) 0x433ee8 LDR	D20, [X2, X27,LSL #3]

  (456) 0x433eec STR	D20, [X26, #56]

  (456) 0x433ef0 LDR	D21, [X2, X24,LSL #3]

  (456) 0x433ef4 STUR	D21, [X28, #504]

  (456) 0x433ef8 LDR	D22, [X2, X23,LSL #3]

  (456) 0x433efc STR	D22, [X26, #40]

  (456) 0x433f00 LDR	D23, [X2, X22,LSL #3]

  (456) 0x433f04 STR	D23, [X26, #32]

  (456) 0x433f08 LDR	D24, [X2, X18,LSL #3]

  (456) 0x433f0c STR	D24, [X26, #24]

  (456) 0x433f10 LDR	D25, [X2, X1,LSL #3]

  (456) 0x433f14 STR	D25, [X26, #16]

  (456) 0x433f18 LDR	D26, [X2, X6,LSL #3]

  (456) 0x433f1c STR	D26, [X26, #8]

  (456) 0x433f20 CMP	W21, W0

  (456) 0x433f24 B.GE	433eb8

0x433f28 ADD	W10, W10, #1

0x433f2c ADD	X2, X2, X14

0x433f30 CMP	W11, W10

0x433f34 B.GT	433dac

0x439e10 MOVZ	W26, #1

0x439e14 B	433df0

/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90: 688 - 692

--------------------------------------------------------------------------------

688:         !$OMP DO

689:         DO k=y_min-depth,y_max+1+depth

690:         !$OMP SIMD

691:           DO j=1,depth

692:             vol_flux_y(1-j,k)=vol_flux_y(1+j,k)

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	update_halo_kernel	update_halo_kernel.f90:754	exec
○	update_halo	update_halo.f90:78	exec
○	advection	advection.f90:56	exec
○	hydro	hydro.f90:64	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec

Path /

Metric	Value
CQA speedup if no scalar integer	6.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.93
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.43
Bottlenecks	P2, P3, P4, P5,
Function	update_halo_kernel._omp_fn.0
Source	update_halo_kernel.f90:688-688,update_halo_kernel.f90:692-692
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	0.83
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	0.84
Front-end cycles	3.50
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	5.00
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	5.00
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.83
P10 cycles	0.50
P11 cycles	0.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	28.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.20
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	19.85
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	22.22
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.58

Metric	Value
CQA speedup if no scalar integer	6.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.93
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.43
Bottlenecks	P2, P3, P4, P5,
Function	update_halo_kernel._omp_fn.0
Source	update_halo_kernel.f90:688-688,update_halo_kernel.f90:692-692
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.00
CQA cycles if no scalar integer	0.83
CQA cycles if FP arith vectorized	5.00
CQA cycles if fully vectorized	0.84
Front-end cycles	3.50
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	5.00
P2 cycles	5.00
P3 cycles	5.00
P4 cycles	5.00
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.83
P10 cycles	0.50
P11 cycles	0.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	28.00
Nb uops	28.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.20
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	19.85
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	22.22
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	14.58

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	update_halo_kernel._omp_fn.0
Source file and lines	update_halo_kernel.f90:688-692
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90:688-692.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90:688,692.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.00 to 0.83 cycles (6.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 19% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.00 to 0.84 cycles (5.93x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	28
loop length	112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	5.00	5.00	5.00	5.00	0.50	0.50	0.00	0.00	0.83	0.50	0.67	0.00	0.00
cycles	3.00	3.00	5.00	5.00	5.00	5.00	0.50	0.50	0.00	0.00	0.83	0.50	0.67	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.50
Overall L1	5.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

1% of peak load performance is reached (1.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.60 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 433dac

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
CMP W13, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 439e10 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0xa610>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X28, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X27, X2, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ X22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W26, W23, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W24, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 433f28 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x4728>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X18, X26, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X16, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W30, W21, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X6, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X3, X6, W26,SXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LDR D4, [X2, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X25, X12, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
AND W5, W30, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X26, X25, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D4, [X12, X3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
CMP W21, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 433f28 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x4728>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W5, 433eb8 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x46b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD W10, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X2, X2, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W11, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 433dac <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x45ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 433df0 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x45f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	update_halo_kernel._omp_fn.0
Source file and lines	update_halo_kernel.f90:688-692
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90:688-692.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90:688,692.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.00 to 0.83 cycles (6.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 19% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.00 to 0.84 cycles (5.93x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	28
loop length	112
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	5.00	5.00	5.00	5.00	0.50	0.50	0.00	0.00	0.83	0.50	0.67	0.00	0.00
cycles	3.00	3.00	5.00	5.00	5.00	5.00	0.50	0.50	0.00	0.00	0.83	0.50	0.67	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.50
Overall L1	5.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.00 cycles. At this rate:

1% of peak load performance is reached (1.60 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.60 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 433dac

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
CMP W13, W15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 439e10 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0xa610>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X28, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X27, X2, X4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ X22, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W26, W23, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W24, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 433f28 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x4728>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X18, X26, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X16, X2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W30, W21, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X6, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X3, X6, W26,SXTW #3	1	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
LDR D4, [X2, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X25, X12, X3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X0, X18, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
AND W5, W30, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X26, X25, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D4, [X12, X3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
CMP W21, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 433f28 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x4728>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W5, 433eb8 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x46b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD W10, W10, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X2, X2, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W11, W10	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 433dac <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x45ac>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 433df0 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x45f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code