OV - exec - Loop 452

0x431fa4 CMP	W23, W24

0x431fa8 B.CC	439e98

0x431fac ADD	X18, X13, X8

0x431fb0 ADD	X1, X25, X8

0x431fb4 ADD	X30, X3, X18,LSL #3

0x431fb8 MOVZ	W0, #0

0x431fbc ADD	X2, X9, X1,LSL #3

0x431fc0 ADD	X27, X9, X30

  (454) 0x431fc4 LD1D	{Z27.D}, P3/Z, [X27, MUL VL]

  (454) 0x431fc8 ORR	W28, WZR, W0

  (454) 0x431fcc REV	Z28.D, Z27.D

  (454) 0x431fd0 ADD	W0, W0, W4

  (454) 0x431fd4 ST1D	{Z28.D}, P3, [X2, MUL VL]

  (454) 0x431fd8 ADD	X27, X27, X3

  (454) 0x431fdc ADD	X2, X2, X5

  (454) 0x431fe0 CMP	W0, W6

  (454) 0x431fe4 B.LS	431fc4

0x431fe8 ADD	W22, W28, W26

0x431fec CMP	W0, W21

0x431ff0 B.EQ	432128

0x431ff4 SBFM	X11, X22, #0, #31

0x431ff8 ADD	X30, X9, X18,LSL #3

0x431ffc SUB	X12, X18, X11

0x432000 SUB	W15, W21, W11

0x432004 ADD	X16, X9, X12,LSL #3

0x432008 ADD	X28, X11, #1

0x43200c AND	W17, W15, #128

0x432010 LDR	D0, [X9, X12,LSL #3]

0x432014 SUB	X1, X16, #8

0x432018 STR	D0, [X30, X11,LSL #3]

0x43201c CMP	W21, W28

0x432020 B.LT	432128

0x432024 CBZ	W17, 4320b8

  (453) 0x4320b8 ORR	X0, XZR, X1

  (453) 0x4320bc ADD	X2, X28, #1

  (453) 0x4320c0 ADD	X27, X28, #2

  (453) 0x4320c4 ADD	X22, X28, #3

  (453) 0x4320c8 LDR	D6, [X0], #504

  (453) 0x4320cc ADD	X18, X28, #4

  (453) 0x4320d0 ADD	X11, X28, #5

  (453) 0x4320d4 ADD	X12, X28, #6

  (453) 0x4320d8 ADD	X15, X28, #7

  (453) 0x4320dc SUB	X1, X1, #64

  (453) 0x4320e0 STR	D6, [X30, X28,LSL #3]

  (453) 0x4320e4 ADD	X28, X28, #8

  (453) 0x4320e8 LDR	D7, [X1, #56]

  (453) 0x4320ec STR	D7, [X30, X2,LSL #3]

  (453) 0x4320f0 LDUR	D16, [X0, #504]

  (453) 0x4320f4 STR	D16, [X30, X27,LSL #3]

  (453) 0x4320f8 LDR	D17, [X1, #40]

  (453) 0x4320fc STR	D17, [X30, X22,LSL #3]

  (453) 0x432100 LDR	D18, [X1, #32]

  (453) 0x432104 STR	D18, [X30, X18,LSL #3]

  (453) 0x432108 LDR	D19, [X1, #24]

  (453) 0x43210c STR	D19, [X30, X11,LSL #3]

  (453) 0x432110 LDR	D1, [X1, #16]

  (453) 0x432114 STR	D1, [X30, X12,LSL #3]

  (453) 0x432118 LDR	D20, [X1, #8]

  (453) 0x43211c STR	D20, [X30, X15,LSL #3]

  (453) 0x432120 CMP	W21, W28

  (453) 0x432124 B.GE	4320b8

0x432128 ADD	W7, W7, #1

0x43212c ADD	X8, X8, X14

0x432130 CMP	W10, W7

0x432134 B.GT	431fa4

0x439e98 MOVZ	W22, #1

0x439e9c ADD	X18, X13, X8

0x439ea0 B	431ff4

/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90: 698 - 702

--------------------------------------------------------------------------------

698:         !$OMP DO

699:         DO k=y_min-depth,y_max+1+depth

700:         !$OMP SIMD

701:           DO j=1,depth

702:             vol_flux_y(x_max+j,k)=vol_flux_y(x_max-j,k)

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	update_halo_kernel	update_halo_kernel.f90:754	exec
○	update_halo	update_halo.f90:78	exec
○	advection	advection.f90:56	exec
○	hydro	hydro.f90:64	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec

Path /

Metric	Value
CQA speedup if no scalar integer	6.90
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.34
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.48
Bottlenecks	P2, P3, P4, P5,
Function	update_halo_kernel._omp_fn.0
Source	update_halo_kernel.f90:698-698,update_halo_kernel.f90:702-702
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.75
CQA cycles if no scalar integer	0.83
CQA cycles if FP arith vectorized	5.75
CQA cycles if fully vectorized	0.91
Front-end cycles	3.88
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	5.75
P2 cycles	5.75
P3 cycles	5.75
P4 cycles	5.75
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.83
P10 cycles	0.50
P11 cycles	0.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	31.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.78
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	18.06
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	20.83
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	6.90
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	6.34
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.48
Bottlenecks	P2, P3, P4, P5,
Function	update_halo_kernel._omp_fn.0
Source	update_halo_kernel.f90:698-698,update_halo_kernel.f90:702-702
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	5.75
CQA cycles if no scalar integer	0.83
CQA cycles if FP arith vectorized	5.75
CQA cycles if fully vectorized	0.91
Front-end cycles	3.88
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	5.75
P2 cycles	5.75
P3 cycles	5.75
P4 cycles	5.75
P5 cycles	0.50
P6 cycles	0.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.83
P10 cycles	0.50
P11 cycles	0.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	31.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	2.78
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	18.06
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	20.83
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	update_halo_kernel._omp_fn.0
Source file and lines	update_halo_kernel.f90:698-702
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90:698-702.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90:698,702.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.75 to 0.83 cycles (6.90x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 18% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.75 to 0.91 cycles (6.34x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	5.75	5.75	5.75	5.75	0.50	0.50	0.00	0.00	0.83	0.50	0.67	0.00	0.00
cycles	3.00	3.00	5.75	5.75	5.75	5.75	0.50	0.50	0.00	0.00	0.83	0.50	0.67	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.88
Overall L1	5.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.75 cycles. At this rate:

1% of peak load performance is reached (1.39 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.39 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 431fa4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
CMP W23, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 439e98 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0xa698>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X18, X13, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X25, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X30, X3, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X2, X9, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X27, X9, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W22, W28, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W0, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 432128 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x2928>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X11, X22, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X30, X9, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X12, X18, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W15, W21, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X16, X9, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X28, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
AND W17, W15, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D0, [X9, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUB X1, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D0, [X30, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
CMP W21, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 432128 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x2928>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W17, 4320b8 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x28b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD W7, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X8, X8, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W10, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 431fa4 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x27a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X18, X13, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 431ff4 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x27f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Function	update_halo_kernel._omp_fn.0
Source file and lines	update_halo_kernel.f90:698-702
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90:698-702.

Analyzed code is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/update_halo_kernel.f90:698,702.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.75 to 0.83 cycles (6.90x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 18% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 5.75 to 0.91 cycles (6.34x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes. The binary loop is storing 8 bytes.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	5.75	5.75	5.75	5.75	0.50	0.50	0.00	0.00	0.83	0.50	0.67	0.00	0.00
cycles	3.00	3.00	5.75	5.75	5.75	5.75	0.50	0.50	0.00	0.00	0.83	0.50	0.67	0.00	0.00

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	3.88
Overall L1	5.75

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 5.75 cycles. At this rate:

1% of peak load performance is reached (1.39 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.39 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 431fa4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	P12	Latency	Recip. throughput
CMP W23, W24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.CC 439e98 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0xa698>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD X18, X13, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X1, X25, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X30, X3, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
MOVZ W0, #0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X2, X9, X1,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X27, X9, X30	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD W22, W28, W26	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W0, W21	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.EQ 432128 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x2928>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
SBFM X11, X22, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X30, X9, X18,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB X12, X18, X11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
SUB W15, W21, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X16, X9, X12,LSL #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X28, X11, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
AND W17, W15, #128	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
LDR D0, [X9, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
SUB X1, X16, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
STR D0, [X30, X11,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0.50	0.50	0	2	0.50
CMP W21, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.LT 432128 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x2928>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
CBZ W17, 4320b8 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x28b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
ADD W7, W7, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X8, X8, X14	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
CMP W10, W7	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.33
B.GT 431fa4 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x27a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50
MOVZ W22, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
ADD X18, X13, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.25
B 431ff4 <__update_halo_kernel_module_MOD_update_halo_kernel._omp_fn.0+0x27f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code