OV - exec - Loop 255

	Loop Id: 255	Module: exec	Source: generate_chunk_kernel.f90:129-155 [...]	Coverage: 0.02%

0x425a40 LDR	W11, [X14]    [12]

0x425a44 CMP	W6, W11

0x425a48 B.EQ	425bb0

0x425a4c LDR	W11, [X16]    [16]

0x425a50 CMP	W6, W11

0x425a54 B.EQ	425b38

0x425a58 ADD	X1, X1, #8

0x425a5c ADD	X8, X8, #8

0x425a60 ADD	X7, X7, #8

0x425a64 ADD	X5, X5, #8

0x425a68 ADD	X4, X4, #8

0x425a6c ADD	X2, X2, #8

0x425a70 ADD	X0, X0, #8

0x425a74 ADD	X3, X3, #8

0x425a78 CMP	X12, X1

0x425a7c B.EQ	425bdc

0x425a80 CMP	W6, W28

0x425a84 B.NE	425a40

0x425a88 LDUR	D24, [X3, #504]    [20]

0x425a8c LDR	D23, [X15, X19,LSL #3]    [6]

0x425a90 FCMPE	D24, D23

0x425a94 B.GE	425aec

0x425a98 B	425a58

0x425aec LDUR	D26, [X3, #496]    [20]

0x425af0 LDR	D25, [X30, X19,LSL #3]    [2]

0x425af4 FCMPE	D26, D25

0x425af8 B.MI	425b00

0x425afc B	425a58

0x425b00 LDR	X11, [SP, #296]    [8]

0x425b04 LDR	D27, [X11, X10,LSL #3]    [21]

0x425b08 LDR	X11, [SP, #176]    [8]

0x425b0c LDR	D28, [X11, X19,LSL #3]    [3]

0x425b10 FCMPE	D27, D28

0x425b14 B.GE	425b1c

0x425b18 B	425a58

0x425b1c LDR	X11, [SP, #272]    [8]

0x425b20 LDR	D29, [X11, X9,LSL #3]    [19]

0x425b24 LDR	X11, [SP, #320]    [8]

0x425b28 LDR	D30, [X11, X19,LSL #3]    [13]

0x425b2c FCMPE	D29, D30

0x425b30 B.MI	425b54

0x425b34 B	425a58

0x425b38 LDUR	D5, [X3, #496]    [20]

0x425b3c FCMP	D2, D5

0x425b40 B.NE	425a58

0x425b44 LDR	X11, [SP, #272]    [8]

0x425b48 LDR	D6, [X11, X9,LSL #3]    [19]

0x425b4c FCMP	D4, D6

0x425b50 B.NE	425a58

0x425b54 LDR	X11, [SP, #280]    [8]

0x425b58 LDR	D31, [X11, X19,LSL #3]    [15]

0x425b5c LDR	X11, [SP, #288]    [8]

0x425b60 STR	D31, [X8]    [5]

0x425b64 LDR	D0, [X11, X19,LSL #3]    [7]

0x425b68 STR	D0, [X7]    [4]

0x425b6c LDR	D1, [X24, X13]    [9]

0x425b70 STR	D1, [X5]    [1]

0x425b74 LDR	D3, [X23, X13]    [11]

0x425b78 STR	D3, [X4]    [23]

0x425b7c LDR	D5, [X24, X13]    [9]

0x425b80 STR	D5, [X5, #8]    [1]

0x425b84 LDR	D6, [X23, X13]    [11]

0x425b88 STR	D6, [X4, #8]    [23]

0x425b8c LDR	D7, [X24, X13]    [9]

0x425b90 STR	D7, [X2]    [18]

0x425b94 LDR	D16, [X23, X13]    [11]

0x425b98 STR	D16, [X0]    [14]

0x425b9c LDR	D17, [X24, X13]    [9]

0x425ba0 STR	D17, [X2, #8]    [18]

0x425ba4 LDR	D18, [X23, X13]    [11]

0x425ba8 STR	D18, [X0, #8]    [14]

0x425bac B	425a58

0x425bb0 LDR	D7, [X27, X9,LSL #3]    [22]

0x425bb4 LDUR	D19, [X1, #496]    [17]

0x425bb8 LDR	D16, [X25, X19,LSL #3]    [10]

0x425bbc FSUB	D17, D7, S4

0x425bc0 FSUB	D20, D19, S2

0x425bc4 FMUL	D18, D17, D17

0x425bc8 FMADD	D21, D20, D20, D18

0x425bcc FSQRT	D22, D21

0x425bd0 FCMPE	D22, D16

0x425bd4 B.LS	425b54

0x425bd8 B	425a58

/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/generate_chunk_kernel.f90: 129 - 155

--------------------------------------------------------------------------------

129:           IF(state_geometry(state).EQ.g_rect ) THEN

130:             IF(vertexx(j+1).GE.state_xmin(state).AND.vertexx(j).LT.state_xmax(state)) THEN

131:               IF(vertexy(k+1).GE.state_ymin(state).AND.vertexy(k).LT.state_ymax(state)) THEN

132:                 energy0(j,k)=state_energy(state)

133:                 density0(j,k)=state_density(state)

134:                 DO kt=k,k+1

135:                   DO jt=j,j+1

136:                     xvel0(jt,kt)=state_xvel(state)

137:                     yvel0(jt,kt)=state_yvel(state)

138:                   ENDDO

139:                 ENDDO

140:               ENDIF

141:             ENDIF

142:           ELSEIF(state_geometry(state).EQ.g_circ ) THEN

143:             radius=SQRT((cellx(j)-x_cent)*(cellx(j)-x_cent)+(celly(k)-y_cent)*(celly(k)-y_cent))

144:             IF(radius.LE.state_radius(state))THEN

[...]

154:           ELSEIF(state_geometry(state).EQ.g_point) THEN

155:             IF(vertexx(j).EQ.x_cent .AND. vertexy(k).EQ.y_cent) THEN

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	generate_chunk_kernel	generate_chunk_kernel.f90:174	exec
○	generate_chunk	generate_chunk.f90:75	exec
○	start	start.f90:104	exec
○	initialise	initialise.f90:141	exec
○	main	clover_leaf.f90:72	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.27
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.48
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.35
Bottlenecks	P10, P11, P12,
Function	generate_chunk_kernel._omp_fn.0
Source	generate_chunk_kernel.f90:129-144,generate_chunk_kernel.f90:154-155
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	14.00
CQA cycles if fully vectorized	3.13
Front-end cycles	10.38
DIV/SQRT cycles	8.50
P0 cycles	8.50
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	8.50
P6 cycles	8.50
P7 cycles	2.50
P8 cycles	2.50
P9 cycles	14.00
P10 cycles	14.00
P11 cycles	14.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	83.00
Nb uops	83.00
Nb loads	NA
Nb stores	10.00
Nb stack references	0.00
FLOP/cycle	0.43
Nb FLOP add-sub	2.00
Nb FLOP mul	1.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.43
Bytes prefetched	0.00
Bytes loaded	248.00
Bytes stored	80.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.99
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.63

Metric	Value
CQA speedup if no scalar integer	1.27
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.48
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.35
Bottlenecks	P10, P11, P12,
Function	generate_chunk_kernel._omp_fn.0
Source	generate_chunk_kernel.f90:129-144,generate_chunk_kernel.f90:154-155
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	14.00
CQA cycles if no scalar integer	11.00
CQA cycles if FP arith vectorized	14.00
CQA cycles if fully vectorized	3.13
Front-end cycles	10.38
DIV/SQRT cycles	8.50
P0 cycles	8.50
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	3.00
P4 cycles	3.00
P5 cycles	8.50
P6 cycles	8.50
P7 cycles	2.50
P8 cycles	2.50
P9 cycles	14.00
P10 cycles	14.00
P11 cycles	14.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	1.00 - 0.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	83.00
Nb uops	83.00
Nb loads	NA
Nb stores	10.00
Nb stack references	0.00
FLOP/cycle	0.43
Nb FLOP add-sub	2.00
Nb FLOP mul	1.00
Nb FLOP fma	1.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	1.00
Nb FLOP rsqrt	0.00
Bytes/cycle	23.43
Bytes prefetched	0.00
Bytes loaded	248.00
Bytes stored	80.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.99
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	15.63

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	generate_chunk_kernel._omp_fn.0
Source file and lines	generate_chunk_kernel.f90:129-155
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/generate_chunk_kernel.f90:129-144,154-155.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=11
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 11 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 14.00 to 11.00 cycles (1.27x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 14.00 to 3.13 cycles (4.48x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

3: addition or subtraction (1 inside FMA instructions)
2: multiply (1 inside FMA instructions)
1: square root

The binary loop is loading 248 bytes. The binary loop is storing 80 bytes.

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	83
loop length	332
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.50	8.50	3.00	3.00	3.00	3.00	8.50	8.50	2.50	2.50	14.00	14.00	14.00	0.00	0.00
cycles	8.50	8.50	3.00	3.00	3.00	3.00	8.50	8.50	2.50	2.50	14.00	14.00	14.00	0.00	0.00

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	10.38
Overall L1	14.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.00 cycles. At this rate:

18% of peak load performance is reached (17.71 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (5.71 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 425a80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR W11, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP W6, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 425bb0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x850>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W11, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP W6, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 425b38 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x7d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X7, X7, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X3, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 425bdc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x87c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W6, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 425a40 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x6e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR D24, [X3, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D23, [X15, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D24, D23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GE 425aec <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x78c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 425a58 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x6f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR D26, [X3, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D25, [X30, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D26, D25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 425b00 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x7a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 425a58 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x6f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D27, [X11, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X11, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D28, [X11, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D27, D28	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GE 425b1c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x7bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 425a58 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x6f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D29, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X11, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D30, [X11, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D29, D30	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 425b54 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x7f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 425a58 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x6f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR D5, [X3, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMP D2, D5	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.NE 425a58 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x6f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D6, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMP D4, D6	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.NE 425a58 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x6f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D31, [X11, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X11, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
STR D31, [X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D0, [X11, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D0, [X7]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D1, [X24, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D1, [X5]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D3, [X23, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D3, [X4]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D5, [X24, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D5, [X5, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D6, [X23, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D6, [X4, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D7, [X24, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D7, [X2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D16, [X23, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D16, [X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D17, [X24, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D17, [X2, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D18, [X23, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D18, [X0, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 425a58 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x6f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D7, [X27, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDUR D19, [X1, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D16, [X25, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSUB D17, D7, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D20, D19, S2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D18, D17, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D21, D20, D20, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FSQRT D22, D21	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	1-0.50
FCMPE D22, D16	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LS 425b54 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x7f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 425a58 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x6f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	generate_chunk_kernel._omp_fn.0
Source file and lines	generate_chunk_kernel.f90:129-155
Module	exec

Ignoring paths for analysis
Too many paths. Rerun with max-paths=11
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 1 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 6 FP arithmetical operations:

3: addition or subtraction (1 inside FMA instructions)
2: multiply (1 inside FMA instructions)
1: square root

The binary loop is loading 248 bytes. The binary loop is storing 80 bytes.

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	83
loop length	332
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	8.50	8.50	3.00	3.00	3.00	3.00	8.50	8.50	2.50	2.50	14.00	14.00	14.00	0.00	0.00
cycles	8.50	8.50	3.00	3.00	3.00	3.00	8.50	8.50	2.50	2.50	14.00	14.00	14.00	0.00	0.00

Cycles executing div or sqrt instructions

1.00-0.50

Cycles summary

Front-end	10.38
Overall L1	14.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.00 cycles. At this rate:

18% of peak load performance is reached (17.71 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (5.71 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 425a80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR W11, [X14]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP W6, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 425bb0 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x850>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W11, [X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
CMP W6, W11	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 425b38 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x7d8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X1, X1, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X8, X8, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X7, X7, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X5, X5, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X0, X0, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X3, X3, #8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.EQ 425bdc <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x87c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W6, W28	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.NE 425a40 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x6e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR D24, [X3, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D23, [X15, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D24, D23	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GE 425aec <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x78c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 425a58 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x6f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR D26, [X3, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D25, [X30, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D26, D25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 425b00 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x7a0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 425a58 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x6f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #296]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D27, [X11, X10,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X11, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D28, [X11, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D27, D28	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GE 425b1c <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x7bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 425a58 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x6f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D29, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X11, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D30, [X11, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMPE D29, D30	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.MI 425b54 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x7f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 425a58 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x6f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDUR D5, [X3, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMP D2, D5	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.NE 425a58 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x6f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D6, [X11, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FCMP D4, D6	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.NE 425a58 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x6f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X11, [SP, #280]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
LDR D31, [X11, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR X11, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33
STR D31, [X8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D0, [X11, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D0, [X7]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D1, [X24, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D1, [X5]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D3, [X23, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D3, [X4]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D5, [X24, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D5, [X5, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D6, [X23, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D6, [X4, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D7, [X24, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D7, [X2]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D16, [X23, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D16, [X0]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D17, [X24, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D17, [X2, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
LDR D18, [X23, X13]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
STR D18, [X0, #8]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
B 425a58 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x6f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR D7, [X27, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDUR D19, [X1, #496]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D16, [X25, X19,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSUB D17, D7, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D20, D19, S2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D18, D17, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D21, D20, D20, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FSQRT D22, D21	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	1-0.50
FCMPE D22, D16	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.LS 425b54 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x7f4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 425a58 <__generate_chunk_kernel_module_MOD_generate_chunk_kernel._omp_fn.0+0x6f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code