OV - exec - Loop 245

	Loop Id: 245	Module: exec	Source: flux_calc_kernel.f90:58-60	Coverage: 4.68%

0x424e08 LD1D	{Z0.D}, P1/Z, [X9, X1,LSL #3]    [10]

0x424e0c LD1D	{Z1.D}, P1/Z, [X15, X1,LSL #3]    [9]

0x424e10 LD1D	{Z2.D}, P1/Z, [X8, X1,LSL #3]    [7]

0x424e14 LD1D	{Z5.D}, P1/Z, [X14, X1,LSL #3]    [12]

0x424e18 LD1D	{Z18.D}, P1/Z, [X11, X1,LSL #3]    [3]

0x424e1c LD1RD	{Z7.D}, P0/Z, [X5]    [1]

0x424e20 FADD	Z4.D, Z1.D, Z0.D

0x424e24 FMUL	Z17.D, Z7.D, Z3.D

0x424e28 FADD	Z6.D, Z2.D, Z4.D

0x424e2c FMUL	Z19.D, Z17.D, Z18.D

0x424e30 FADD	Z16.D, Z5.D, Z6.D

0x424e34 FMUL	Z20.D, Z16.D, Z19.D

0x424e38 ST1D	{Z20.D}, P1, [X3, X1,LSL #3]    [11]

0x424e3c LD1D	{Z21.D}, P1/Z, [X7, X1,LSL #3]    [6]

0x424e40 LD1D	{Z22.D}, P1/Z, [X13, X1,LSL #3]    [2]

0x424e44 LD1D	{Z23.D}, P1/Z, [X6, X1,LSL #3]    [5]

0x424e48 LD1D	{Z25.D}, P1/Z, [X12, X1,LSL #3]    [4]

0x424e4c LD1D	{Z30.D}, P1/Z, [X10, X1,LSL #3]    [13]

0x424e50 LD1RD	{Z27.D}, P0/Z, [X5]    [1]

0x424e54 FADD	Z24.D, Z21.D, Z22.D

0x424e58 FMUL	Z29.D, Z27.D, Z3.D

0x424e5c FADD	Z26.D, Z24.D, Z23.D

0x424e60 FMUL	Z31.D, Z29.D, Z30.D

0x424e64 FADD	Z28.D, Z26.D, Z25.D

0x424e68 FMUL	Z0.D, Z28.D, Z31.D

0x424e6c ST1D	{Z0.D}, P1, [X2, X1,LSL #3]    [8]

0x424e70 ADD	X1, X1, X0

0x424e74 WHILELO	P1.D, X1, X4

0x424e78 B.NE	424e08

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/flux_calc_kernel.f90: 58 - 60

--------------------------------------------------------------------------------

58:           *(xvel0(j,k)+xvel0(j,k+1)+xvel1(j,k)+xvel1(j,k+1))

59:         vol_flux_y(j,k)=0.25_8*dt*yarea(j,k)                  &

60:           *(yvel0(j,k)+yvel0(j+1,k)+yvel1(j,k)+yvel1(j+1,k))

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.12
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.17
Bottlenecks	P10, P11,
Function	flux_calc_kernel._omp_fn.0
Source	flux_calc_kernel.f90:58-60
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	16
CQA cycles	7.00
CQA cycles if no scalar integer	7.00
CQA cycles if FP arith vectorized	7.00
CQA cycles if fully vectorized	6.25
Front-end cycles	3.63
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	1.00
P4 cycles	0.25
P5 cycles	6.00
P6 cycles	6.00
P7 cycles	6.00
P8 cycles	6.00
P9 cycles	7.00
P10 cycles	7.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	29.00
Nb uops	29.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	6.86
Nb FLOP add-sub	24.00
Nb FLOP mul	24.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	57.14
Bytes prefetched	0.00
Bytes loaded	336.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	92.31
Vectorization ratio load	83.33
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	94.23
Vector-efficiency ratio load	87.50
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.12
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.17
Bottlenecks	P10, P11,
Function	flux_calc_kernel._omp_fn.0
Source	flux_calc_kernel.f90:58-60
Source loop unroll info	unrolled by 16
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	16
CQA cycles	7.00
CQA cycles if no scalar integer	7.00
CQA cycles if FP arith vectorized	7.00
CQA cycles if fully vectorized	6.25
Front-end cycles	3.63
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	1.00
P4 cycles	0.25
P5 cycles	6.00
P6 cycles	6.00
P7 cycles	6.00
P8 cycles	6.00
P9 cycles	7.00
P10 cycles	7.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	29.00
Nb uops	29.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	6.86
Nb FLOP add-sub	24.00
Nb FLOP mul	24.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	57.14
Bytes prefetched	0.00
Bytes loaded	336.00
Bytes stored	64.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	92.31
Vectorization ratio load	83.33
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	94.23
Vector-efficiency ratio load	87.50
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	flux_calc_kernel._omp_fn.0
Source file and lines	flux_calc_kernel.f90:58-60
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/flux_calc_kernel.f90:58-60.

The related source loop is unrolled by 16 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 94% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 7.00 to 6.25 cycles (1.12x speedup).

Details

92% of VPU instructions are used in vector version (process two or more data elements in vector registers):

83% of VPU loads are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 48 FP arithmetical operations:

24: addition or subtraction
24: multiply

The binary loop is loading 336 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	6.00	6.00	1.00	1.00	7.00	7.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	6.00	6.00	6.00	6.00	7.00	7.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.63
Data deps.	1.00
Overall L1	7.00

Vectorization ratios

INT

all	85%
load	83%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	92%
load	83%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

50% of peak load performance is reached (48.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
19% of peak store performance is reached (9.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 424e08

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LD1D {Z0.D}, P1/Z, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z1.D}, P1/Z, [X15, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z2.D}, P1/Z, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z5.D}, P1/Z, [X14, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z18.D}, P1/Z, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z7.D}, P0/Z, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z4.D, Z1.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z17.D, Z7.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z6.D, Z2.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z19.D, Z17.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z16.D, Z5.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z20.D, Z16.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z20.D}, P1, [X3, X1,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z21.D}, P1/Z, [X7, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z22.D}, P1/Z, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P1/Z, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z25.D}, P1/Z, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z30.D}, P1/Z, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z27.D}, P0/Z, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z24.D, Z21.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z29.D, Z27.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z26.D, Z24.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z31.D, Z29.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z28.D, Z26.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z0.D, Z28.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z0.D}, P1, [X2, X1,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
WHILELO P1.D, X1, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2
B.NE 424e08 <__flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	flux_calc_kernel._omp_fn.0
Source file and lines	flux_calc_kernel.f90:58-60
Module	exec

gain
potential
hint
expert

Vectorization

Details

92% of VPU instructions are used in vector version (process two or more data elements in vector registers):

83% of VPU loads are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 48 FP arithmetical operations:

24: addition or subtraction
24: multiply

The binary loop is loading 336 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	6.00	6.00	1.00	1.00	7.00	7.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	6.00	6.00	6.00	6.00	7.00	7.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.63
Data deps.	1.00
Overall L1	7.00

Vectorization ratios

INT

all	85%
load	83%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	92%
load	83%
store	100%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.00 cycles. At this rate:

50% of peak load performance is reached (48.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
19% of peak store performance is reached (9.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 424e08

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput
LD1D {Z0.D}, P1/Z, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z1.D}, P1/Z, [X15, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z2.D}, P1/Z, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z5.D}, P1/Z, [X14, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z18.D}, P1/Z, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z7.D}, P0/Z, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z4.D, Z1.D, Z0.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z17.D, Z7.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z6.D, Z2.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z19.D, Z17.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z16.D, Z5.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z20.D, Z16.D, Z19.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z20.D}, P1, [X3, X1,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
LD1D {Z21.D}, P1/Z, [X7, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z22.D}, P1/Z, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z23.D}, P1/Z, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z25.D}, P1/Z, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z30.D}, P1/Z, [X10, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1RD {Z27.D}, P0/Z, [X5]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FADD Z24.D, Z21.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z29.D, Z27.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z26.D, Z24.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z31.D, Z29.D, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
FADD Z28.D, Z26.D, Z25.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	2	0.50
FMUL Z0.D, Z28.D, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
ST1D {Z0.D}, P1, [X2, X1,LSL #3]	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	2	0.50
ADD X1, X1, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
WHILELO P1.D, X1, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	3	2
B.NE 424e08 <__flux_calc_kernel_module_MOD_flux_calc_kernel._omp_fn.0+0x1a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code