OV - exec - Loop 235

	Loop Id: 235	Module: exec	Source: field_summary_kernel.f90:62-71	Coverage: 0.34%

0x4245ec LD1D	{Z23.D}, P0/Z, [X12, X1,LSL #3]    [11]

0x4245f0 LD1D	{Z1.D}, P0/Z, [X3, X1,LSL #3]    [4]

0x4245f4 LD1D	{Z0.D}, P0/Z, [X0, X1,LSL #3]    [7]

0x4245f8 LD1D	{Z3.D}, P0/Z, [X9, X1,LSL #3]    [6]

0x4245fc LD1D	{Z16.D}, P0/Z, [X22, X1,LSL #3]    [9]

0x424600 LD1D	{Z17.D}, P0/Z, [X4, X1,LSL #3]    [10]

0x424604 LD1D	{Z19.D}, P0/Z, [X11, X1,LSL #3]    [3]

0x424608 LD1D	{Z20.D}, P0/Z, [X6, X1,LSL #3]    [12]

0x42460c LD1D	{Z22.D}, P0/Z, [X8, X1,LSL #3]    [1]

0x424610 LD1D	{Z24.D}, P0/Z, [X14, X1,LSL #3]    [5]

0x424614 LD1D	{Z25.D}, P0/Z, [X13, X1,LSL #3]    [8]

0x424618 FMUL	Z26.D, Z24.D, Z23.D

0x42461c LD1D	{Z27.D}, P0/Z, [X5, X1,LSL #3]    [2]

0x424620 FMUL	Z2.D, Z1.D, Z1.D

0x424624 ADD	X1, X1, X15

0x424628 FMAD	Z0.D, P1/M, Z0.D, Z2.D

0x42462c FMUL	Z6.D, Z3.D, Z3.D

0x424630 MOVPRFX	Z7, Z5

0x424634 FMLA	Z7.D, P1/M, Z0.D, Z4.D

0x424638 FMAD	Z16.D, P1/M, Z16.D, Z6.D

0x42463c FMUL	Z18.D, Z17.D, Z17.D

0x424640 FMLA	Z7.D, P1/M, Z16.D, Z4.D

0x424644 FMAD	Z19.D, P1/M, Z19.D, Z18.D

0x424648 FMUL	Z21.D, Z20.D, Z20.D

0x42464c FMLA	Z7.D, P1/M, Z19.D, Z4.D

0x424650 FMAD	Z22.D, P1/M, Z22.D, Z21.D

0x424654 FADDA	D12, P0, D12, Z23.D

0x424658 FMAD	Z22.D, P1/M, Z4.D, Z7.D

0x42465c FADDA	D11, P0, D11, Z26.D

0x424660 MOVPRFX	Z28, Z26

0x424664 FMUL	Z28.D, P1/M, Z28.D, #0

0x424668 FMUL	Z29.D, Z25.D, Z26.D

0x42466c FMUL	Z30.D, Z28.D, Z22.D

0x424670 FADDA	D9, P0, D9, Z29.D

0x424674 FADDA	D8, P0, D8, Z30.D

0x424678 FMUL	Z31.D, Z27.D, Z23.D

0x42467c FADDA	D10, P0, D10, Z31.D

0x424680 WHILELO	P0.D, X1, X2

0x424684 B.NE	4245ec

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/field_summary_kernel.f90: 62 - 71

--------------------------------------------------------------------------------

62:             vsqrd=vsqrd+0.25*(xvel0(jv,kv)**2+yvel0(jv,kv)**2)

63:           ENDDO

64:         ENDDO

65:         cell_vol=volume(j,k)

66:         cell_mass=cell_vol*density0(j,k)

67:         vol=vol+cell_vol

68:         mass=mass+cell_mass

69:         ie=ie+cell_mass*energy0(j,k)

70:         ke=ke+cell_mass*0.5*vsqrd

71:         press=press+cell_vol*pressure(j,k)

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P6, P7,
Function	field_summary_kernel._omp_fn.0
Source	field_summary_kernel.f90:62-71
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	12.00
Front-end cycles	4.88
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	1.00
P4 cycles	0.25
P5 cycles	12.00
P6 cycles	12.00
P7 cycles	11.00
P8 cycles	11.00
P9 cycles	6.00
P10 cycles	6.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	39.00
Nb uops	39.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	10.00
Nb FLOP add-sub	20.00
Nb FLOP mul	36.00
Nb FLOP fma	32.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	94.44
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P6, P7,
Function	field_summary_kernel._omp_fn.0
Source	field_summary_kernel.f90:62-71
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	12.00
Front-end cycles	4.88
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.25
P3 cycles	1.00
P4 cycles	0.25
P5 cycles	12.00
P6 cycles	12.00
P7 cycles	11.00
P8 cycles	11.00
P9 cycles	6.00
P10 cycles	6.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	39.00
Nb uops	39.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	10.00
Nb FLOP add-sub	20.00
Nb FLOP mul	36.00
Nb FLOP fma	32.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	384.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	94.44
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	field_summary_kernel._omp_fn.0
Source file and lines	field_summary_kernel.f90:62-71
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/field_summary_kernel.f90:62-71.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 100% of vector register length is used (average across all VPU instructions).

Details

94% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 32 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 120 FP arithmetical operations:

52: addition or subtraction (32 inside FMA instructions)
68: multiply (32 inside FMA instructions)

The binary loop is loading 384 bytes.

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

General properties

nb instructions	39
loop length	156
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	12.00	12.00	0.00	0.00	6.00	6.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	12.00	12.00	11.00	11.00	6.00	6.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	4.88
Data deps.	8.00
Overall L1	12.00

Vectorization ratios

INT

all	85%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	94%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

33% of peak load performance is reached (32.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4245ec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput
LD1D {Z23.D}, P0/Z, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z1.D}, P0/Z, [X3, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z0.D}, P0/Z, [X0, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z3.D}, P0/Z, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z16.D}, P0/Z, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z17.D}, P0/Z, [X4, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z19.D}, P0/Z, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P0/Z, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z22.D}, P0/Z, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z24.D}, P0/Z, [X14, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z25.D}, P0/Z, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z26.D, Z24.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
LD1D {Z27.D}, P0/Z, [X5, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z2.D, Z1.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADD X1, X1, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
FMAD Z0.D, P1/M, Z0.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMUL Z6.D, Z3.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVPRFX Z7, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMLA Z7.D, P1/M, Z0.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMAD Z16.D, P1/M, Z16.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMUL Z18.D, Z17.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMLA Z7.D, P1/M, Z16.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMAD Z19.D, P1/M, Z19.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMUL Z21.D, Z20.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMLA Z7.D, P1/M, Z19.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMAD Z22.D, P1/M, Z22.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FADDA D12, P0, D12, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50
FMAD Z22.D, P1/M, Z4.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FADDA D11, P0, D11, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50
MOVPRFX Z28, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMUL Z28.D, P1/M, Z28.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMUL Z29.D, Z25.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMUL Z30.D, Z28.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FADDA D9, P0, D9, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50
FADDA D8, P0, D8, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50
FMUL Z31.D, Z27.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FADDA D10, P0, D10, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50
WHILELO P0.D, X1, X2	1	0	0	0	0	1	0	0	0	0	0	3	2
B.NE 4245ec <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x18c>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Function	field_summary_kernel._omp_fn.0
Source file and lines	field_summary_kernel.f90:62-71
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 100% of vector register length is used (average across all VPU instructions).

Details

94% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

FMA

Detected 32 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 120 FP arithmetical operations:

52: addition or subtraction (32 inside FMA instructions)
68: multiply (32 inside FMA instructions)

The binary loop is loading 384 bytes.

Arithmetic intensity

Arithmetic intensity is 0.31 FP operations per loaded or stored byte.

General properties

nb instructions	39
loop length	156
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	0.50	0.25	1.00	0.25	12.00	12.00	0.00	0.00	6.00	6.00	0.00	0.00	0.00
cycles	0.50	0.50	0.50	0.25	1.00	0.25	12.00	12.00	11.00	11.00	6.00	6.00	0.00	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	4.88
Data deps.	8.00
Overall L1	12.00

Vectorization ratios

INT

all	85%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	94%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

33% of peak load performance is reached (32.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 4245ec

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P10	P11	Latency	Recip. throughput
LD1D {Z23.D}, P0/Z, [X12, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z1.D}, P0/Z, [X3, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z0.D}, P0/Z, [X0, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z3.D}, P0/Z, [X9, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z16.D}, P0/Z, [X22, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z17.D}, P0/Z, [X4, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z19.D}, P0/Z, [X11, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z20.D}, P0/Z, [X6, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z22.D}, P0/Z, [X8, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z24.D}, P0/Z, [X14, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
LD1D {Z25.D}, P0/Z, [X13, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z26.D, Z24.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
LD1D {Z27.D}, P0/Z, [X5, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	6	0.50
FMUL Z2.D, Z1.D, Z1.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
ADD X1, X1, X15	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
FMAD Z0.D, P1/M, Z0.D, Z2.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMUL Z6.D, Z3.D, Z3.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOVPRFX Z7, Z5	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMLA Z7.D, P1/M, Z0.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMAD Z16.D, P1/M, Z16.D, Z6.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMUL Z18.D, Z17.D, Z17.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMLA Z7.D, P1/M, Z16.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMAD Z19.D, P1/M, Z19.D, Z18.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMUL Z21.D, Z20.D, Z20.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMLA Z7.D, P1/M, Z19.D, Z4.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FMAD Z22.D, P1/M, Z22.D, Z21.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FADDA D12, P0, D12, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50
FMAD Z22.D, P1/M, Z4.D, Z7.D	1	0	0	0	0	0	0	0.50	0.50	0	0	4	0.50
FADDA D11, P0, D11, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50
MOVPRFX Z28, Z26	1	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50
FMUL Z28.D, P1/M, Z28.D, #0	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMUL Z29.D, Z25.D, Z26.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FMUL Z30.D, Z28.D, Z22.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FADDA D9, P0, D9, Z29.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50
FADDA D8, P0, D8, Z30.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50
FMUL Z31.D, Z27.D, Z23.D	1	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
FADDA D10, P0, D10, Z31.D	1	0	0	0	0	0	0	0.50	0.50	0	0	8	1.50
WHILELO P0.D, X1, X2	1	0	0	0	0	1	0	0	0	0	0	3	2
B.NE 4245ec <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x18c>	1	0.50	0.50	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code