OV - exec - Loop 226

	Loop Id: 226	Module: exec	Source: calc_dt_kernel.f90:96-129	Coverage: 0.01%

0x423140 LDR	W1, [SP, #124]

0x423144 CMP	W1, W13

0x423148 B.GT	42329c

0x42314c LDR	X1, [SP, #192]

0x423150 LDR	D3, [X27, X16]

0x423154 LDR	D1, [X28, X16]

0x423158 STR	X1, [SP, #112]

0x42315c LDR	X1, [SP, #176]

0x423160 LDR	D0, [X21]

0x423164 FADD	D2, D3, D1

0x423168 LDR	D21, [X1]

0x42316c LDR	X1, [SP, #184]

0x423170 FMUL	D3, D2, D0

0x423174 FADD	D21, D21, D21

0x423178 LDR	D20, [X1]

0x42317c LDR	X1, [SP, #160]

0x423180 FADD	D20, D20, D20

0x423184 LDR	D18, [X1]

0x423188 LDR	X1, [SP, #200]

0x42318c FNEG	D22, D18

0x423190 LDR	D24, [X1, X15,LSL #3]

0x423194 LDR	X15, [SP, #168]

0x423198 LDR	X1, [SP, #208]

0x42319c LDR	D23, [X15]

0x4231a0 LDR	X15, [SP, #216]

0x4231a4 LDR	D0, [X1, X17]

0x4231a8 LDR	X1, [SP, #112]

0x4231ac LDR	D1, [X15, X17]

0x4231b0 B	4231bc

  (227) 0x4231b4 FMOV	D1, D16

  (227) 0x4231b8 FMOV	D0, D17

  (227) 0x4231bc LDR	D4, [X3, X1,LSL #3]

  (227) 0x4231c0 FMOV	D27, D3

  (227) 0x4231c4 FABS	D28, D3

  (227) 0x4231c8 LDR	D5, [X11, X1,LSL #3]

  (227) 0x4231cc LDR	D8, [X2, X1,LSL #3]

  (227) 0x4231d0 LDR	D17, [X5, X1,LSL #3]

  (227) 0x4231d4 FADD	D9, D4, D5

  (227) 0x4231d8 LDR	D30, [X6, X1,LSL #3]

  (227) 0x4231dc LDR	D29, [X9, X1,LSL #3]

  (227) 0x4231e0 FADD	D7, D17, D0

  (227) 0x4231e4 LDR	D16, [X4, X1,LSL #3]

  (227) 0x4231e8 FMUL	D3, D9, D8

  (227) 0x4231ec FADD	D5, D30, D30

  (227) 0x4231f0 LDR	D9, [X8, X1,LSL #3]

  (227) 0x4231f4 LDR	D31, [X10, X1,LSL #3]

  (227) 0x4231f8 FMUL	D7, D7, D29

  (227) 0x4231fc FADD	D6, D16, D1

  (227) 0x423200 LDR	D2, [X12, X1,LSL #3]

  (227) 0x423204 FADD	D0, D3, D25

  (227) 0x423208 FDIV	D5, D5, D9

  (227) 0x42320c LDR	D4, [X14, X1,LSL #3]

  (227) 0x423210 FMINNM	D29, D4, D24

  (227) 0x423214 FMUL	D4, D29, D23

  (227) 0x423218 LDR	D1, [X7, X1,LSL #3]

  (227) 0x42321c FABS	D8, D3

  (227) 0x423220 FMUL	D6, D6, D31

  (227) 0x423224 FABS	D9, D7

  (227) 0x423228 FSUB	D0, D0, S27

  (227) 0x42322c FADD	D29, D2, D2

  (227) 0x423230 FMUL	D30, D2, D21

  (227) 0x423234 FMUL	D31, D2, D20

  (227) 0x423238 FMUL	D2, D18, D2

  (227) 0x42323c FMAXNM	D28, D28, D2

  (227) 0x423240 FMAXNM	D8, D28, D8

  (227) 0x423244 FABS	D27, D6

  (227) 0x423248 FMAXNM	D9, D27, D9

  (227) 0x42324c FMAXNM	D9, D9, D2

  (227) 0x423250 FADD	D7, D0, D7

  (227) 0x423254 FDIV	D30, D30, D8

  (227) 0x423258 FMADD	D1, D1, D1, D5

  (227) 0x42325c FSUB	D6, D7, S6

  (227) 0x423260 FDIV	D31, D31, D9

  (227) 0x423264 FDIV	D5, D6, D29

  (227) 0x423268 FSQRT	D29, D1

  (227) 0x42326c FMAXNM	D0, D29, D18

  (227) 0x423270 FDIV	D4, D4, D0

  (227) 0x423274 FMINNM	D27, D30, D4

  (227) 0x423278 FCMPE	D5, D22

  (227) 0x42327c B.MI	42330c

  (227) 0x423280 ADD	X1, X1, #1

  (227) 0x423284 LDR	D2, [X20]

  (227) 0x423288 FMINNM	D28, D31, D2

  (227) 0x42328c FMINNM	D9, D28, D27

  (227) 0x423290 FMINNM	D19, D19, D9

  (227) 0x423294 CMP	W13, W1

  (227) 0x423298 B.GE	4231b4

0x42329c LDR	W1, [SP, #232]

0x4232a0 ADD	X3, X3, X22

0x4232a4 ADD	X11, X11, X22

0x4232a8 ADD	X2, X2, X24

0x4232ac ADD	X4, X4, X18

0x4232b0 ADD	X10, X10, X23

0x4232b4 ADD	X5, X5, X18

0x4232b8 ADD	X9, X9, X23

0x4232bc ADD	X21, X21, X24

0x4232c0 ADD	X16, X16, X22

0x4232c4 ADD	X17, X17, X18

0x4232c8 CMP	W26, W1

0x4232cc LDR	X1, [SP, #152]

0x4232d0 ORR	X15, XZR, X0

0x4232d4 CSEL	W19, W19, W26, #1

0x4232d8 CSINC	W25, W25, WZR, #1

0x4232dc ADD	X7, X7, X1

0x4232e0 LDR	X1, [SP, #144]

0x4232e4 ADD	X6, X6, X1

0x4232e8 LDR	X1, [SP, #136]

0x4232ec ADD	X8, X8, X1

0x4232f0 LDR	X1, [SP, #128]

0x4232f4 ADD	X12, X12, X1

0x4232f8 LDR	W1, [SP, #120]

0x4232fc CMP	W1, W0

0x423300 B.LE	423370

0x423304 ADD	X0, X0, #1

0x423308 B	423140

  (227) 0x42330c FDIV	D8, D26, D5

  (227) 0x423310 LDR	D30, [X30]

  (227) 0x423314 ADD	X1, X1, #1

  (227) 0x423318 FNMUL	D7, D8, D30

  (227) 0x42331c FMINNM	D31, D7, D31

  (227) 0x423320 FMINNM	D6, D31, D27

  (227) 0x423324 FMINNM	D19, D19, D6

  (227) 0x423328 CMP	W13, W1

  (227) 0x42332c B.GE	4231b4

0x423330 B	42329c

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90: 96 - 129

--------------------------------------------------------------------------------

96:         dsx=celldx(j)

97:         dsy=celldy(k)

98:

99:         cc=soundspeed(j,k)*soundspeed(j,k)

100:         cc=cc+2.0_8*viscosity_a(j,k)/density0(j,k)

101:         cc=MAX(SQRT(cc),g_small)

102:

103:         dtct=dtc_safe*MIN(dsx,dsy)/cc

104:

105:         div=0.0

106:

107:         dv1=(xvel0(j  ,k)+xvel0(j  ,k+1))*xarea(j  ,k)

108:         dv2=(xvel0(j+1,k)+xvel0(j+1,k+1))*xarea(j+1,k)

109:

110:         div=div+dv2-dv1

111:

112:         dtut=dtu_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

113:

114:         dv1=(yvel0(j,k  )+yvel0(j+1,k  ))*yarea(j,k  )

115:         dv2=(yvel0(j,k+1)+yvel0(j+1,k+1))*yarea(j,k+1)

116:

117:         div=div+dv2-dv1

118:

119:         dtvt=dtv_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

120:

121:         div=div/(2.0_8*volume(j,k))

122:

123:         IF(div.LT.-g_small)THEN

124:           dtdivt=dtdiv_safe*(-1.0_8/div)

125:         ELSE

126:           dtdivt=g_big

127:         ENDIF

128:

129:         dt_min_val=MIN(dt_min_val,dtct,dtut,dtvt,dtdivt)

Path /

Metric	Value
CQA speedup if no scalar integer	2.75
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.87
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P10,
Function	calc_dt_kernel._omp_fn.0
Source	calc_dt_kernel.f90:97-97,calc_dt_kernel.f90:101-103,calc_dt_kernel.f90:112-114,calc_dt_kernel.f90:119-119,calc_dt_kernel.f90:123-123,calc_dt_kernel.f90:129-129
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.17
CQA cycles if no scalar integer	3.33
CQA cycles if FP arith vectorized	9.17
CQA cycles if fully vectorized	1.56
Front-end cycles	7.25
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	5.25
P2 cycles	5.25
P3 cycles	5.25
P4 cycles	5.25
P5 cycles	1.25
P6 cycles	1.25
P7 cycles	1.25
P8 cycles	1.25
P9 cycles	9.17
P10 cycles	8.83
P11 cycles	9.00
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	58.00
Nb uops	58.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.44
Nb FLOP add-sub	3.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.25
Bytes prefetched	0.00
Bytes loaded	196.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.44
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Metric	Value
CQA speedup if no scalar integer	2.75
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.87
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	P10,
Function	calc_dt_kernel._omp_fn.0
Source	calc_dt_kernel.f90:97-97,calc_dt_kernel.f90:101-103,calc_dt_kernel.f90:112-114,calc_dt_kernel.f90:119-119,calc_dt_kernel.f90:123-123,calc_dt_kernel.f90:129-129
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.17
CQA cycles if no scalar integer	3.33
CQA cycles if FP arith vectorized	9.17
CQA cycles if fully vectorized	1.56
Front-end cycles	7.25
DIV/SQRT cycles	2.50
P0 cycles	2.50
P1 cycles	5.25
P2 cycles	5.25
P3 cycles	5.25
P4 cycles	5.25
P5 cycles	1.25
P6 cycles	1.25
P7 cycles	1.25
P8 cycles	1.25
P9 cycles	9.17
P10 cycles	8.83
P11 cycles	9.00
P12 cycles	0.50
P13 cycles	0.50
P14 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	58.00
Nb uops	58.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.44
Nb FLOP add-sub	3.00
Nb FLOP mul	1.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.25
Bytes prefetched	0.00
Bytes loaded	196.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.44
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	12.50

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	calc_dt_kernel._omp_fn.0
Source file and lines	calc_dt_kernel.f90:96-129
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:96-129.

Analyzed code is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:97,101-103,112-114,119,123,129.

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 5 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.17 to 3.33 cycles (2.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 9.17 to 1.56 cycles (5.87x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 4 FP arithmetical operations:

3: addition or subtraction
1: multiply

The binary loop is loading 196 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	58
loop length	232
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	5.25	5.25	5.25	5.25	1.25	1.25	1.25	1.25	9.17	8.83	9.00	0.50	0.50
cycles	2.50	2.50	5.25	5.25	5.25	5.25	1.25	1.25	1.25	1.25	9.17	8.83	9.00	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.25
Overall L1	9.17

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.17 cycles. At this rate:

22% of peak load performance is reached (21.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.87 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 423140

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR W1, [SP, #124]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W1, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 42329c <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x39c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D3, [X27, X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D1, [X28, X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR X1, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X1, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D2, D3, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR D21, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X1, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMUL D3, D2, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FADD D21, D21, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR D20, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X1, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FADD D20, D20, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR D18, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X1, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FNEG D22, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR D24, [X1, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X15, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D23, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X15, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D0, [X1, X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X1, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D1, [X15, X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
B 4231bc <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W1, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X3, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X11, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X10, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X5, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X21, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X16, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X17, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W26, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X1, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X15, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL W19, W19, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W25, W25, WZR, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X7, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W1, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 423370 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 423140 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x240>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 42329c <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x39c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	calc_dt_kernel._omp_fn.0
Source file and lines	calc_dt_kernel.f90:96-129
Module	exec

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. Rerun with max-paths=5
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 9.17 to 3.33 cycles (2.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 4 FP arithmetical operations:

3: addition or subtraction
1: multiply

The binary loop is loading 196 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	58
loop length	232
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

7.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	2.50	2.50	5.25	5.25	5.25	5.25	1.25	1.25	1.25	1.25	9.17	8.83	9.00	0.50	0.50
cycles	2.50	2.50	5.25	5.25	5.25	5.25	1.25	1.25	1.25	1.25	9.17	8.83	9.00	0.50	0.50

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	7.25
Overall L1	9.17

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.17 cycles. At this rate:

22% of peak load performance is reached (21.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (0.87 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 423140

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput
LDR W1, [SP, #124]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W1, W13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.GT 42329c <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x39c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR X1, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D3, [X27, X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR D1, [X28, X16]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
STR X1, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50
LDR X1, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D0, [X21]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
FADD D2, D3, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR D21, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X1, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FMUL D3, D2, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25
FADD D21, D21, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR D20, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X1, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FADD D20, D20, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR D18, [X1]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X1, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
FNEG D22, D18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25
LDR D24, [X1, X15,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X15, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR X1, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D23, [X15]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X15, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D0, [X1, X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
LDR X1, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
LDR D1, [X15, X17]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33
B 4231bc <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x2bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LDR W1, [SP, #232]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X3, X3, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X11, X11, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X2, X2, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X4, X4, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X10, X10, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X5, X5, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X9, X9, X23	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X21, X21, X24	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X16, X16, X22	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X17, X17, X18	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CMP W26, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
LDR X1, [SP, #152]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ORR X15, XZR, X0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSEL W19, W19, W26, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
CSINC W25, W25, WZR, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
ADD X7, X7, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X6, X6, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X8, X8, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR X1, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
ADD X12, X12, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
LDR W1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33
CMP W1, W0	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33
B.LE 423370 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
ADD X0, X0, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
B 423140 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x240>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
B 42329c <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x39c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code