OV - exec - Loop 180

0x4212f0 ADD	W7, W7, #1

0x4212f4 SUB	X27, X3, #8

0x4212f8 ORR	P0.B, P8/Z, P8.B, P8.B

0x4212fc ADD	X16, X4, X3

0x421300 ADD	X28, X3, X10

0x421304 MOVZ	X0, #0

  (179) 0x421308 LD1D	{Z4.D}, P0/Z, [X27, X0,LSL #3]

  (179) 0x42130c LD1D	{Z5.D}, P0/Z, [X3, X0,LSL #3]

  (179) 0x421310 LD1D	{Z6.D}, P0/Z, [X16, X0,LSL #3]

  (179) 0x421314 LD1D	{Z16.D}, P0/Z, [X28, X0,LSL #3]

  (179) 0x421318 FADD	Z7.D, Z5.D, Z4.D

  (179) 0x42131c FADD	Z17.D, Z6.D, Z7.D

  (179) 0x421320 FADD	Z18.D, Z16.D, Z17.D

  (179) 0x421324 FMUL	Z19.D, Z18.D, Z20.D

  (179) 0x421328 ST1D	{Z19.D}, P0, [X14, X0,LSL #3]

  (179) 0x42132c ADD	X0, X0, X30

  (179) 0x421330 WHILELO	P0.D, X0, X2

  (179) 0x421334 B.NE	421308

0x421338 ADD	X3, X3, X13

0x42133c ADD	X14, X14, X12

0x421340 CMP	W9, W7

0x421344 B.GT	4212f0

/home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 190 - 196

--------------------------------------------------------------------------------

190:         !$OMP DO

[...]

196:               +mass_flux_y(j-1,k+1)+mass_flux_y(j  ,k+1))

Coverage (%)	Name	Source Location	Module
►100.00+	GOMP_parallel		libgomp.so.1.0.0
○	advec_mom_kernel	advec_mom_kernel.f90:256	exec
○	advec_mom_driver	advec_mom_driver.f90:81	exec
○	advection	advection.f90:77	exec
○	hydro	hydro.f90:64	exec
○	main	clover_leaf.f90:41	exec
○	__libc_start_main		libc-2.31.so
○	_start	clover_leaf.f90:41	exec

Path /

Metric	Value
CQA speedup if no scalar integer	2.25
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.14
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.80
Bottlenecks	P2, P3, P4, P5,
Function	advec_mom_kernel._omp_fn.0
Source	advec_mom_kernel.f90:190-190,advec_mom_kernel.f90:196-196
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.25
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	2.25
CQA cycles if fully vectorized	0.44
Front-end cycles	1.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	10.00
Nb uops	10.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	14.29
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	23.21
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Metric	Value
CQA speedup if no scalar integer	2.25
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	5.14
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.80
Bottlenecks	P2, P3, P4, P5,
Function	advec_mom_kernel._omp_fn.0
Source	advec_mom_kernel.f90:190-190,advec_mom_kernel.f90:196-196
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.25
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	2.25
CQA cycles if fully vectorized	0.44
Front-end cycles	1.25
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.25
P5 cycles	0.00
P6 cycles	0.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	10.00
Nb uops	10.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	0.00
Bytes prefetched	0.00
Bytes loaded	0.00
Bytes stored	0.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	14.29
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	50.00
Vector-efficiency ratio all	23.21
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	25.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	18.75

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel._omp_fn.0
Source file and lines	advec_mom_kernel.f90:190-196
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/advec_mom_kernel.f90:190,196.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.25 to 1.00 cycles (2.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is probably not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.25 to 0.44 cycles (5.14x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	10
loop length	40
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	0.50	0.50	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.25
Data deps.	1.00
Overall L1	2.25

Vectorization ratios

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.25 cycles. At this rate:

ASM code

In the binary file, the address of the loop is: 4212f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	Latency	Recip. throughput
ADD W7, W7, #1	1	0	0	0.25	0.25	0.25	0.25	1	0.25
SUB X27, X3, #8	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ORR P0.B, P8/Z, P8.B, P8.B	1	0	0	0	0	1	0	1	1
ADD X16, X4, X3	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ADD X28, X3, X10	1	0	0	0.25	0.25	0.25	0.25	1	0.25
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ADD X3, X3, X13	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ADD X14, X14, X12	1	0	0	0.25	0.25	0.25	0.25	1	0.25
CMP W9, W7	1	0	0	0.25	0.25	0.25	0.25	1	0.33
B.GT 4212f0 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0xcb0>	1	0.50	0.50	0	0	0	0	1	0.50

Function	advec_mom_kernel._omp_fn.0
Source file and lines	advec_mom_kernel.f90:190-196
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/169-814-4157/intel/CloverLeaf/build/CloverLeaf/CloverLeaf_ref/kernels/advec_mom_kernel.f90:190,196.

Warnings:
Non-innermost loop: analyzing only self part (ignoring child loops).

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 2.25 to 1.00 cycles (2.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is probably not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.25 to 0.44 cycles (5.14x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop does not load or store any data.

General properties

nb instructions	10
loop length	40
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	0.50	0.50	2.25	2.25	2.25	2.25	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	1.25
Data deps.	1.00
Overall L1	2.25

Vectorization ratios

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.25 cycles. At this rate:

ASM code

In the binary file, the address of the loop is: 4212f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	Latency	Recip. throughput
ADD W7, W7, #1	1	0	0	0.25	0.25	0.25	0.25	1	0.25
SUB X27, X3, #8	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ORR P0.B, P8/Z, P8.B, P8.B	1	0	0	0	0	1	0	1	1
ADD X16, X4, X3	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ADD X28, X3, X10	1	0	0	0.25	0.25	0.25	0.25	1	0.25
MOVZ X0, #0	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ADD X3, X3, X13	1	0	0	0.25	0.25	0.25	0.25	1	0.25
ADD X14, X14, X12	1	0	0	0.25	0.25	0.25	0.25	1	0.25
CMP W9, W7	1	0	0	0.25	0.25	0.25	0.25	1	0.33
B.GT 4212f0 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0xcb0>	1	0.50	0.50	0	0	0	0	1	0.50

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code