OV - exec - Loop 138

	Loop Id: 138	Module: exec	Source: advec_cell_kernel.f90:202-246 [...]	Coverage: 3.69%

0x41e6a8 LDR	D27, [X14, X1,LSL #3]    [3]

0x41e6ac ORR	X5, XZR, X8

0x41e6b0 ORR	X9, XZR, X17

0x41e6b4 ORR	X7, XZR, X13

0x41e6b8 ORR	X12, XZR, X8

0x41e6bc FCMPE	D27, #0

0x41e6c0 B.GT	41e6dc

0x41e6c4 CMP	W28, W20

0x41e6c8 CSEL	W5, W28, W20, #13

0x41e6cc SBFM	X12, X5, #0, #31

0x41e6d0 ORR	X9, XZR, X12

0x41e6d4 ORR	X7, XZR, X8

0x41e6d8 ORR	X5, XZR, X13

0x41e6dc MADD	X2, X24, X5, X21

0x41e6e0 FABS	D28, D27

0x41e6e4 ADD	X4, X19, X1

0x41e6e8 MADD	X3, X23, X5, X19

0x41e6ec ADD	X6, X25, X12

0x41e6f0 LDR	D29, [X18, X8,LSL #3]    [7]

0x41e6f4 MADD	X12, X23, X7, X4

0x41e6f8 MOVI	D0, #0

0x41e6fc ADD	X2, X2, X1

0x41e700 MADD	X4, X23, X9, X4

0x41e704 LDR	D30, [X26, X6,LSL #3]    [4]

0x41e708 ADD	X3, X3, X1

0x41e70c LDR	D31, [X11, X2,LSL #3]    [9]

0x41e710 LDR	D4, [X0, X3,LSL #3]    [10]

0x41e714 LDR	D3, [X0, X12,LSL #3]    [5]

0x41e718 FDIV	D18, D29, D30

0x41e71c LDR	D2, [X0, X4,LSL #3]    [2]

0x41e720 FDIV	D1, D28, D31

0x41e724 FSUB	D19, D3, S4

0x41e728 FSUB	D22, D4, S2

0x41e72c FCMPE	D19, D0

0x41e730 FABS	D20, D19

0x41e734 FMUL	D23, D22, D19

0x41e738 FABS	D21, D22

0x41e73c FCSEL	D24, D6, D5, #9

0x41e740 FCMPE	D23, D0

0x41e744 FADD	D25, D1, D5

0x41e748 FSUB	D26, D16, S1

0x41e74c FMUL	D28, D18, D25

0x41e750 B.GT	41f134

0x41e754 FADD	D4, D0, D4

0x41e758 ADD	X6, X30, X1

0x41e75c MADD	X5, X22, X5, X6

0x41e760 MADD	X7, X22, X7, X6

0x41e764 MADD	X9, X22, X9, X6

0x41e768 FMUL	D27, D4, D27

0x41e76c STR	D27, [X15, X1,LSL #3]    [1]

0x41e770 FABS	D19, D27

0x41e774 LDR	D1, [X10, X5,LSL #3]    [6]

0x41e778 LDR	D22, [X10, X7,LSL #3]    [8]

0x41e77c LDR	D20, [X10, X9,LSL #3]    [12]

0x41e780 LDR	D21, [X0, X3,LSL #3]    [10]

0x41e784 FSUB	D24, D22, S1

0x41e788 LDR	D23, [X11, X2,LSL #3]    [9]

0x41e78c FSUB	D25, D1, S20

0x41e790 FCMPE	D24, #0

0x41e794 FABS	D29, D24

0x41e798 FMUL	D31, D25, D24

0x41e79c FABS	D30, D25

0x41e7a0 FCSEL	D2, D6, D5, #9

0x41e7a4 FCMPE	D31, #0

0x41e7a8 B.GT	41f108

0x41e7ac FADD	D1, D1, D17

0x41e7b0 FMUL	D27, D1, D27

0x41e7b4 STR	D27, [X16, X1,LSL #3]    [11]

0x41e7b8 ADD	X1, X1, #1

0x41e7bc CMP	W27, W1

0x41e7c0 B.GE	41e6a8

0x41f108 FMUL	D18, D21, D23

0x41f10c FMUL	D26, D26, D29

0x41f110 FMINNM	D0, D29, D30

0x41f114 FMADD	D28, D28, D30, D26

0x41f118 FDIV	D4, D19, D18

0x41f11c FMUL	D3, D28, D7

0x41f120 FMINNM	D19, D3, D0

0x41f124 FSUB	D22, D5, S4

0x41f128 FMUL	D20, D22, D2

0x41f12c FMADD	D1, D19, D20, D1

0x41f130 B	41e7b0

0x41f134 FMUL	D0, D26, D20

0x41f138 FSUB	D29, D5, S1

0x41f13c FMINNM	D30, D20, D21

0x41f140 FMADD	D31, D28, D21, D0

0x41f144 FMUL	D3, D29, D24

0x41f148 FMUL	D18, D31, D7

0x41f14c FMINNM	D2, D18, D30

0x41f150 FMUL	D0, D2, D3

0x41f154 B	41e754

/home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_cell_kernel.f90: 202 - 246

--------------------------------------------------------------------------------

202:         DO j=x_min,x_max

203:

204:           IF(vol_flux_y(j,k).GT.0.0)THEN

[...]

210:             upwind   =MIN(k+1,y_max+2)

[...]

216:           sigmat=ABS(vol_flux_y(j,k))/pre_vol(j,donor)

217:           sigma3=(1.0_8+sigmat)*(vertexdy(k)/vertexdy(dif))

218:           sigma4=2.0_8-sigmat

219:

220:           sigma=sigmat

221:           sigmav=sigmat

222:

223:           diffuw=density1(j,donor)-density1(j,upwind)

224:           diffdw=density1(j,downwind)-density1(j,donor)

225:           wind=1.0_8

226:           IF(diffdw.LE.0.0) wind=-1.0_8

227:           IF(diffuw*diffdw.GT.0.0)THEN

228:             limiter=(1.0_8-sigmav)*wind*MIN(ABS(diffuw),ABS(diffdw)&

229:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

230:           ELSE

231:             limiter=0.0

232:           ENDIF

233:           mass_flux_y(j,k)=vol_flux_y(j,k)*(density1(j,donor)+limiter)

234:

235:           sigmam=ABS(mass_flux_y(j,k))/(density1(j,donor)*pre_vol(j,donor))

236:           diffuw=energy1(j,donor)-energy1(j,upwind)

237:           diffdw=energy1(j,downwind)-energy1(j,donor)

238:           wind=1.0_8

239:           IF(diffdw.LE.0.0) wind=-1.0_8

240:           IF(diffuw*diffdw.GT.0.0)THEN

241:             limiter=(1.0_8-sigmam)*wind*MIN(ABS(diffuw),ABS(diffdw)&

242:               ,one_by_six*(sigma3*ABS(diffuw)+sigma4*ABS(diffdw)))

243:           ELSE

244:             limiter=0.0

245:           ENDIF

246:           ener_flux(j,k)=mass_flux_y(j,k)*(energy1(j,donor)+limiter)

Path /

Metric	Value
CQA speedup if no scalar integer	2.62
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.47
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	P6, P7, P8, P9,
Function	advec_cell_kernel._omp_fn.0
Source	advec_cell_kernel.f90:202-204,advec_cell_kernel.f90:210-210,advec_cell_kernel.f90:216-246
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.25
CQA cycles if no scalar integer	4.67
CQA cycles if FP arith vectorized	12.25
CQA cycles if fully vectorized	1.64
Front-end cycles	11.38
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	5.75
P2 cycles	5.75
P3 cycles	7.00
P4 cycles	5.50
P5 cycles	12.25
P6 cycles	12.25
P7 cycles	12.25
P8 cycles	12.25
P9 cycles	4.67
P10 cycles	4.67
P11 cycles	4.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	3.00 - 1.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	91.00
Nb uops	91.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.61
Nb FLOP add-sub	10.00
Nb FLOP mul	13.00
Nb FLOP fma	3.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.14
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.53
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.67

Metric	Value
CQA speedup if no scalar integer	2.62
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	7.47
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	P6, P7, P8, P9,
Function	advec_cell_kernel._omp_fn.0
Source	advec_cell_kernel.f90:202-204,advec_cell_kernel.f90:210-210,advec_cell_kernel.f90:216-246
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.25
CQA cycles if no scalar integer	4.67
CQA cycles if FP arith vectorized	12.25
CQA cycles if fully vectorized	1.64
Front-end cycles	11.38
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	5.75
P2 cycles	5.75
P3 cycles	7.00
P4 cycles	5.50
P5 cycles	12.25
P6 cycles	12.25
P7 cycles	12.25
P8 cycles	12.25
P9 cycles	4.67
P10 cycles	4.67
P11 cycles	4.67
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	3.00 - 1.50
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	91.00
Nb uops	91.00
Nb loads	NA
Nb stores	2.00
Nb stack references	0.00
FLOP/cycle	2.61
Nb FLOP add-sub	10.00
Nb FLOP mul	13.00
Nb FLOP fma	3.00
Nb FLOP div	3.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	9.14
Bytes prefetched	0.00
Bytes loaded	96.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	23.53
Vector-efficiency ratio load	25.00
Vector-efficiency ratio store	25.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	16.67

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_cell_kernel._omp_fn.0
Source file and lines	advec_cell_kernel.f90:202-246
Module	exec

The loop is defined in /home/hbollore/qaas-runs/170-309-0949/intel/CloverLeafFC/build/CloverLeafFC/CloverLeaf_ref/kernels/advec_cell_kernel.f90:202-204,210,216-246.

The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 8 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.25 to 4.67 cycles (2.63x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Your loop is not vectorized. Only 23% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 12.25 to 1.64 cycles (7.47x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 3 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

13: addition or subtraction (3 inside FMA instructions)
16: multiply (3 inside FMA instructions)
3: divide

The binary loop is loading 96 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.29 FP operations per loaded or stored byte.

General properties

nb instructions	91
loop length	364
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	5.75	5.75	7.00	5.50	12.25	12.25	12.25	12.25	4.67	4.67	4.67	0.00	0.00
cycles	3.00	3.00	5.75	5.75	7.00	5.50	12.25	12.25	12.25	12.25	4.67	4.67	4.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

3.00-1.50

Cycles summary

Front-end	11.38
Overall L1	12.25

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.25 cycles. At this rate:

8% of peak load performance is reached (7.84 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.31 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41e6a8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR D27, [X14, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ORR X5, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X9, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X7, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X12, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FCMPE D27, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GT 41e6dc <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x39c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W28, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
CSEL W5, W28, W20, #13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X12, X5, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X9, XZR, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X7, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X5, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X2, X24, X5, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FABS D28, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
ADD X4, X19, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X3, X23, X5, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X6, X25, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D29, [X18, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MADD X12, X23, X7, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
ADD X2, X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X4, X23, X9, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR D30, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X3, X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D31, [X11, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D4, [X0, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D3, [X0, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FDIV D18, D29, D30	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
LDR D2, [X0, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FDIV D1, D28, D31	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FSUB D19, D3, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D22, D4, S2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMPE D19, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FABS D20, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D23, D22, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FABS D21, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCSEL D24, D6, D5, #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMPE D23, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FADD D25, D1, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D26, D16, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D28, D18, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
B.GT 41f134 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0xdf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FADD D4, D0, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
ADD X6, X30, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X5, X22, X5, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X7, X22, X7, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X9, X22, X9, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FMUL D27, D4, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR D27, [X15, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
FABS D19, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR D1, [X10, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D22, [X10, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D20, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D21, [X0, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSUB D24, D22, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR D23, [X11, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSUB D25, D1, S20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMPE D24, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FABS D29, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D31, D25, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FABS D30, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCSEL D2, D6, D5, #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMPE D31, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GT 41f108 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0xdc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FADD D1, D1, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D27, D1, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR D27, [X16, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W27, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 41e6a8 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMUL D18, D21, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL D26, D26, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMINNM D0, D29, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMADD D28, D28, D30, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FDIV D4, D19, D18	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FMUL D3, D28, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMINNM D19, D3, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D22, D5, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D20, D22, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D1, D19, D20, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
B 41e7b0 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMUL D0, D26, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FSUB D29, D5, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMINNM D30, D20, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMADD D31, D28, D21, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D3, D29, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL D18, D31, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMINNM D2, D18, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D0, D2, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
B 41e754 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x414>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	advec_cell_kernel._omp_fn.0
Source file and lines	advec_cell_kernel.f90:202-246
Module	exec

Ignoring paths for analysis
Too many paths. Rerun with max-paths=8
RecMII not computed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = max(0,x) (Fortran instrinsic procedure)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.25 to 4.67 cycles (2.63x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this loop

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one:
- recompile with fassociative-math (included in Ofast or ffast-math) to extend loop vectorization to FP reductions.
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: Fortran storage order is column-major: do i do j a(i,j) = b(i,j) (slow, non stride 1) => do i do j a(j,i) = b(i,j) (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

FMA

Detected 3 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

13: addition or subtraction (3 inside FMA instructions)
16: multiply (3 inside FMA instructions)
3: divide

The binary loop is loading 96 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.29 FP operations per loaded or stored byte.

General properties

nb instructions	91
loop length	364
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

11.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	3.00	3.00	5.75	5.75	7.00	5.50	12.25	12.25	12.25	12.25	4.67	4.67	4.67	0.00	0.00
cycles	3.00	3.00	5.75	5.75	7.00	5.50	12.25	12.25	12.25	12.25	4.67	4.67	4.67	0.00	0.00

Execution ports to units layout:

P0:
P1:
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P7 (128 bits): VPU, ALU, FP store data
P8 (128 bits): VPU, ALU, DIV/SQRT
P9 (128 bits): ALU, VPU
P10 (256 bits): store address, load
P11 (256 bits): store address, load
P12 (256 bits): load
P13 (64 bits): store data
P14 (64 bits): store data

Cycles executing div or sqrt instructions

3.00-1.50

Cycles summary

Front-end	11.38
Overall L1	12.25

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.25 cycles. At this rate:

8% of peak load performance is reached (7.84 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.31 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41e6a8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR D27, [X14, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ORR X5, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X9, XZR, X17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X7, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X12, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
FCMPE D27, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GT 41e6dc <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x39c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMP W28, W20	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
CSEL W5, W28, W20, #13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
SBFM X12, X5, #0, #31	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X9, XZR, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X7, XZR, X8	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ORR X5, XZR, X13	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X2, X24, X5, X21	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FABS D28, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
ADD X4, X19, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X3, X23, X5, X19	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
ADD X6, X25, X12	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D29, [X18, X8,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
MADD X12, X23, X7, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MOVI D0, #0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
ADD X2, X2, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X4, X23, X9, X4	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
LDR D30, [X26, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X3, X3, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDR D31, [X11, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D4, [X0, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D3, [X0, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FDIV D18, D29, D30	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
LDR D2, [X0, X4,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FDIV D1, D28, D31	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FSUB D19, D3, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D22, D4, S2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMPE D19, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FABS D20, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D23, D22, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FABS D21, D22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCSEL D24, D6, D5, #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMPE D23, D0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FADD D25, D1, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D26, D16, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D28, D18, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
B.GT 41f134 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0xdf4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FADD D4, D0, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
ADD X6, X30, X1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
MADD X5, X22, X5, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X7, X22, X7, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
MADD X9, X22, X9, X6	1	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1
FMUL D27, D4, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR D27, [X15, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
FABS D19, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR D1, [X10, X5,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D22, [X10, X7,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D20, [X10, X9,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D21, [X0, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSUB D24, D22, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
LDR D23, [X11, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FSUB D25, D1, S20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCMPE D24, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
FABS D29, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D31, D25, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FABS D30, D25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FCSEL D2, D6, D5, #9	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	2	0.50
FCMPE D31, #0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	2	1
B.GT 41f108 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0xdc8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FADD D1, D1, D17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D27, D1, D27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
STR D27, [X16, X1,LSL #3]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
ADD X1, X1, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
CMP W27, W1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GE 41e6a8 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x368>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMUL D18, D21, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL D26, D26, D29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMINNM D0, D29, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMADD D28, D28, D30, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FDIV D4, D19, D18	1	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	1-0.50
FMUL D3, D28, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMINNM D19, D3, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FSUB D22, D5, S4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D20, D22, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMADD D1, D19, D20, D1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
B 41e7b0 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x470>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
FMUL D0, D26, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FSUB D29, D5, S1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMINNM D30, D20, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMADD D31, D28, D21, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMUL D3, D29, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMUL D18, D31, D7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
FMINNM D2, D18, D30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25
FMUL D0, D2, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25
B 41e754 <__advec_cell_kernel_module_MOD_advec_cell_kernel._omp_fn.0+0x414>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Code clean check

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Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code